HP ProLiant BL460c Gen8 NUMA Architecture?

[chuckk281]

Ron had a BL460c Gen8 architecture question:

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From what I can tell the BL460G8 is using a NUMA architecture.  But I can’t find this specifically stated anywhere.  Can somebody verify?

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Reply from Armand:

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It’s true that doing an in depth look to the Intel documentation related to E5, NUMA is not often, or never mentioned.

However, the existence of QPI (Quick Path Interconnect) and IMC (Integrated Memory Controller) in the Intel E5 architecture, lead to assume it is a NUMA architecture when used in a DP or MP type of server.

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Also a reply from Chris:

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A simple test that everybody can do is to find out from QuickSpecs if on a 2 or more socket server you can configure maximum memory with only one processor present. 

If the answer is no, then it is NUMA by definition, because it means that memory access goes through controllers on the CPU die.

And this has been the case certainly for ProLiants since G6 if not earlier.

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Some info and FAQs on NUMA from  http://lse.sourceforge.net/numa/faq/ :

Frequently Given Answers:

1. What does NUMA stand for?
   NUMA stands for Non-Uniform Memory Access.
   
   
2. OK, So what does Non-Uniform Memory Access really mean to me?
   Non-Uniform Memory Access means that it will take longer to access some regions of memory than others. This is due to the fact that some regions of memory are on physically different busses from other regions. For a more visual description, please refer to the section on NUMA architeture implementations. Also, see the real-world analogy for the NUMA architecture. This can result in some programs that are not NUMA-aware performing poorly. It also introduces the concept of local and remote memory.
   
   
3. What is the difference between NUMA and SMP?
   The NUMA architecture was designed to surpass the scalability limits of the SMP architecture. With SMP, which stands for Symmetric Multi-Processing, all memory access are posted to the same shared memory bus. This works fine for a relatively small number of CPUs, but the problem with the shared bus appears when you have dozens, even hundreds, of CPUs competing for access to the shared memory bus. NUMA alleviates these bottlenecks by limiting the number of CPUs on any one memory bus, and connecting the various nodes by means of a high speed interconnect.
   
   
4. What is the difference between NUMA and ccNUMA?
   The difference is almost nonexistent at this point. ccNUMA stands for Cache-Coherent NUMA, but NUMA and ccNUMA have really come to be synonymous. The applications for non-cache coherent NUMA machines are almost non-existent, and they are a real pain to program for, so unless specifically stated otherwise, NUMA actually means ccNUMA.

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