make's inference rule to compile C files

[Stefan Paitoni]

I have difficulties to define the correct inference rule in a makefile to compile C files whose generated object files are in an other directory. It seems that the following inference rule demands (to be executed) that the C file MUST be in the same directory as object file. I want my object files to be in another directory than my source files. This rule does NOT work :
.c.o :
/opt/ansic/bin/cc ....
mv ... ../tmp_obj

EXEC : ../tmp_obj/test.o

I dont find any way to tell 'make' that the source is in the current directory and not in ../tmp_obj directory.

[Sergiy Nevstruyev]

Hi Stefan,
try this one:

OD = ./obj
OD_OBJS = $(OD)/test.o
OBJS = test.o

main: moveobjs $(OBJS) removeobjs

moveobjs:
cp $(OD_OBJS) . || echo ""

.c.o:
gcc -o $(OD)/$@ -c $<

removeobjs:
rm $(OBJS)

Sergej.

[Stefan Paitoni]

Thanks guys.

I found the solution :

VPATH=:

.c.o :
...