hp StorageWorks enterprise virtual array Event Text Description File © Copyright 2001-2005 Hewlett-Packard Company WARNING: Modification of this file may cause Enterprise Storage Management Software to improperly translate event information Model number string: HSV200 Software version number string: 6110 Baselevel build string: CR0ECA Structure Format: Endian Little COUPLED CRASH CONTROL CODES: Coupled Crash Control Code: 0 Other HSV200 controller should not perform a coupled crash. Coupled Crash Control Code: 1 Other HSV200 controller should perform a coupled crash. DUMP/RESTART CONTROL CODES: Dump/Restart Control Code: 0 Perform crash dump then restart. Dump/Restart Control Code: 1 Do not perform crash dump, just restart. Dump/Restart Control Code: 2 Perform crash dump and do not restart. Dump/Restart Control Code: 3 Do not perform crash dump and do not restart. SEVERITY LEVEL CODES: Severity Level Code: 0 Normal -- informational in nature. Severity Level Code: 1 Critical -- failure or failure imminent. Severity Level Code: 2 Warning -- not failed but attention recommended or required. Severity Level Code: 3 Undetermined -- more information needed to determine severity. CORRECTIVE ACTION CODES: Corrective Action Code: 0 No action necessary. Corrective Action Code: 1 An unrecoverable hardware detected fault occurred or an unrecoverable software inconsistency was detected, proceed with HSV200 controller support avenues. Corrective Action Code: 2 Inconsistent/erroneous information received from the operating system. Proceed with operating system software support avenues. Corrective Action Code: 3 Follow the recommended corrective action shown in the termination corrective action code of this event's detailed information. The cause of the controller termination associated with this controller event can only be determined by obtaining the detailed information of the associated termination event. To obtain that information follow Corrective Action [[06]]. Corrective Action Code: 4 Follow the recommended corrective action described in the recursing termination event. Perform these steps to obtain that termination event's information: Corrective Action Code: 5 Follow the recommended corrective action described in the termination event reported by the other controller that caused this termination event to occur. Perform these steps to obtain that termination event's information: Corrective Action Code: 6 Perform these steps to obtain the termination information associated with this controller event: Corrective Action Code: 7 A significant hardware detected fault occurred or a significant software inconsistency was detected. Accumulate information to report to HSV200 controller engineering. Corrective Action Code: 8 A significant hardware detected fault occurred or a significant software inconsistency was detected. Accumulate information to report to HSV200 controller engineering. Corrective Action Code: 9 Determine power loss cause and take appropriate action to ensure power is restored and maintained. Corrective Action Code: a A portion of low memory is purposely set to produce an uncorrectable memory error in order to detect low memory access violations made by the HSV200 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.). Unfortunately, there is no method available for immediately distinguishing a low memory access violation from an uncorrectable memory error that occurs elsewhere in memory. However, the memory diagnostics that are executed following controller restart will immediately terminate HSV200 controller operation if any portion of memory is found defective. In that case perform corrective action [[20]]. If defective memory is not found during HSV200 controller restart and this termination event is again reported, the most likely cause is a software induced low memory access violation. In that case perform corrective action [[01]]. Corrective Action Code: b The GLUE eeprom on this HSV200 controller has been reprogrammed with new GLUE chip code. This HSV200 controller must be power cycled to complete the GLUE chip code update procedure.

In addition, this HSV200 controller's functional code has been updated. Controller operations will continue with the old functional code until the power cycle necessary to complete the GLUE chip code update is performed. NOTE: If a spontaneous termination of controller operations occurs before the controller's power is cycled, this HSV200 controller will be running new functional code with old GLUE code after the controller restarts which will result in a termination of controller operation. To recover from that situation this HSV200 controller must be power cycled. After doing so, this HSV200 controller will be running new functional code with new GLUE code after the controller restarts which will allow normal controller operations to resume. Corrective Action Code: 20 Replace the HSV200 controller Field Replaceable Unit (FRU). Note that the FRU must be a single power supply type if so indicated in this event's detailed information. Corrective Action Code: 22 Replace the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge. CAUTION: The information described in corrective action [[38]] must be understood before attempting a cache battery replacement. Corrective Action Code: 23 Replace the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge. CAUTION: The information described in corrective action [[38]] must be understood before attempting a cache battery replacement. Corrective Action Code: 24 Replace the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge. Corrective Action Code: 25 Replace the "2" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge. Corrective Action Code: 26 Replace the "1" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply closest to the cache battery door hinge. Corrective Action Code: 27 Replace the "2" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply farthest from the cache battery door hinge. Corrective Action Code: 28 Reinstall the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge. Corrective Action Code: 29 Reinstall the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge. Corrective Action Code: 2a Reinstall the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge. Corrective Action Code: 2b Reinstall the "2" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge. Corrective Action Code: 2c Reinstall the "1" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply closest to the cache battery door hinge, or restore AC power. Corrective Action Code: 2d Reinstall the "2" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply farthest from the cache battery door hinge, or restore AC power. Corrective Action Code: 2e Reduce the ambient temperature in the vicinity of the indicated HSV200 controller. Corrective Action Code: 2f Ensure that both batteries in the indicated HSV200 controller are installed and functioning normally. A cache battery failure will be indicated by the red battery status LED located on the OCP display. If that LED is on, open the battery compartment door and check for the amber status LED in the lower right corner of each battery assembly. If the amber status LED is ONLY on in the battery assembly closest to the battery compartment door hinge, perform corrective action [[22]]. If the amber status LED is ONLY on in the battery assembly farthest from the cache battery door hinge, perform corrective action [[23]]. If the amber status LED is on in BOTH battery assemblies, perform [[22]] and [[23]] simultaneously. Corrective Action Code: 30 GBIC SFF Serial ID Data check code failure. Corrective action: Try re-seating the GBIC, if failure persists, replace the GBIC, lastly perform corrective action [[20]]. Corrective Action Code: 36 The temperature on the HSV200 controller has become critical. Proceed with corrective action [[2e]] and restart the controller. Corrective Action Code: 37 The temperature on the HSV200 controller could not be accurately determined possibly due to faulty operation of a temperature sensor or the temperature acquisition communication path. If the problem persists, perform Corrective Action [[20]]. Corrective Action Code: 38 Before performing cache battery replacement the following must be understood:

Corrective Action Code: 39 If this event is an isolated occurrence, then no further action is necessary. If this event occurs more than once in a three month period, perform Corrective Action [[20]]. Corrective Action Code: 3a Insert and re-seat the GBIC. If failure persists, replace the GBIC, or lastly perform Corrective Action [[20]]. Corrective Action Code: 3b Isolated occurrences of this event may be safely ignored. If this event occurs more than once in a three month period, perform Corrective Action [[20]]. Corrective Action Code: 40 Replace the indicated physical disk drive. Corrective Action Code: 41 Reinstall the indicated physical disk drive or install a drive blank. Corrective Action Code: 42 Perform these steps in an attempt to clear the error: If the error persists, perform Corrective Action [[40]]. Corrective Action Code: 43 Perform these steps in an attempt to clear the error: Corrective Action Code: 44 A Fibre Channel port has failed. This may be caused by a failure on the indicated HSV200 controller, or the coprresponding Fibre Channel Switch. Proceed with corrective action [[01]]. Corrective Action Code: 46 Numerous failures have occurred while attempting to communicate with a particular Physical Disk Drive on a particular Fibre Channel port. The HSV200 controller will attempt to use an alternate Fibre Channel port to communicate with that Physical Disk Drive. If communication fails on the alternate Fibre Channel port, that Physical Disk Drive will be rendered inoperable. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 47 Dropped frames are potential indications of an impending Fibre Channel port or physical disk drive failure when they occur excessively. If frame drop becomes excessive, the indicated Fibre Channel port or the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 48 Unexpected work from a physical disk drive is an indication of an impending drive failure. If unexpected work becomes excessive, the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 49 Bad ALPAs are indications of an impending physical disk drive failure. If the number of bad ALPAs becomes excessive, the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 4a Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV200 controller Host Port or Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cable, faulty Drive Enclosure I/O module, or faulty Fibre Channel Switch. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 4c This event is probably a symptom of another problem. Check for failed Fibre Channel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the same rack or loop. If this is an isolated occurrence of this event, ungroup the indicated physical disk drive and remove it from the system. Corrective Action Code: 4d Load the latest physical disk drive firmware superfile for the physical disk drive type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be ungrouped and removed. Using a superfile that updates the controller approved firmware table may be sufficient to correct the problem. Corrective Action Code: 4e This event is probably a symptom of another problem. Check for failed Fibre Channel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the same rack or loop. Corrective Action Code: 4f Remove the indicated physical disk drive and install a drive blank. Corrective Action Code: 50 Delete the indicated inoperative Snapshot Logical Disk. Corrective Action Code: 51 Evaluate previously reported Physical Device, Device Enclosure, and Logical Disk events to determine root cause and corrective action. Corrective Action Code: 52 Delete the indicated inoperative Logical Disk, unless an instant restore operation is possible. Corrective Action Code: 5f Unable to communicate to the destination controllers, or through a specific path to the destination. Check to see if the destination controllers have malfunctioned, and perform the repair actions indicated in event reports found for the destination controllers. In addition, check for a malfunction that may have occurred in the Fibre Channel fabric between the sites. Corrective Action Code: 60 Unable to communicate to the indicated source virtual disk, because the virtual disk or another member in the Data Replication Group malfunctioned. Perform the repair actions indicated in event reports found for that source virtual disk or another virtual disk member in that Data Replication Group. Corrective Action Code: 61 Unable to communicate to the indicated destination virtual disk on the remote Storage System because the virtual disk malfunctioned. Perform the repair actions indicated in event reports found for that destination virtual disk on the remote Storage System. Corrective Action Code: 62 The Data Replication Log for the specified Data Replication Group has insufficient space to grow the log. A copy resynchronization will be started when data replication can resume. Evaluate whether sufficient disk storage has been made available for the log to grow in capacity. If necessary, add new volumes to the Disk Group. Corrective Action Code: 63 The Data Replication Source Site and the Data Replication Destination Site cannot communicate because the software versions are incompatible. Communication will automatically continue when both sites are at compatible software levels. Corrective Action Code: 64 Check the Data Replication Destination Site for problems with physical disk drives or fibre channel loops. The Data Replication Destination Site may also be temporarily experiencing higher than usual levels of disk related activity. Corrective Action Code: 65 Check the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not the case then restart the Data Replication Destination Site controllers. Then restart the Data Replication Source Site controllers. Corrective Action Code: 66 Check both the Data Replication Source Site and the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not the case then restart the Data Replication Source Site controllers. IF you have already taken this action and are receiving this event for a second time then restart the Data Replication Destination Site controllers instead. Corrective Action Code: 67 Check link speed and quality between the Data Replication Source Site controllers and the Data Replication Destination Site controllers. Corrective Action Code: 68 Reduce the number of controller pairs on the fabric to the supported maximum. Corrective Action Code: 69 Check fabric switch settings and inter site link quality between the Data Replication Source Site controllers and the Data Replication Destination Site controllers. Corrective Action Code: 80 Perform these steps in an attempt to clear the error: If the error persists, immediately (within 7 minutes) perform Corrective Action [[81]]. If that action cannot be performed immediately, perform Corrective Action [[85]] immediately. Corrective Action Code: 81 Replace the indicated drive enclosure power supply. Hewlett-Packard recommends not removing a defective drive enclosure power supply until a replacement drive enclosure power supply is available. Corrective Action Code: 82 Perform these steps in an attempt to clear the error: If the error persists, perform Corrective Action [[83]]. Corrective Action Code: 83 Replace the indicated drive enclosure blower. CAUTION: Removing a blower automatically closes flaps over the power supply blower opening. However, the air flow within the enclosure changes and can cause an over temperature condition. Hewlett-Packard recommends not removing a defective blower until a replacement blower is available. Corrective Action Code: 84 Immediately replace one of the missing drive enclosure blowers. The other blower should be replaced as soon as possible. If a blower is not available for immediate replacement, perform Corrective Action [[85]] immediately. Corrective Action Code: 85 If the problem cannot be corrected, the Enterprise Virtual Array should be shut down to: CAUTION: This is a drastic measure that will stop all Enterprise Virtual Array operations. Hewlett-Packard recommends using this procedure only when necessary to protect a drive enclosure from overheating or to clear drive enclosure errors that cannot otherwise be cleared. Corrective Action Code: 86 If the indicated drive enclosure element's temperature sensor is high, follow these steps to correct the over temperature condition: If the indicated drive enclosure element's temperature sensor is low, follow this step to correct the below temperature condition: After performing the actions described above observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists. Corrective Action Code: 87 Immediately perform Corrective Action [[86]]. If the problem persists after performing those actions, perform Corrective Action [[85]] immediately. Corrective Action Code: 88 Reset the indicated Drive Enclosure Environmental Monitoring Unit using the following procedure: If the problem persists, perform Corrective Action [[89]]. Corrective Action Code: 89 Replace the indicated Drive Enclosure Environmental Monitoring Unit. Corrective Action Code: 8a The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[89]]. Corrective Action Code: 8b Perform these steps in an attempt to clear the error: If the problem still persists, then perform Corrective Action [[89]]. Corrective Action Code: 8c The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[8b]]. Corrective Action Code: 8d Initialize the indicated drive enclosure by: Corrective Action Code: 8e This error may be caused by a defective drive enclosure address bus cable, an incorrectly connected cable, or a defective enclosure address bus junction box. Perform these steps in an attempt to clear the error: Corrective Action Code: 8f Perform these steps in an attempt to clear the error: Corrective Action Code: 90 Perform these steps in an attempt to clear the error: Corrective Action Code: 91 Replace the indicated drive enclosure. Corrective Action Code: 92 The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[91]]. Corrective Action Code: 93 Replace the indicated drive enclosure I/O module. Corrective Action Code: 94 The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[93]]. Corrective Action Code: 95 Reset the indicated device enclosure I/O module using the following procedure: If the problem persists, perform Corrective Action [[93]]. Corrective Action Code: 96 The Drive Enclosure Environmental Monitoring Unit has requested new Drive Enclosure Environmental Monitoring Unit code. The code could not be found. Upgrade with the latest revision of the Drive Enclosure Environmental Monitoring Unit code update. Corrective Action Code: 97 Ensure all HSV200 controllers are connected to the enclosure address bus. If all controllers are connected, then replace the Y-cable and restart the controllers. Corrective Action Code: 98 Reduce the number of drive enclosures. Corrective Action Code: 99 Ensure that each drive enclosure I/O module is connected to the correct Fibre Channel port. Corrective Action Code: 9a Ensure A/C input to the rack PDU is intact, otherwise perform [[81]]. Corrective Action Code: 9b If the element is not redetected within 10 minutes, the indicated Drive Enclosure Environmental Monitoring Unit may need to be replaced. The problem may be caused by the controller not being able to communicate with the drives in this enclosure for reasons that are unrelated to the Drive Enclosure Environmental Monitoring Unit. Corrective Action Code: 9c Ungroup and replace the physical disk drive. If this does not correct the problem, replace the Drive Enclosure Environmental Monitoring Unit and power cycle the physical disk drive. If the problem is persistent, replace Device Enclosure. Corrective Action Code: b4 Add new volumes to the Disk Group or increase the Disk Group occupancy alarm level threshold. Corrective Action Code: b5 Add new volumes to the Disk Group or delete unwanted logical disks from Disk Group. Corrective Action Code: b6 To restore the Disk Group to a Single Point of Failure Robust Configuration add more physical disk drives or rearrange the existing Single Point of Failure Robust Configuration to ensure the physical disk drives members are on different Fibre Channel device enclosures. Corrective Action Code: b9 Evaluate previously reported events associated with this HSV200 controller to determine root cause and corrective action. Corrective Action Code: ba Check to see if this HSV200 controller has suffered a power failure. If so, perform Corrective Action [[09]]. Otherwise, perform Corrective Action [[b9]]. Corrective Action Code: bf Evaluate previously reported Device or Device Enclosure events that related to the Physical Disk Drive that is associated with this Volume to determine root cause and corrective action. Corrective Action Code: c3 Evaluate previously reported Device, Device Enclosure, and Host events to determine root cause and corrective action. If the problem persists, follow Corrective Action [[20]]. Corrective Action Code: c4 Load the latest physical disk drive firmware superfile for the physical disk drive type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be ungrouped and removed. Using a superfile that updates the controller approved firmware table may be sufficient to correct the problem. Corrective Action Code: c5 Check enclosure address bus cable connections between Drive Enclosure Environmental Monitoring Unit and nodes. If cabling is not the problem, the node or Drive Enclosure Environmental Monitoring Unit may need to be replaced. Corrective Action Code: c8 Replace the "0" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement. Corrective Action Code: c9 Replace the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement. Corrective Action Code: ca Replace the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement. Corrective Action Code: cb Replace the "3" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement. Corrective Action Code: cc Reinstall the "0" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly. Corrective Action Code: cd Reinstall the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly. Corrective Action Code: ce Reinstall the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly. Corrective Action Code: cf Reinstall the "3" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly. Corrective Action Code: d0 Ensure the required number of batteries in the indicated HSV200 controller are installed and functioning normally. Each battery assembly has a green LED located to the side of a battery symbol label and an amber LED located to the side of a caution symbol label. A cache battery failure will be indicated when the amber LED is on and the green LED is off. If the upper left battery assembly is failed, perform corrective action [[c8]]. If the lower left battery assembly is failed, perform corrective action [[c9]]. If the upper right battery assembly is failed, perform corrective action [[ca]]. If the lower right battery assembly is failed, perform corrective action [[cb]]. Corrective Action Code: d1 Before performing cache battery replacement the following must be understood: Corrective Action Code: d2 Replace the "0" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blower. Corrective Action Code: d3 Replace the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower. Corrective Action Code: d4 Reinstall the "0" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blower. Corrective Action Code: d5 Reinstall the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower. Corrective Action Code: d6 Verify AC connection integrity of "0" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply. Replace assembly if AC connection is good and malfunction persists. Corrective Action Code: d7 Verify AC connection integrity of "1" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply. Replace assembly if AC connection is good and malfunction persists. Corrective Action Code: d8 Reinstall the "0" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply. Corrective Action Code: d9 Reinstall the "1" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply. Corrective Action Code: da If this event is an isolated occurrence, then no further action is necessary. Perform these steps in an attempt to clear persistent occurrences: Corrective Action Code: db This event indicates a SLAVE ROHS compliant controller is being force loaded from the MASTER with code that is inappropriate for this hardware. This will continue until this controller is made MASTER or the current master is upgraded to the appropriate level of code that will run on both controllers. SOFTWARE COMPONENT ID CODES: Software Component ID Code: 1 Executive Services Software Component ID Code: 2 Cache Management Component Software Component ID Code: 3 Storage System State Services Software Component ID Code: 4 Fault Manager Software Component ID Code: 6 Fibre Channel Services Software Component ID Code: 7 Container Services Software Component ID Code: 8 Raid Services Software Component ID Code: 9 Storage System Management Interface Software Component ID Code: b System Services (DFP, XMFC, etc. processing) Software Component ID Code: c Data Replication Manager Component Software Component ID Code: d Disk Enclosure Environmental Monitoring Unit Services Software Component ID Code: e System Data Center Software Component ID Code: 42 Host Port Software Component ID Code: 83 Diagnostic Operations Generator Software Component ID Code: 84 Diagnostic Runtime Services (Scrubbing, UPS, temp/battery/voltage monitoring, etc.) EVENT CODES: Event Code: 0102000d Severity: Normal -- informational in nature. A time change occurred. Event Code: 0300200a Severity: Critical -- failure or failure imminent. An HSV200 controller has failed in communicating with the Cabinet (Rack) Bus Interface Controller. Event Code: 0301400b Severity: Critical -- failure or failure imminent. A physical disk drive has been rendered inoperable. Event Code: 03024f0b Severity: Warning -- not failed but attention recommended or required. A physical disk drive will not be used because the maximum number of physical disk drives already exist in the current Storage System. Event Code: 0303000a Severity: Normal -- informational in nature. An HSV200 controller has begun booting. Event Code: 0304000a Severity: Normal -- informational in nature. An HSV200 controller has finished the process of bringing the Storage System online. Event Code: 0305000a Severity: Normal -- informational in nature. An HSV200 controller has been joined into the Storage System. Event Code: 0306000a Severity: Normal -- informational in nature. An HSV200 controller has been ousted from the Storage System. Event Code: 0307000a Severity: Normal -- informational in nature. An HSV200 controller is now the Storage System Master. Event Code: 0308000a Severity: Normal -- informational in nature. An HSV200 controller has been brought into the Storage System. Event Code: 03090018 Severity: Normal -- informational in nature. The Redundant Storage Set has started migrating members. Event Code: 030a0018 Severity: Normal -- informational in nature. The Redundant Storage Set has finished migrating members. Event Code: 030b4f0b Severity: Warning -- not failed but attention recommended or required. A physical disk drive has failed during Storage System realization. Event Code: 030c001e Severity: Normal -- informational in nature. The DebugFlags and/or PrintFlags have changed. Event Code: 030d001e Severity: Normal -- informational in nature. Process with work during CSM reset: Event Code: 030e070b Severity: Warning -- not failed but attention recommended or required. About to write ID block to wrong physical disk drive. Event Code: 030f001e Severity: Normal -- informational in nature. RoHS Status of the HSV200 controller has been determined. Event Code: 0310001f Severity: Normal -- informational in nature. A Storage System Virtual Disk has changed controller mastership. Event Code: 03114420 Severity: Critical -- failure or failure imminent. A Fibre Channel Switch responded to a fabric port login. The corresponding device Fibre Channel port on the specified HSV200 controller has been failed. Event Code: 03120021 Severity: Normal -- informational in nature. A Logical Disk attach operation has completed. Refer to event details for completion status. Event Code: 03130021 Severity: Normal -- informational in nature. A snapclone Logical Disk has completed the unsharing operation. Event Code: 03140021 Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the detach operation. Event Code: 03150021 Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the fracture operation. Event Code: 03160021 Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the synchronization operation. Event Code: 03170021 Severity: Normal -- informational in nature. A Logical Disk has completed the instant restore operation. Event Code: 0400031c Severity: Undetermined -- more information needed to determine severity. HSV200 controller operation was terminated due to an unrecoverable event detected by either software or hardware or due to an action initiated via the Storage System Management Interface. Event Code: 0401031c Severity: Undetermined -- more information needed to determine severity. This HSV200 controller has received a last gasp message from another HSV200 controller prior to it terminating operation. Event Code: 04020101 Severity: Critical -- failure or failure imminent. A machine check occurred while a termination event was being processed. Event Code: 04030102 Severity: Critical -- failure or failure imminent. An unexpected event occurred while a termination event was being processed. Event Code: 04040003 Severity: Normal -- informational in nature. The Storage System Event Log validation completed successfully. Event Code: 04050003 Severity: Normal -- informational in nature. The Storage System Event Log validation failed. Event Code: 04060803 Severity: Normal -- informational in nature. Local event reports were lost due to an insufficient supply of Event Log Packets on this HSV200 controller. Event Code: 04070803 Severity: Normal -- informational in nature. Remote event reports were lost due to an insufficient supply of Event Log Packets on this HSV200 controller. Event Code: 04080003 Severity: Normal -- informational in nature. The Storage System Termination Event Log has become inaccessible. Event Code: 04090003 Severity: Normal -- informational in nature. The Storage System Termination Event Log validation completed successfully. Event Code: 040a0003 Severity: Normal -- informational in nature. The Storage System Termination Event Log validation failed. Event Code: 040b0003 Severity: Normal -- informational in nature. The Storage System Termination Event Log has been updated with the termination event information obtained from the HSV200 controller that is not the Storage System Master. Event Code: 040c0803 Severity: Normal -- informational in nature. The Fault Manager on the Storage System Master received an invalid Event Information Packet from the remote Fault Manager. Event Code: 040d0003 Severity: Normal -- informational in nature. The Fault Manager operation was made quiescent. Event Code: 040e031c Severity: Undetermined -- more information needed to determine severity. An HSV200 controller sent a last gasp message prior to terminating operation with an indication that both HSV200 controllers should terminate operation. Event Code: 040f0003 Severity: Normal -- informational in nature. This HSV200 controller sent its termination event information to the HSV200 controller that is the Storage System Master. Event Code: 04100803 Severity: Normal -- informational in nature. Event reports were lost due to an insufficient supply of ISR Event Log Packets on the HSV200 controller that is the Storage System Master. Event Code: 04110803 Severity: Normal -- informational in nature. Event reports were lost due to an insufficient supply of ISR Event Log Packets on the HSV200 controller that is not the Storage System Master. Event Code: 04120003 Severity: Normal -- informational in nature. The last event reporting interval has changed or last event reporting has been enabled or disabled. Event Code: 04130003 Severity: Normal -- informational in nature. Storage System event reporting is still active. Event Code: 0414031d Severity: Undetermined -- more information needed to determine severity. HSV200 controller operation was terminated due to an unrecoverable event detected by either software or hardware or due to an action initiated via the Storage System Management Interface. Event Code: 0415031d Severity: Undetermined -- more information needed to determine severity. This HSV200 controller has received a last gasp message from another HSV200 controller prior to it terminating operation. Event Code: 0416031d Severity: Undetermined -- more information needed to determine severity. An HSV200 controller sent a last gasp message prior to terminating operation with an indication that both HSV200 controllers should terminate operation. Event Code: 04180003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Log validation completed successfully. Event Code: 04190003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Log validation failed. Event Code: 041a031c Severity: Undetermined -- more information needed to determine severity. An error condition was encountered while this HSV200 controller's Last Termination Event information was being processed. Event Code: 041b031d Severity: Undetermined -- more information needed to determine severity. An error condition was encountered while this HSV200 controller's Last Termination Event information was being processed. Event Code: 06000009 Severity: Normal -- informational in nature. A physical disk drive has reported that it has exceeded its failure prediction threshold. Event Code: 06014a08 Severity: Warning -- not failed but attention recommended or required. A Fibre Channel port on the HSV200 controller has failed to respond. Event Code: 06020009 Severity: Normal -- informational in nature. A physical disk drive has reported a check condition error. Event Code: 06034713 Severity: Warning -- not failed but attention recommended or required. An exchange sent to a physical disk drive or another HSV200 controller via the mirror port or a Fibre Channel port has timed out. Event Code: 06044812 Severity: Warning -- not failed but attention recommended or required. Work was unexpectedly sent to this HSV200 controller by a physical disk drive or another HSV200 controller. Event Code: 06054909 Severity: Warning -- not failed but attention recommended or required. Work has been sent to a physical disk drive or another HSV200 controller via the mirror port but it did not respond. Event Code: 06074709 Severity: Warning -- not failed but attention recommended or required. A Target Discovery Service Descriptor exchange sent to a physical disk drive has timed out. Event Code: 06080007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV200 controller's Fibre Channel port. This informational event is triggered by the occurrence of an excessive number of Tachyon chip link status errors detected within a particular link status error type. Event Code: 06090013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous failure prediction threshold exceeded errors. Event Code: 060a0013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous check condition errors. Event Code: 060b4709 Severity: Warning -- not failed but attention recommended or required. A non-data exchange sent to a physical disk drive has timed out. Event Code: 060c0013 Severity: Normal -- informational in nature. A loop switch has been detected on a Fibre Channel port. Event Code: 060d0013 Severity: Normal -- informational in nature. The location of a physical disk drive previously reported as unknown is now known. Event Code: 060e9613 Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit requested a code update but the code update could not be found, so the update was not performed. Event Code: 060f4013 Severity: Critical -- failure or failure imminent. The Drive Enclosure Environmental Monitoring Unit is able to communicate with a physical disk drive but this HSV200 controller is unable to communicate with that physical disk drive on the Fibre Channel bus. Event Code: 06109b13 Severity: Undetermined -- more information needed to determine severity. An HSV200 controller is unable to communicate with this Drive Enclosure Environmental Monitoring Unit. Event Code: 06120008 Severity: Normal -- informational in nature. The retry count for a task assigned to a Drive Enclosure Environmental Monitoring Unit has been exhausted. Event Code: 06130013 Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit is able to communicate with this HSV200 controller. Event Code: 06149813 Severity: Critical -- failure or failure imminent. There are too many drive enclosures attached to a Fibre Channel port. Event Code: 06159913 Severity: Critical -- failure or failure imminent. The cable connected to the I/O module is attached to the wrong Fibre Channel port. Event Code: 06169713 Severity: Critical -- failure or failure imminent. An HSV200 controller does not have an address on the enclosure address bus. Event Code: 06180013 Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit has begun updating its code. Do not power down this drive enclosure until the code update has completed. Event Code: 06190013 Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit has completed updating its code. It is now safe to power down this drive enclosure. Event Code: 061a0009 Severity: Normal -- informational in nature. A physical disk drive has exceeded its soft error threshold. Event Code: 061b0013 Severity: Normal -- informational in nature. An HSV200 controller now has an address on the enclosure address bus. Event Code: 061c4709 Severity: Warning -- not failed but attention recommended or required. An outbound frame targeted to a physical disk drive has timed out. Event Code: 061d4709 Severity: Warning -- not failed but attention recommended or required. A Fibre Channel exchange to a physical disk drive has completed but is missing data. Event Code: 061e4c13 Severity: Critical -- failure or failure imminent. An HSV200 controller has detected only one port of a Fibre Channel device. Event Code: 061f0013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device with only one port has been corrected and redundancy has been restored. Event Code: 06204013 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel device has been detected. The device has been failed to prevent possible data corruption or system instability. Event Code: 06210013 Severity: Normal -- informational in nature. A Fibre Channel device with incorrect block size has been detected. Event Code: 06230013 Severity: Normal -- informational in nature. An HSV200 controller is about to retry a failed port. Event Code: 06240013 Severity: Normal -- informational in nature. An HSV200 controller has successfully retried a failed port. Event Code: 06254313 Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign a hard address to a physical disk drive on the loop. Event Code: 06268913 Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign an address to a physical disk drive on the loop. This has occurred because another physical disk drive has already obtained this AL_PA. Event Code: 06270113 Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign address(s) to a physical disk drive on the loop. Soft addressing was detected for this enclosure. Event Code: 06280008 Severity: Normal -- informational in nature. The retry count for an OB task assigned to a Drive Enclosure Environmental Monitoring Unit has been exhausted. Event Code: 06290009 Severity: Normal -- informational in nature. The HSV200 controller has sent a Basic Link Service command Abort Sequence Frame. Event Code: 062a0009 Severity: Normal -- informational in nature. The HSV200 controller has sent an Extended Link Service command Reinstate Recovery Qualifier. Event Code: 062b4004 Severity: Critical -- failure or failure imminent. A physical disk drive was bypassed rendering it unusable. Event Code: 062c0012 Severity: Normal -- informational in nature. One or more media defects were detected on a physical disk drive. Event Code: 062d0012 Severity: Normal -- informational in nature. An HSV200 controller issued a directed LIP to an arbitrated loop physical address. Event Code: 062e0012 Severity: Normal -- informational in nature. An HSV200 controller has detected loop receiver failures. Event Code: 06304e13 Severity: Critical -- failure or failure imminent. An HSV200 controller has detected only one port of all Fibre Channel devices in an enclosure. Event Code: 06310013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device enclosure with only one port has been corrected and redundancy has been restored. Event Code: 06324e13 Severity: Critical -- failure or failure imminent. An HSV200 controller has detected only one port of all Fibre Channel devices on a loop. Event Code: 06330013 Severity: Normal -- informational in nature. A previously reported Fibre Channel loop with only one port has been corrected and redundancy has been restored. Event Code: 06340013 Severity: Normal -- informational in nature. An HSV200 controller has been told to enable a device port, and that device port was not disabled during boot diagnostics. Event Code: 06354d04 Severity: Critical -- failure or failure imminent. An unrecognized Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process. Event Code: 06364d04 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process. Event Code: 0637c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process that is later than the latest known supported revision. Event Code: 0638c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process that has a newer supported revision available. Event Code: 06394008 Severity: Critical -- failure or failure imminent. The HSV200 controller bypassed a device bay in an attempt to restore loop operability. Replace this drive only if the Loop Recovery algorithm did not abort. Event Code: 063a0008 Severity: Normal -- informational in nature. The HSV200 controller is attempting to recover devices on the indicated ports. Event Code: 063b0008 Severity: Normal -- informational in nature. The HSV200 controller has finished error recovery attempts on the indicated ports. Event Code: 063c0008 Severity: Normal -- informational in nature. The HSV200 controller been requested to unbypass device bays on the indicated port. Loop recovery incomplete. Event Code: 063d9b09 Severity: Undetermined -- more information needed to determine severity. The HSV200 controller has detected a enclosure on the enclosure address bus that does not have a Fibre Channel connection. Event Code: 063ec513 Severity: Critical -- failure or failure imminent. The HSV200 controller has detected an enclosure on the Fibre Channel but is unable to communicate with the Drive Enclosure Environmental Monitoring Unit on the enclosure address bus or the Drive Enclosure Environmental Monitoring Unit is reporting an invalid enclosure number. Event Code: 063f9c13 Severity: Warning -- not failed but attention recommended or required. A physical disk drive is using an improper protocol to attempt communication with an Drive Enclosure Environmental Monitoring Unit. The physical disk drive identified in the device field has stopped communicating with the HSV200 controller. Event Code: 06404d04 Severity: Critical -- failure or failure imminent. A Fibre Channel physical disk drive that has new capabilities has been detected. The physical disk drive has properties that may or may not be compatible with this release of Enterprise Virtual Array firmware -- the drive will be prevented from being used until the Approved Drive Firmware table has been updated to allow it. Event Code: 06410017 Severity: Normal -- informational in nature. The device loop configuration has changed on a HSV200 controller's Fibre Channel port. This informational event contains a page of the newly genereated fibre channel loop map. Devices are listed in loop order using their ALPAs. Event Code: 06420009 Severity: Normal -- informational in nature. A user command has been sent to a physical disk drive. Event Code: 06440008 Severity: Normal -- informational in nature. An HSV200 controller is evaluating the next drive enclosure in the Loop Recovery Process. Event Code: 06450008 Severity: Normal -- informational in nature. An HSV200 controller has identified a starting point for the Loop Recovery Process. It does not mean this drive is defective. Event Code: 06460008 Severity: Normal -- informational in nature. An HSV200 controller has determined the CAB bus is not usable at this time. A loop recovery operation will not be intitated. Event Code: 06480008 Severity: Normal -- informational in nature. An HSV200 controller experienced the failure of an EMU unbypass operation during loop recovery. User should evaluate any bypassed drives that were not identified as loop disrupters during the recovery for possible re-introduction into the system. Event Code: 06490008 Severity: Normal -- informational in nature. The HSV200 controller is attempting to recover devices in the indicated enclosure. Event Code: 064a0008 Severity: Normal -- informational in nature. The HSV200 controller has finished error recovery attempts in the indicated enclosure. Event Code: 064b0008 Severity: Normal -- informational in nature. The HSV200 controller has been instructed to Enable or Disable Loop Recovery Operations. Event Code: 064c0004 Severity: Normal -- informational in nature. Device Fibre Channel physical disk drive was placed on the Drive Suspect List (DSL) Look at events around this one to help determine what has happened. Fibre Channel port number used to communicate with the physical disk drive is contained in the port field. The arbitrated loop physical address of the physical disk drive is contained in the al_pa field. Note that the content of the rack_num field will not be valid until Event Code: 064d0008 Severity: Normal -- informational in nature. The HSV200 controller has finished attempts to codeload all Drive Enclosure Environmental Monitoring Unit hardware requiring updates, and has completed staggered codeload if necessary. Event Code: 064e0009 Severity: Normal -- informational in nature. A physical disk drive has reported a non-zero RSP_CODE. in response to an I/O. This is not interesting by itself, as the I/O will be retried if retries remain and are allowed for the particular type of I/O. Event Code: 0700b515 Severity: Warning -- not failed but attention recommended or required. Allocation of a Virtual Disk has stalled due to insufficient space in the Disk Group caused by the failure or pulling of a physical disk drive. Event Code: 0701b515 Severity: Warning -- not failed but attention recommended or required. Expansion of a Virtual Disk has stalled due to insufficient space in the Disk Group caused by the failure or pulling of a physical disk drive. Event Code: 07020015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Group has started. Event Code: 07030015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Group has finished. Event Code: 07040015 Severity: Normal -- informational in nature. A member management operation has started due to the appearance or disappearance of a physical disk drive. Event Code: 07050015 Severity: Normal -- informational in nature. A member management operation has finished. Event Code: 07060015 Severity: Normal -- informational in nature. A Disk Group has started changing its internal structure due to the appearance or disappearance of a Volume. Event Code: 07070015 Severity: Normal -- informational in nature. A Disk Group has finished changing its internal structure due to the appearance or disappearance of a Volume. Event Code: 07080015 Severity: Normal -- informational in nature. Deallocation of a Virtual Disk has failed after three attempts due to unknown circumstances. This will more than likely be caused by failing physical drives. The deletion will be restarted when a resync/reboot occurs. Event Code: 0709b515 Severity: Warning -- not failed but attention recommended or required. A member management operation has stalled due to insufficient space in the Disk Group. Event Code: 070a0015 Severity: Normal -- informational in nature. A stalled member management operation is being restarted. Event Code: 070b0015 Severity: Normal -- informational in nature. Unexpected metadata utility event. If available, the tag1 field contains the identity of the Volume, and tag2 field contains the identity of the Logical Disk. Event Code: 070d0015 Severity: Normal -- informational in nature. A member management operation encounter an error while processing a Logical Disk. Processing on this logical disk will be retried again. Event Code: 09010005 Severity: Normal -- informational in nature. A physical disk drive has transitioned to the NORMAL state. Event Code: 09020005 Severity: Normal -- informational in nature. The state of a Volume has changed. Event Code: 09030005 Severity: Normal -- informational in nature. The state of a Logical Disk has changed. Event Code: 09040005 Severity: Normal -- informational in nature. An HSV200 controller has transitioned to the NORMAL state. Event Code: 09050005 Severity: Normal -- informational in nature. The state of a battery assembly has changed. Event Code: 0906bf05 Severity: Undetermined -- more information needed to determine severity. A Volume has transitioned to the MISSING state. Event Code: 09070005 Severity: Normal -- informational in nature. A Fibre Channel port has transitioned to the NORMAL state. Event Code: 0908b405 Severity: Warning -- not failed but attention recommended or required. A Disk Group's occupancy alarm level threshold has been reached. Event Code: 09090005 Severity: Normal -- informational in nature. The resource availability state of a Volume has transitioned to the SUFFICIENT state. Event Code: 090a0005 Severity: Normal -- informational in nature. The data availability state of an internal Logical Disk has transitioned to the NORMAL state. Event Code: 090c0005 Severity: Normal -- informational in nature. A snapclone Logical Disk has completed the unsharing operation. Event Code: 090d0005 Severity: Normal -- informational in nature. The state of the quorum disk flag of a Volume has changed. Event Code: 090e3605 Severity: Critical -- failure or failure imminent. The temperature trip point for a temperature sensor located within an HSV200 controller has been reached. Event Code: 090f2e05 Severity: Warning -- not failed but attention recommended or required. The temperature within an HSV200 controller is approaching its trip point. Event Code: 09110005 Severity: Normal -- informational in nature. An HSV200 controller's blower "1" is now present. Event Code: 09122405 Severity: Critical -- failure or failure imminent. An HSV200 controller's blower "1" is running slower than the lowest acceptable speed. Event Code: 09132005 Severity: Critical -- failure or failure imminent. A voltage sensor has reported a voltage that is out of range. Event Code: 0914bf05 Severity: Undetermined -- more information needed to determine severity. A Volume has transitioned to the FAILED state. Event Code: 0915b905 Severity: Undetermined -- more information needed to determine severity. An HSV200 controller has failed. Event Code: 09160005 Severity: Normal -- informational in nature. The temperature within an HSV200 controller has returned to its normal operating range. Event Code: 09172805 Severity: Critical -- failure or failure imminent. An HSV200 controller's battery assembly "1" has been removed. Event Code: 09180005 Severity: Normal -- informational in nature. An HSV200 controller's battery assembly "1" is now in use. Event Code: 09190005 Severity: Normal -- informational in nature. A voltage sensor has returned to a normal range. Event Code: 091a2005 Severity: Critical -- failure or failure imminent. The battery assembly voltage regulator located within an HSV200 controller is offline. Event Code: 091b0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to the NORMAL state. Event Code: 091c0005 Severity: Normal -- informational in nature. The occupancy alarm level for a Disk Group has returned to the normal range. Event Code: 091d2205 Severity: Critical -- failure or failure imminent. An HSV200 controller's battery assembly "1" has malfunctioned. Event Code: 091e0005 Severity: Normal -- informational in nature. An HSV200 controller's battery assembly "1" is now present. Event Code: 091f2905 Severity: Critical -- failure or failure imminent. An HSV200 controller's battery assembly "2" has been removed. Event Code: 09200005 Severity: Normal -- informational in nature. An HSV200 controller's battery assembly "2" is now present. Event Code: 09210005 Severity: Normal -- informational in nature. An HSV200 controller's battery assembly "2" is now functioning properly. Event Code: 09222305 Severity: Critical -- failure or failure imminent. An HSV200 controller's battery assembly has malfunctioned. Event Code: 09232b05 Severity: Critical -- failure or failure imminent. An HSV200 controller's blower "2" has been removed. Event Code: 09240005 Severity: Normal -- informational in nature. An HSV200 controller's blower assembly "2" is now present. Event Code: 09252505 Severity: Critical -- failure or failure imminent. An HSV200 controller's blower assembly "2" is running slower than the lowest acceptable speed. Event Code: 09262c05 Severity: Critical -- failure or failure imminent. An HSV200 controller's "1" blower/power supply assembly has been removed or AC power has been removed from the power supply. Event Code: 09270005 Severity: Normal -- informational in nature. An HSV200 controller's "1" blower/power supply assembly has been reinstalled or AC power has been restored to the power supply. Event Code: 09282d05 Severity: Critical -- failure or failure imminent. An HSV200 controller's "2" blower/power supply assembly has been removed or AC power has been removed from the power supply. Event Code: 09290005 Severity: Normal -- informational in nature. An HSV200 controller's "2" blower/power supply assembly has been reinstalled or AC power has been restored to the power supply. Event Code: 092a2605 Severity: Critical -- failure or failure imminent. An HSV200 controller's "1" blower/power supply is running slower than the lowest acceptable speed. Event Code: 092b2705 Severity: Critical -- failure or failure imminent. An HSV200 controller's "2" blower/power supply is running slower than the lowest acceptable speed. Event Code: 092c2f05 Severity: Warning -- not failed but attention recommended or required. An HSV200 controller's battery assembly has transitioned to the "Battery System Hold-up Time is zero hours" state. Event Code: 092dbf05 Severity: Undetermined -- more information needed to determine severity. The resource availability state of a Volume has transitioned to the INSUFFICIENT state. Event Code: 092e0005 Severity: Normal -- informational in nature. An HSV200 controller has rejected a login attempt. Event Code: 092f0005 Severity: Normal -- informational in nature. An HSV200 controller has processed a Storage System Management Interface command with the result of non-success return code. Event Code: 09300005 Severity: Normal -- informational in nature. An HSV200 controller has updated the physical disk drive map for a loop pair. Event Code: 09314205 Severity: Critical -- failure or failure imminent. A physical disk drive has transitioned to the DEGRADED state. Event Code: 09324005 Severity: Critical -- failure or failure imminent. A physical disk drive has transitioned to the FAILED state. Event Code: 0933000e Severity: Normal -- informational in nature. A Derived Unit was created. Event Code: 0934000e Severity: Normal -- informational in nature. A Logical Disk was created. Event Code: 0935000e Severity: Normal -- informational in nature. A Disk Group was created. Event Code: 0936000e Severity: Normal -- informational in nature. A physical disk drive was discovered. Event Code: 0937000e Severity: Normal -- informational in nature. A Presented Unit was created. Event Code: 0938000e Severity: Normal -- informational in nature. A Storage System Host Path was created. Event Code: 0939000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was created. Event Code: 093a000e Severity: Normal -- informational in nature. A Volume was created. Event Code: 093b000e Severity: Normal -- informational in nature. A Derived Unit was deleted. Event Code: 093c000e Severity: Normal -- informational in nature. A Logical Disk was deleted. Event Code: 093d000e Severity: Normal -- informational in nature. A Disk Group was deleted. Event Code: 093e420e Severity: Critical -- failure or failure imminent. A physical disk drive has disappeared. Event Code: 093f000e Severity: Normal -- informational in nature. A Presented Unit was deleted. Event Code: 0940000e Severity: Normal -- informational in nature. A Storage System Host Path was deleted. Event Code: 0941000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was deleted. Event Code: 0943000e Severity: Normal -- informational in nature. An HSV200 controller has joined the Storage System. Event Code: 0944ba0e Severity: Undetermined -- more information needed to determine severity. An HSV200 controller has left the Storage System. Event Code: 0945000e Severity: Normal -- informational in nature. The Storage System has been deleted by an HSV200 controller. Event Code: 0946000e Severity: Normal -- informational in nature. A Data Replication Group was created. Event Code: 0947000e Severity: Normal -- informational in nature. A Data Replication Group was deleted. Event Code: 0948000e Severity: Normal -- informational in nature. An internal Logical Disk associated with a snapshot Virtual Disk was created. Event Code: 0949000e Severity: Normal -- informational in nature. An internal Logical Disk associated with a copy of a Virtual Disk was created. Event Code: 094a000e Severity: Normal -- informational in nature. Destination Data Replication Group not deleted due to inoperative members. Event Code: 094b000e Severity: Normal -- informational in nature. A Volume was removed from a LDAD. Event Code: 094c000e Severity: Normal -- informational in nature. A new Remote Node has been discovered. Event Code: 094d000e Severity: Normal -- informational in nature. The Remote Node object has been discarded. Event Code: 094e000e Severity: Normal -- informational in nature. The Remote Node Storage System UUID has changed. Event Code: 0965000f Severity: Normal -- informational in nature. A host operating system mode has changed. Event Code: 0966000f Severity: Normal -- informational in nature. Time was set on a Storage System. Event Code: 0967000f Severity: Normal -- informational in nature. The LUN of a Presented Unit has changed. Event Code: 0968000f Severity: Normal -- informational in nature. The device addition policy of a Storage System has changed. Event Code: 0969000f Severity: Normal -- informational in nature. The quiescent state of a Storage System Virtual Disk has changed. Event Code: 096a000f Severity: Normal -- informational in nature. The enabled/disabled state of a Storage System Virtual Disk has changed. Event Code: 096b000f Severity: Normal -- informational in nature. The cache policy of a Storage System Virtual Disk has changed. Event Code: 096c000f Severity: Normal -- informational in nature. The usage state of a Volume changed. Event Code: 096d000f Severity: Normal -- informational in nature. The disk failure protection level of a Disk Group has changed. Event Code: 096e000f Severity: Normal -- informational in nature. The write protected state of a Derived Unit has changed. Event Code: 0970460f Severity: Warning -- not failed but attention recommended or required. A physical disk drive has experienced numerous communication failures on a particular Fibre Channel port. Event Code: 0971000f Severity: Normal -- informational in nature. An HSV200 controller has received a request to shutdown. Event Code: 0972000f Severity: Normal -- informational in nature. An HSV200 controller has completed its shutdown preparations. Event Code: 0973000f Severity: Normal -- informational in nature. The failsafe state of a Data Replication Group has changed. Event Code: 0974000f Severity: Normal -- informational in nature. The mode of a Data Replication Group has changed. Event Code: 0975000f Severity: Normal -- informational in nature. The synchronous/asynchronous operational state of a Data Replication Group has changed. Event Code: 0976000f Severity: Normal -- informational in nature. The read only attribute of a Data Replication Group has changed. Event Code: 0977000f Severity: Normal -- informational in nature. A Data Replication Group failover has occurred. Event Code: 0978000f Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed. Event Code: 0979000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was added to a Data Replication Group. Event Code: 097a000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was removed from a Data Replication Group. Event Code: 097b000f Severity: Normal -- informational in nature. The auto suspend attribute of a Data Replication Group has changed. Event Code: 097c000f Severity: Normal -- informational in nature. The destination presentation attribute of a Data Replication Group has changed. Event Code: 097d000f Severity: Normal -- informational in nature. The flags of a physical disk drive have changed because of a maintenance mode change. Event Code: 097e000f Severity: Normal -- informational in nature. The defer_copy attribute of a Data Replication Group has changed. Event Code: 097f000f Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed. Event Code: 0980000f Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed. Event Code: 0981000f Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed. Event Code: 09c85105 Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the DATA LOST state. Event Code: 09c95105 Severity: Undetermined -- more information needed to determine severity. A Disk Group has transitioned to an INOPERATIVE state. Event Code: 09ca5105 Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the FAILED state. Event Code: 09cb5005 Severity: Critical -- failure or failure imminent. An internal Logical Disk has transitioned to the SNAPSHOT OVERCOMMIT state. Event Code: 09cc5105 Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the DEVICE DATA LOST state. Event Code: 09cdc305 Severity: Undetermined -- more information needed to determine severity. A Fibre Channel port has transitioned to the FAILED state. Event Code: 09ce0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to an INOPERATIVE MARKED state. Event Code: 09cf4105 Severity: Warning -- not failed but attention recommended or required. A physical disk drive has transitioned to the NOT PRESENT state. Event Code: 09d00005 Severity: Normal -- informational in nature. An HSV200 controller no longer needs attention. Event Code: 09d1b905 Severity: Undetermined -- more information needed to determine severity. An HSV200 controller needs attention. Event Code: 09d22a05 Severity: Critical -- failure or failure imminent. An HSV200 controller's blower "1" has been removed. Event Code: 09d35105 Severity: Undetermined -- more information needed to determine severity. At least one Virtual Disk associated with a Data Replication Group has transitioned to the INOPERATIVE state. The remaining Virtual Disks associated with this Data Replication Group have been forced INOPERATIVE. Event Code: 09d40005 Severity: Normal -- informational in nature. All the Virtual Disks associated with a Data Replication Group have transitioned to the OPERATIVE state. Event Code: 09d50005 Severity: Normal -- informational in nature. The state of a physical disk drive has transitioned to the Single Port on Fibre state. Event Code: 09d63705 Severity: Warning -- not failed but attention recommended or required. An HSV200 controller has been powered off because the temperature sensors do not agree and the system temperature can not be accurately determined. Event Code: 09d73705 Severity: Warning -- not failed but attention recommended or required. An HSV200 controller has been powered off because the temperature sensors can not be accessed and the system temperature can not be accurately determined. Event Code: 09d8b605 Severity: Undetermined -- more information needed to determine severity. A Redundant Storage Set has two members on the same Fibre Channel device enclosure causing a Disk Group to lose its Single Point of Failure Robust Configuration. Event Code: 09d90005 Severity: Normal -- informational in nature. A Disk Group has attained a Single Point of Failure Robust Configuration. Event Code: 09da0005 Severity: Normal -- informational in nature. An HSV200 controller's blower "1" is running at normal speed. Event Code: 09db0005 Severity: Normal -- informational in nature. An HSV200 controller's blower "2" is running at normal speed. Event Code: 09dc0b05 Severity: Warning -- not failed but attention recommended or required. An HSV200 controller's glue eeprom has been programmed. A controller reset is going to be initiated to finish the glue part programming. This will take longer than the resync that normally occurs after a codeload. Event Code: 09dd0005 Severity: Normal -- informational in nature. An HSV200 controller receives a maintenance invoke call from the user Event Code: 09de5205 Severity: Critical -- failure or failure imminent. An internal Logical Disk has transitioned to the INVALIDATED state. Event Code: 0b000010 Severity: Normal -- informational in nature. An HSV200 controller has begun a resynchronization operation. This is a restart of the HSV200 controller in a manner that has little or no impact on host system connectivity. Event Code: 0b01b515 Severity: Warning -- not failed but attention recommended or required. A migrate method drive codeload has stalled due to insufficient space in the Disk Group. Event Code: 0b020004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware version has been loaded into memory in preparation for codeload. Event Code: 0b040004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload begun. Event Code: 0b050004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload has finished. Event Code: 0b06001a Severity: Normal -- informational in nature. An HSV200 controller has begun/finished a code load, code use, or code burn operation as indicated, in a manner that has little or no impact on host system connectivity. Event Code: 0b070b1a Severity: Warning -- not failed but attention recommended or required. An HSV200 controller has finished a code load to the GLUE eeprom. Event Code: 0b09001e Severity: Normal -- informational in nature. Process with work, eg. during CSM Hang and Unit Stalled Too Long. Event Code: 0c03000c Severity: Normal -- informational in nature. The specified Data Replication Group has transitioned to the Merging state, because the Data Replication Destination Storage System is now accessible or resumed. Event Code: 0c045f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state because the Data Replication Destination Storage System is inaccessible. Event Code: 0c05610c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state due to an inaccessible Destination Virtual Disk. Event Code: 0c06600c Severity: Critical -- failure or failure imminent. A Full Copy was terminated prior to completion: An unrecoverable read error occurred on the specified Source Virtual Disk during the Full Copy. Event Code: 0c075f0c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible alternate Storage System; The Full Copy will continue when the Data Replication Destination is restored. Event Code: 0c08610c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible Destination Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored. Event Code: 0c09620c Severity: Warning -- not failed but attention recommended or required. A Data Replication Log has been reset due to insufficient Disk Group capacity; The Data Replication Destination has been marked for a Full Copy. Event Code: 0c0a000c Severity: Normal -- informational in nature. A Data Replication Log has been reset due to a Data Replication Group failover. Event Code: 0c0c000c Severity: Normal -- informational in nature. A Destination Data Replication Group has successfully completed a Merge. Event Code: 0c0f000c Severity: Normal -- informational in nature. A Data Replication Group is no longer in a Failsafe Locked state. Event Code: 0c10000c Severity: Normal -- informational in nature. A Destination Data Replication Group has been marked for a Full Copy. Event Code: 0c11000c Severity: Normal -- informational in nature. This Data Replication Group is transitioning from a Data Replication Source role to a Data Replication Destination role. Event Code: 0c12000c Severity: Normal -- informational in nature. This Data Replication Group is transitioning from a Data Replication Destination role to a Data Replication Source role. Event Code: 0c160016 Severity: Normal -- informational in nature. An HSV200 controller has sent a time report message to this HSV200 controller. Event Code: 0c17630c Severity: Critical -- failure or failure imminent. The Data Replication Manager communications protocol version between the Data Replication Source Storage System and a Data Replication Destination Storage System is mismatched. Event Code: 0c18640c Severity: Critical -- failure or failure imminent. Conditions on the Data Replication Destination Storage System are preventing acceptable replication throughput: Initiating temporary logging on the affected Data Replication Group that is failsafe mode disabled. Event Code: 0c19020c Severity: Critical -- failure or failure imminent. Overlapping concurrent host writes to an Active/Active Peer Storage System violate a Data Replication Manager architectural requirement, resulting in a reparative resynchronization operation for the master Storage System and a Full Copy operation. Event Code: 0c1a000c Severity: Normal -- informational in nature. The specified Destination Virtual Disk has successfully completed a Full Copy. Event Code: 0c1b5f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has transitioned to the Logging state because the alternate Storage System is not accessible. Event Code: 0c1c610c Severity: Critical -- failure or failure imminent. The specified Source Data Replication Group has transitioned to the (not merging) Logging state because a Destination Virtual Disk is not accessible. Event Code: 0c1d000c Severity: Normal -- informational in nature. Inconsistency was found in the group log: A Full Copy of the affected Data Replication Group will be initiated. Event Code: 0c1e5f0c Severity: Critical -- failure or failure imminent. The members of the specified Source Data Replication Group have not been presented to the host because the remote Storage System is not accessible: Suspend Source Data Replication Group to override this behavior, which will present the members. Event Code: 0c1f000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been presented to the host because the remote Storage System is now accessible or source group is now suspended. Event Code: 0c20650c Severity: Critical -- failure or failure imminent. Conditions on the Data Replication Destination Storage System are preventing replication processing: The specified Source Data Replication Group will remain in the Logging or the Failsafe Locked state until corrective action is performed. Event Code: 0c21660c Severity: Critical -- failure or failure imminent. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c22000c Severity: Normal -- informational in nature. A Data Replication Path between this Storage System and the Peer Storage System has been opened. Event Code: 0c23670c Severity: Warning -- not failed but attention recommended or required. Conditions on the inter site link are preventing acceptable replication throughput: Initiating temporary logging on the affected Data Replication Group that is failsafe mode disabled. Event Code: 0c24000c Severity: Normal -- informational in nature. The specified Source Data Replication Group has transitioned to the (not merging) Logging state because a Destination Virtual Disk is momentarily inaccessible. Event Code: 0c25000c Severity: Normal -- informational in nature. A Full Copy terminated prior to completion: A remote copy error occurred due to a momentarily inaccessible Destination Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored. Event Code: 0c26000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been opened due to simultaneous requests from each Storage System Event Code: 0c27000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been opened by the Peer Storage System. Event Code: 0c285f0c Severity: Critical -- failure or failure imminent. A Data Replication Path to the Peer Storage System is not currently available. Event Code: 0c29000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed in order to force Data Replication Manager traffic to the controller's Preferred Port. Event Code: 0c2a000c Severity: Normal -- informational in nature. A Data Replication Path to a Peer Storage System has been found. Event Code: 0c2b600c Severity: Critical -- failure or failure imminent. A Merge was terminated prior to completion: An unrecoverable read error occurred on the log unit of the specified Data Replication Group during the Merge. Event Code: 0c2c660c Severity: Critical -- failure or failure imminent. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c2d000c Severity: Normal -- informational in nature. The Peer Storage System port name that was incorrectly associated with a host has been deleted from the specified client object. Event Code: 0c2e680c Severity: Warning -- not failed but attention recommended or required. Insufficient resources exist to discover additional remote nodes. Event Code: 0c2f000c Severity: Normal -- informational in nature. Sufficient resources now exist to allow discovery of additional remote nodes. Event Code: 0c30000c Severity: Normal -- informational in nature. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c31000c Severity: Normal -- informational in nature. A stalled Full Copy has been restarted. Event Code: 0c325f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the host port connection has failed. Event Code: 0c335f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the link or the Storage System has become unresponsive. Event Code: 0c345f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, due to slow response on the connection between the specified host port and the Peer Storage System. Event Code: 0c35070c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has closed, because a Data Replication Group configuration change lock was not released in a timely manner. Event Code: 0c365f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, due to thrashing of the connection between the specified host port and the Peer Storage System. Event Code: 0c375f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the maximum ping retry count has been exceeded. Event Code: 0c38630c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Data Replication Path protocol version is not supported by the controller firmware. Event Code: 0c39000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Data Replication Path is not being used. Event Code: 0c3a5f0c Severity: Critical -- failure or failure imminent. A Data Replication Path between this Storage System and the Peer Storage System could not be created, possibly due to a connection failure between the specified host port and the Peer Storage System. Event Code: 0c3b000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Peer Storage System requested the creation of a new Data Replication Path. Event Code: 0c3c000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the Peer Storage System tried to open a Data Replication Path to a different host port. Event Code: 0c3d5f0c Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed because of a frame retransmit limit was reached. Event Code: 0c3e000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System was closed by the Peer Storage System. Event Code: 0c3f000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the NPortID of the remote port changed. Event Code: 0c40690c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has closed because an out of order frame sequence number was detected. Event Code: 0c41000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed to allow creation of a Data Replication Path that requires a lower protocol version. Event Code: 0c42000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because Peer Storage System no longer exists. Event Code: 0c43000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been closed by user request. Event Code: 0c49000c Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the corresponding connection data was deleted. This is typically due to a change in the fabric. Event Code: 0c4a000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the Storage System is re-starting. Event Code: 0c4b000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the Storage System is not active. Event Code: 0c4c000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the firmware has not completed Data Replication Path discovery. Event Code: 0c4d000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the firmware is performing Data Replication Path discovery on the path. Event Code: 0c4e000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the remote port is not associated with a Enterprise Virtual Array. Event Code: 0c4f000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the remote port world wide identifier is associated with a host system. Event Code: 0c50000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the supplied UUID does not match the UUID for this Storage System. Event Code: 0c51000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the requested protocol version is not compatible with the existing Data Replication Path. Event Code: 0c52000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the requested port was disabled by the user. Event Code: 0c53000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the insufficient resources exist to create the Data Replication Path. Event Code: 0c54000c Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected to force the use of a lower protocol version on the Data Replication Path. Event Code: 0c550016 Severity: Normal -- informational in nature. A time synchronization message has been sent to a Alternate Site. Event Code: 0c56000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout value has been changed. Event Code: 0c57000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout value has been reset to the default value. Event Code: 0c58690c Severity: Warning -- not failed but attention recommended or required. Excessive data exchange retry rate on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources. Event Code: 0c59690c Severity: Warning -- not failed but attention recommended or required. Excessive out of order message rate on the inter site link is impacting replication throughput. Event Code: 0c5a670c Severity: Warning -- not failed but attention recommended or required. Excessive PING response time on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources. Event Code: 0c5b670c Severity: Warning -- not failed but attention recommended or required. Replication data exchange write resources on the inter site link have been reduced to the minimum allowed value. Event Code: 0c5c670c Severity: Warning -- not failed but attention recommended or required. Replication data exchange copy resources on the inter site link have been reduced to the minimum allowed value. Event Code: 0c5d000c Severity: Normal -- informational in nature. Quality of service on the inter site link has improved: Increasing data exchange resources to improve replication throughput. Event Code: 0c5e000c Severity: Normal -- informational in nature. A Replication Write History Log Shrink is in progress. Event Code: 0c5f000c Severity: Normal -- informational in nature. A Replication Write History Log Shrink has completed. Event Code: 0c60000c Severity: Normal -- informational in nature. Excessive Vdisk response time at the Data Replication Destination has been detected: Reducing data exchange copy resources on the inter site link to limit replication throughput. Event Code: 0d000111 Severity: Critical -- failure or failure imminent. An unrecognized event was reported by a Drive Enclosure Environmental Monitoring Unit. Event Code: 0d014011 Severity: Critical -- failure or failure imminent. A physical disk drive was detected that is not Fibre Channel compatible or cannot operate at the link rate established by the drive enclosure I/O modules. Event Code: 0d024111 Severity: Warning -- not failed but attention recommended or required. A physical disk drive is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition. Event Code: 0d034111 Severity: Warning -- not failed but attention recommended or required. A physical disk drive was removed while software-activated drive locking was enabled on a drive enclosure that does not support drive locking. Event Code: 0d044211 Severity: Critical -- failure or failure imminent. A physical disk drive that is capable of operating at the loop link rate established by the drive enclosure I/O module was found to be running at a different rate. Event Code: 0d330911 Severity: Warning -- not failed but attention recommended or required. The AC input to a drive enclosure power supply has been lost. Note that the remaining power supply has become a single point of failure. Event Code: 0d348011 Severity: Critical -- failure or failure imminent. A drive enclosure power supply is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition. The operational power supply will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply shuts down, whichever occurs first. Event Code: 0d359a11 Severity: Critical -- failure or failure imminent. A drive enclosure power supply component has failed. Event Code: 0d478311 Severity: Critical -- failure or failure imminent. A drive enclosure blower is not operating properly. This could affect the drive enclosure air flow and cause an over temperature condition. A single blower operating at high speed can provide sufficient air flow to cool an enclosure and the elements for up to 100 hours. However, operating an enclosure at temperatures approaching an overheating threshold can damage elements and may reduce the mean time before failure of a specific element. Event Code: 0d4b8211 Severity: Critical -- failure or failure imminent. A drive enclosure blower is improperly installed or missing. This affects the drive enclosure air flow and can cause an over temperature condition. Event Code: 0d4c8411 Severity: Critical -- failure or failure imminent. Both drive enclosure blowers are missing. This severely affects the drive enclosure air flow and can cause an over temperature condition. The operational power supply(s) will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply(s) shut down, whichever occurs first. Event Code: 0d5b8611 Severity: Warning -- not failed but attention recommended or required. A drive enclosure temperature sensor out of range condition has been reported by one of the drive enclosure elements. Event Code: 0d5f8711 Severity: Critical -- failure or failure imminent. The average temperature of two of the three temperature sensor groups (i.e., Drive Enclosure Environmental Monitoring Unit, Disk Drives, and Power Supplies) exceeds the CRITICAL level. The operational power supply(s) will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply(s) shut down, whichever occurs first. Refer to the HSV element manager GUI for the temperature threshold values. Event Code: 0d6f8811 Severity: Warning -- not failed but attention recommended or required. An internal Drive Enclosure Environmental Monitoring Unit error has occurred. Event Code: 0d710011 Severity: Normal -- informational in nature. An internal Drive Enclosure Environmental Monitoring Unit error has occurred. Event Code: 0d728a11 Severity: Warning -- not failed but attention recommended or required. A Drive Enclosure Environmental Monitoring Unit is unable to collect data for the SCSI-3 Enclosure Services (SES) page. Event Code: 0d7e8c11 Severity: Warning -- not failed but attention recommended or required. Invalid data was read from a Drive Enclosure Environmental Monitoring Unit NVRAM. Event Code: 0d7f8b11 Severity: Warning -- not failed but attention recommended or required. An internal Drive Enclosure Environmental Monitoring Unit error has occurred. Event Code: 0d828e11 Severity: Warning -- not failed but attention recommended or required. A drive enclosure's address is incorrect or the enclosure has no address. Event Code: 0d838911 Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has experienced a hardware failure. Event Code: 0d858f11 Severity: Warning -- not failed but attention recommended or required. A drive enclosure power supply failed to respond to a shut down command. Event Code: 0d8d9011 Severity: Critical -- failure or failure imminent. A drive enclosure transceiver error has been detected. Event Code: 0da18111 Severity: Critical -- failure or failure imminent. A drive enclosure power supply voltage sensor out-of-range condition has been reported. Event Code: 0db58111 Severity: Critical -- failure or failure imminent. A drive enclosure power supply current sensor out of range condition has been reported. Event Code: 0dd89211 Severity: Warning -- not failed but attention recommended or required. A drive enclosure backplane invalid NVRAM read error has occurred. Event Code: 0dd99111 Severity: Critical -- failure or failure imminent. A drive enclosure backplane error has occurred. Event Code: 0ddd9311 Severity: Critical -- failure or failure imminent. A drive enclosure I/O module error has occurred. Event Code: 0dde9511 Severity: Warning -- not failed but attention recommended or required. A drive enclosure I/O module is unable to communicate with the Drive Enclosure Environmental Monitoring Unit. Event Code: 0dec9411 Severity: Warning -- not failed but attention recommended or required. A drive enclosure I/O module invalid NVRAM read error has occurred. Event Code: 0df00011 Severity: Normal -- informational in nature. The status has changed on one or more of the drive enclosures. This informational event is generated for the HSV element manager GUI and contains no user information. Event Code: 0df68811 Severity: Warning -- not failed but attention recommended or required. An Drive Enclosure Environmental Monitoring Unit has detected missing receive interrupts on its Com Port. Event Code: 0df70011 Severity: Normal -- informational in nature. An Drive Enclosure Environmental Monitoring Unit has rebooted following the detection of missing receive interrupts on its Com Port. Event Code: 0df80011 Severity: Normal -- informational in nature. An Drive Enclosure Environmental Monitoring Unit has initialized its Com Port following the detection of an overrun condition. Event Code: 0e000019 Severity: Normal -- informational in nature. Battery subsystem boot time status. Event Code: 0e010019 Severity: Normal -- informational in nature. Battery assembly "0" is now present. Event Code: 0e02cc19 Severity: Critical -- failure or failure imminent. Battery assembly "0" has been removed. Event Code: 0e030019 Severity: Normal -- informational in nature. The status of battery assembly "0" has changed. Event Code: 0e04c819 Severity: Critical -- failure or failure imminent. Battery assembly "0" has malfunctioned. Event Code: 0e050019 Severity: Normal -- informational in nature. Battery assembly "1" is now present. Event Code: 0e06cd19 Severity: Critical -- failure or failure imminent. Battery assembly "1" has been removed. Event Code: 0e070019 Severity: Normal -- informational in nature. The status of battery assembly "1" has changed. Event Code: 0e08c919 Severity: Critical -- failure or failure imminent. Battery assembly "1" has malfunctioned. Event Code: 0e090019 Severity: Normal -- informational in nature. Battery assembly "2" is now present. Event Code: 0e0ace19 Severity: Critical -- failure or failure imminent. Battery assembly "2" has been removed. Event Code: 0e0b0019 Severity: Normal -- informational in nature. The status of battery assembly "2" has changed. Event Code: 0e0cca19 Severity: Critical -- failure or failure imminent. Battery assembly "2" has malfunctioned. Event Code: 0e0d0019 Severity: Normal -- informational in nature. Battery assembly "3" is now present. Event Code: 0e0ecf19 Severity: Critical -- failure or failure imminent. Battery assembly "3" has been removed. Event Code: 0e0f0019 Severity: Normal -- informational in nature. The status of battery assembly "3" has changed. Event Code: 0e10cb19 Severity: Critical -- failure or failure imminent. Battery assembly "3" has malfunctioned. Event Code: 0e110019 Severity: Normal -- informational in nature. The battery subsystem has transitioned to the good state. Event Code: 0e120019 Severity: Normal -- informational in nature. The battery subsystem has transitioned to the low state. Event Code: 0e13d019 Severity: Warning -- not failed but attention recommended or required. The battery subsystem has transitioned to the bad state. Event Code: 0e140019 Severity: Normal -- informational in nature. Blower subsystem boot time status. Event Code: 0e150019 Severity: Normal -- informational in nature. Blower assembly "0" is now present. Event Code: 0e16d419 Severity: Critical -- failure or failure imminent. Blower assembly "0" has been removed. Event Code: 0e170019 Severity: Normal -- informational in nature. The status of blower assembly "0" has changed. Event Code: 0e18d219 Severity: Critical -- failure or failure imminent. Blower assembly "0" has malfunctioned. Event Code: 0e190019 Severity: Normal -- informational in nature. Blower assembly "1" is now present. Event Code: 0e1ad519 Severity: Critical -- failure or failure imminent. Blower assembly "1" has been removed. Event Code: 0e1b0019 Severity: Normal -- informational in nature. The status of blower assembly "1" has changed. Event Code: 0e1cd319 Severity: Critical -- failure or failure imminent. Blower assembly "1" has malfunctioned. Event Code: 0e1dda19 Severity: Warning -- not failed but attention recommended or required. Battery read memory failure has occurred. Event Code: 0e1e0019 Severity: Normal -- informational in nature. Temperature subsystem boot time status. Event Code: 0e1f0019 Severity: Normal -- informational in nature. The temperature within an HSV200 controller has returned to its normal operating range. Event Code: 0e202e19 Severity: Warning -- not failed but attention recommended or required. The temperature within an HSV200 controller is approaching its trip point. Event Code: 0e213619 Severity: Critical -- failure or failure imminent. The temperature trip point for a temperature sensor located within an HSV200 controller has been reached. Event Code: 0e220019 Severity: Normal -- informational in nature. Power Supply subsystem boot time status. Event Code: 0e230019 Severity: Normal -- informational in nature. Power Supply assembly "0" is now present. Event Code: 0e24d819 Severity: Critical -- failure or failure imminent. Power Supply assembly "0" has been removed. Event Code: 0e250019 Severity: Normal -- informational in nature. The status of power supply assembly "0" has changed. Event Code: 0e26d619 Severity: Critical -- failure or failure imminent. Power supply assembly "0" lost AC connection or has malfunctioned. Event Code: 0e270019 Severity: Normal -- informational in nature. Power Supply assembly "1" is now present. Event Code: 0e28d919 Severity: Critical -- failure or failure imminent. Power Supply assembly "1" has been removed. Event Code: 0e290019 Severity: Normal -- informational in nature. The status of power supply assembly "1" has changed. Event Code: 0e2ad719 Severity: Critical -- failure or failure imminent. Power supply assembly "1" lost AC connection or has malfunctioned. Event Code: 42000008 Severity: Normal -- informational in nature. A host Fibre Channel port transitioned to the link down state. Event Code: 42010008 Severity: Normal -- informational in nature. A host Fibre Channel port transitioned to the link failed state. Event Code: 42030007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a host Fibre Channel port. Event Code: 42044a08 Severity: Warning -- not failed but attention recommended or required. A host Fibre Channel port has failed to respond. Event Code: 42050008 Severity: Normal -- informational in nature. A host Fibre Channel port has transitioned to a deadlocked state. Event Code: 4206001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transitioned to Stalled Too Long. Event Code: 4207001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transitioned to ownership by the other HSV200 controller. Event Code: 42080008 Severity: Normal -- informational in nature. A host Fibre Channel port has been reissued a freeze command. Event Code: 42090008 Severity: Normal -- informational in nature. A host Fibre Channel port has been issued a soft reset. Event Code: 420a001b Severity: Normal -- informational in nature. Indicated Virtual Disk that previously entered into Stalled Too Long has now been unstalled and resumed. Event Code: 83002014 Severity: Critical -- failure or failure imminent. A failure was detected during the execution of this HSV200 controller's on-board diagnostics. Event Code: 83013014 Severity: Warning -- not failed but attention recommended or required. A GBIC SFF Serial ID Data check code failure was detected during the execution of this HSV200 controller's on-board diagnostics. Event Code: 83073a14 Severity: Warning -- not failed but attention recommended or required. A GBIC SFF was determined to be not present during the execution of this HSV200 controller's on-board diagnostics. Event Code: 83083b14 Severity: Warning -- not failed but attention recommended or required. A failure was detected during testing of this HSV200 controller's SRAM. Event Code: 83093b14 Severity: Warning -- not failed but attention recommended or required. A parity error was detected during testing of this HSV200 controller's SRAM. Event Code: 830a3b14 Severity: Warning -- not failed but attention recommended or required. Force parity generation failed during test of this HSV200 controller's SRAM. TERMINATION CODES: Termination Code: 0101011f Severity: Critical -- failure or failure imminent. Unknown fault type reported by EXEC. Termination Code: 0102011f Severity: Critical -- failure or failure imminent. DLQ entry not properly linked. Termination Code: 0103011f Severity: Critical -- failure or failure imminent. Timer not expired as expected. Termination Code: 0104011f Severity: Critical -- failure or failure imminent. Structure not a timer as expected. Termination Code: 0105011f Severity: Critical -- failure or failure imminent. DLQ entry doubly linked. Termination Code: 0106011f Severity: Critical -- failure or failure imminent. DLQ head not properly linked. Termination Code: 0107011f Severity: Critical -- failure or failure imminent. SQ entry doubly linked. Termination Code: 0108011f Severity: Critical -- failure or failure imminent. Structure not a BQUE as expected. Termination Code: 0109011f Severity: Critical -- failure or failure imminent. Structure not a SEM as expected. Termination Code: 010a011f Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 010b011f Severity: Critical -- failure or failure imminent. ILF invocation not from SC. Termination Code: 010c011f Severity: Critical -- failure or failure imminent. Too many performance log instances. Termination Code: 010d011f Severity: Critical -- failure or failure imminent. Undefined performance log call. Termination Code: 010e011f Severity: Critical -- failure or failure imminent. Structure not AQUE as expected. Termination Code: 010f011f Severity: Critical -- failure or failure imminent. Waiter queue not empty as expected. Termination Code: 0110011f Severity: Critical -- failure or failure imminent. Structure not GATE as expected. Termination Code: 0111011f Severity: Critical -- failure or failure imminent. Receiver queue not empty as expected. Termination Code: 0112011f Severity: Critical -- failure or failure imminent. BQUE has unexpected items. Termination Code: 0113011f Severity: Critical -- failure or failure imminent. Structure not ASEM as expected. Termination Code: 0114011f Severity: Critical -- failure or failure imminent. Unknown system trap routine. Termination Code: 0115011f Severity: Critical -- failure or failure imminent. Active DMA list is empty. Termination Code: 0116011f Severity: Critical -- failure or failure imminent. CDB address not as expected. Termination Code: 0117011f Severity: Critical -- failure or failure imminent. Attempt to allocate a buffer that is already in use. Termination Code: 0118011f Severity: Critical -- failure or failure imminent. Attempt to free a buffer that is already free. Termination Code: 0119011f Severity: Critical -- failure or failure imminent. Interrupts unexpectedly disabled. Termination Code: 011a011f Severity: Critical -- failure or failure imminent. Page zero corrupted. Termination Code: 011b011f Severity: Critical -- failure or failure imminent. DCBZ not cache line aligned. Termination Code: 011c0140 Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled). Termination Code: 011d01c0 Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled). Termination Code: 011e0120 Severity: Critical -- failure or failure imminent. Console requested restart without dump (not coupled). Termination Code: 011f01a0 Severity: Critical -- failure or failure imminent. Console requested restart without dump (coupled). Termination Code: 01220105 Severity: Critical -- failure or failure imminent. Unknown SMI interrupt occurred. Termination Code: 01400100 Severity: Critical -- failure or failure imminent. Expiration queue not BQUE. Termination Code: 015a0100 Severity: Critical -- failure or failure imminent. exc_do_preempt_high called with empty subprocess queue Termination Code: 02000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 02010100 Severity: Critical -- failure or failure imminent. CACHE$GET_DATA called with bad get data. Termination Code: 02020100 Severity: Critical -- failure or failure imminent. Cannot allocate BQ. Termination Code: 02030100 Severity: Critical -- failure or failure imminent. Duplicate dirty data found in Buffer Metadata Array. Termination Code: 02040100 Severity: Critical -- failure or failure imminent. Invalid Primary Mirror Operation state. Termination Code: 02050100 Severity: Critical -- failure or failure imminent. Invalid Unit Cache state. Termination Code: 02070100 Severity: Critical -- failure or failure imminent. Mirror data structure inconsistency. Termination Code: 02080100 Severity: Critical -- failure or failure imminent. Mirror UUID Changed. Termination Code: 02090100 Severity: Critical -- failure or failure imminent. Invalid call to CACHE$LOCK_META. Termination Code: 020a0100 Severity: Critical -- failure or failure imminent. Cannot align parity and user data. Termination Code: 020b0100 Severity: Critical -- failure or failure imminent. Invalid Pullover Memory Operation state. Termination Code: 020c0100 Severity: Critical -- failure or failure imminent. Invalid Group Cache Operation state. Termination Code: 020d0100 Severity: Critical -- failure or failure imminent. Process NV Data NCA corrupted. Termination Code: 020e0100 Severity: Critical -- failure or failure imminent. Process NV Data Freeing Diag Buffer. Termination Code: 020f0100 Severity: Critical -- failure or failure imminent. Improper MWB Recovery data sent. Termination Code: 02100100 Severity: Critical -- failure or failure imminent. Mnode & MFC NCAE Difference. Termination Code: 02110100 Severity: Critical -- failure or failure imminent. Improper MWBF Recovery data sent. Termination Code: 02120100 Severity: Critical -- failure or failure imminent. WRITE HOLE COLLISION IN RS_CRITICAL.c Termination Code: 02150100 Severity: Critical -- failure or failure imminent. Unable to obtain free cache nodes. Termination Code: 02160100 Severity: Critical -- failure or failure imminent. Unable to obtain free volatile cache buffers. Termination Code: 02180102 Severity: Critical -- failure or failure imminent. Invalid Proxy Write Mirror Operation state. Termination Code: 02190102 Severity: Critical -- failure or failure imminent. Invalid Proxy Read Mirror Operation state. Termination Code: 021a0102 Severity: Critical -- failure or failure imminent. Invalid Proxy Verify Mirror Operation state. Termination Code: 021b0100 Severity: Critical -- failure or failure imminent. Not enough XDs for RSTORE flush Termination Code: 021c0102 Severity: Critical -- failure or failure imminent. Invalid Flush Node Detected Termination Code: 03010104 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; one HSV200 controller is suspect. Termination Code: 03020184 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; both HSV200 controllers are suspect. Termination Code: 03030102 Severity: Critical -- failure or failure imminent. Invalid value in switch statement. Termination Code: 03040102 Severity: Critical -- failure or failure imminent. The minimum number of quorum disks is no longer accessible. Backend hardware failure, backend configuration problems, or HSV200 controller hardware failure are all possible causes. Termination Code: 03060184 Severity: Critical -- failure or failure imminent. An error for which no recovery is possible occurred. Termination Code: 030a0102 Severity: Critical -- failure or failure imminent. Index out of bounds in scsscsdb_get_scsdb_ds call. Termination Code: 030b0101 Severity: Critical -- failure or failure imminent. Area offset unknown in scsscsdb_get_scsdb_ds call. Termination Code: 030c0100 Severity: Critical -- failure or failure imminent. All SCSDB cache pages in use. Termination Code: 030d0101 Severity: Critical -- failure or failure imminent. scsscsdb_free_scsdb_page cache inconsistency. Termination Code: 030e0102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 030f0101 Severity: Critical -- failure or failure imminent. Call to commit SCSDB while cache page dirty or in use. Termination Code: 03100102 Severity: Critical -- failure or failure imminent. Index out of bounds in scscvmdb_get_cvmdb_ds call. Termination Code: 03110101 Severity: Critical -- failure or failure imminent. Area offset unknown in scscvmdb_get_cvmdb_ds call. Termination Code: 03120100 Severity: Critical -- failure or failure imminent. All CVMDB cache pages in use. Termination Code: 03130101 Severity: Critical -- failure or failure imminent. scscvmdb_free_cvmdb_page cache inconsistency. Termination Code: 03140102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 03150101 Severity: Critical -- failure or failure imminent. Call to commit CVMDB while cache page dirty or in use. Termination Code: 03160100 Severity: Critical -- failure or failure imminent. Unable to allocate login maps. Termination Code: 031f0100 Severity: Critical -- failure or failure imminent. Unable to allocate tdsd pool. Termination Code: 032a0000 Severity: Normal -- informational in nature. Both HSV200 controllers registered as Storage System Master. Termination Code: 033c0106 Severity: Critical -- failure or failure imminent. Invalid port login state in remote port object. Termination Code: 033d0105 Severity: Critical -- failure or failure imminent. Remote port logged_in timer expired in inappropriate login state. Termination Code: 03500020 Severity: Normal -- informational in nature. Crash forced by maintenance invoke CRASH or SCS_DEBUG command. Termination Code: 03510141 Severity: Critical -- failure or failure imminent. Crash forced by other HSV200 controller. Termination Code: 03520140 Severity: Critical -- failure or failure imminent. This controller killed other controller and CPLD_CRASH_ALWAYS set. Termination Code: 03640020 Severity: Normal -- informational in nature. This HSV200 controller was requested to terminate operation and then restart. Termination Code: 03650060 Severity: Normal -- informational in nature. This HSV200 controller was requested to terminate operation and then not restart. Termination Code: 03660060 Severity: Normal -- informational in nature. This HSV200 controller was requested to terminate operation and then power off. Termination Code: 03670000 Severity: Normal -- informational in nature. This HSV200 controller was requested to terminate operation, perform a crash dump and then restart. Termination Code: 03680040 Severity: Normal -- informational in nature. This HSV200 controller was requested to terminate operation, perform a crash dump and then not restart. Termination Code: 03690080 Severity: Normal -- informational in nature. Both HSV200 controllers were requested to terminate operation, perform a crash dump and then restart. Termination Code: 036a00c0 Severity: Normal -- informational in nature. Both HSV200 controllers were requested to terminate operation, perform a crash dump and then not restart. Termination Code: 036b0001 Severity: Normal -- informational in nature. This controller was requested to terminate operation as a result of a unit having cache data that could not fail over. Termination Code: 036c01c8 Severity: Critical -- failure or failure imminent. This special termination event is for engineering debug purpose. Termination Code: 03780101 Severity: Critical -- failure or failure imminent. Unable to realize the CVMDB or SCSDB during Storage System Master failover. Backend hardware failure, backend configuration problems, or HSV200 controller hardware failure are all possible causes. Termination Code: 03790020 Severity: Normal -- informational in nature. This HSV200 controller is restarting in order to use a new version of firmware. Termination Code: 0400011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap (i.e., SIMM operand of twi instruction not a recognized FM_TRAP_TYPE_xxx variant or tw instruction executed). Termination Code: 0401011f Severity: Critical -- failure or failure imminent. Machine Check Interrupt Vector Service Routine (MCIVSR) entered; termination processing interrupted before fm_decode_machine_check could be performed. Termination Code: 0402011f Severity: Critical -- failure or failure imminent. DEBUG statement executed. Termination Code: 0403047f Severity: Undetermined -- more information needed to determine severity. Termination event is recursive -- i.e., the Termination Event Information contained in multiple recent Termination Events array entries is identical and the terminations occurred within a short interval of time. Termination Code: 04050101 Severity: Critical -- failure or failure imminent. Out of range event data block index encountered in fm_update_scelaba_entry. Termination Code: 0406017f Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad. Either the EDC was not updated due to premature termination of post-termination operations or the memory area was corrupted in an unexplained manner. A power supply internal failure could cause this termination. Note: The in progress event information may not describe the event that caused the HSV200 controller to terminate operation depending on how far termination processing got before the event occurred. Termination Code: 0407016a Severity: Critical -- failure or failure imminent. An unexpected event array entry indicated that post-termination operations were terminated prematurely before or during the event report block load. Termination Code: 04080582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV200 controller with the coupled crash flag set. Termination Code: 040905a2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV200 controller with the coupled crash flag set. Termination Code: 040a05c2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV200 controller with the coupled crash flag set. Termination Code: 040b05e2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV200 controller with the coupled crash flag set. Termination Code: 040c0582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV200 controller with the coupled crash flag set and an unrecognized Dump/Restart code. Termination Code: 040d0101 Severity: Critical -- failure or failure imminent. Unrecognized fm_update_scelaba_entry operation code encountered. Termination Code: 040e0100 Severity: Critical -- failure or failure imminent. This HSV200 controller is not the Storage System Master when conditions dictate that it should be. Termination Code: 040f0100 Severity: Critical -- failure or failure imminent. This HSV200 controller is the Storage System Master when conditions dictate that it should not be. Termination Code: 04100182 Severity: Critical -- failure or failure imminent. The Storage System Termination Event Log or Storage System Event Log is not active when conditions dictate that it should be. Termination Code: 04110181 Severity: Critical -- failure or failure imminent. The Storage System Termination Event Log or Storage System Event Log is inaccessible. Termination Code: 04120123 Severity: Critical -- failure or failure imminent. An invalid entry or an inconsistency between entries was found in the Last Termination Event array following a controller resynchronization operation; all entries in the array were reset. Termination Code: 04130107 Severity: Critical -- failure or failure imminent. Structure type is not as expected. Termination Code: 04140104 Severity: Critical -- failure or failure imminent. Event Information Packet type is out of range. Termination Code: 04150104 Severity: Critical -- failure or failure imminent. Event Information Packet size is too big. Termination Code: 04160103 Severity: Critical -- failure or failure imminent. Event Information Packet size is not a longword multiple. Termination Code: 04170107 Severity: Critical -- failure or failure imminent. Invalid Storage System Termination Event Log or Storage System Event Log I/O request, no data mapped (unallocated) or object is unknown. Termination Code: 04180107 Severity: Critical -- failure or failure imminent. Unrecognized status returned following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04190100 Severity: Critical -- failure or failure imminent. The restartdebug routine was invoked without a termination having been performed. Termination Code: 041a0100 Severity: Critical -- failure or failure imminent. The Fault Manager's active queue is unexpectedly empty. Termination Code: 041b0105 Severity: Critical -- failure or failure imminent. The Fault Manager detected that the correct event data block was not cached. Termination Code: 041c0100 Severity: Critical -- failure or failure imminent. Calling process is not the Storage System Management Interface or Host Port SCSI as it should be. Termination Code: 041d0100 Severity: Critical -- failure or failure imminent. Calling process is not the Storage System Management Interface as it should be. Termination Code: 041e0102 Severity: Critical -- failure or failure imminent. Termination Event Information Store Packet content is not as expected. Termination Code: 041f0a1f Severity: Critical -- failure or failure imminent. Either a low memory access violation made by the HSV200 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.) or an uncorrectable memory error was detected. Termination Code: 0420011f Severity: Critical -- failure or failure imminent. The HSV200 controller inactivity watchdog timer expired. Termination Code: 04210107 Severity: Critical -- failure or failure imminent. Drive Broken status returned following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04220102 Severity: Critical -- failure or failure imminent. The Software Component ID specified in an Event Code is illegal. Termination Code: 04240960 Severity: Warning -- not failed but attention recommended or required. Power failed. Termination Code: 043f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 0, Reserved exception. Termination Code: 0440011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 100, System Reset exception. Termination Code: 0441011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 200, Machine Check exception. Termination Code: 0442011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 300, DSI exception (i.e., a data memory access cannot be performed). Termination Code: 0443011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 400, ISI exception (i.e., an attempt to fetch the next instruction to be executed failed). Termination Code: 0444011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 500, External Interrupt exception. Termination Code: 0445011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 600, Alignment exception (i.e., a memory access cannot be performed because the address alignment or mode is incompatible for the instruction that was about to be executed). Termination Code: 0446011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 700, Program exception (i.e., execution of an illegal or privileged instruction was attempted). Termination Code: 0447011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 800, Floating-Point Unavailable exception (i.e., an attempt was made to execute a floating-point instruction and the floating-point available bit in the MSR was cleared). Termination Code: 0448011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 900, Decrementer exception. Termination Code: 0449011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector A00, Reserved exception. Termination Code: 044a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector B00, Reserved exception. Termination Code: 044b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector C00, System Call exception. Termination Code: 044c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector D00, Trace exception. Termination Code: 044d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector E00, Floating-Point Assist exception. Termination Code: 044e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector F00, Reserved exception. Termination Code: 044f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1000, Instruction Translation Miss exception. Termination Code: 0450011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1100, Data Load Translation Miss exception. Termination Code: 0451011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1200, Data Store Translation Miss exception. Termination Code: 0452011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1300, Instruction Address Break exception. Termination Code: 0453011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1400, System Management exception. Termination Code: 04540101 Severity: Critical -- failure or failure imminent. Event data block count unexpected. Termination Code: 04550101 Severity: Critical -- failure or failure imminent. FM_locate_event_info received unexpected event retrieval status. Termination Code: 04560102 Severity: Critical -- failure or failure imminent. FM_activeq_read_event was unable to satisfy an active queue event request due to an internal inconsistency. Termination Code: 04570105 Severity: Critical -- failure or failure imminent. A direct call to FM_x_terminate_ctl was made. FM_terminate_ctl_user or FM_terminate_ctl_isr must be used instead. Termination Code: 0458011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1500, Reserved exception. Termination Code: 0459011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1600, Altivec exception. Termination Code: 045a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1700, Reserved exception. Termination Code: 045b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1800, Reserved exception. Termination Code: 045c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1900, Reserved exception. Termination Code: 045d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1A00, Reserved exception. Termination Code: 045e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1B00, Reserved exception. Termination Code: 045f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1C00, Reserved exception. Termination Code: 0460011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1D00, Reserved exception. Termination Code: 0461011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1E00, Reserved exception. Termination Code: 0462011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1F00, Reserved exception. Termination Code: 0463011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2000, Reserved exception. Termination Code: 0464011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2100, Reserved exception. Termination Code: 0465011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2200, Reserved exception. Termination Code: 0466011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2300, Reserved exception. Termination Code: 0467011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2400, Reserved exception. Termination Code: 0468011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2500, Reserved exception. Termination Code: 0469011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2600, Reserved exception. Termination Code: 046a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2700, Reserved exception. Termination Code: 046b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2800, Reserved exception. Termination Code: 046c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2900, Reserved exception. Termination Code: 046d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2A00, Reserved exception. Termination Code: 046e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2B00, Reserved exception. Termination Code: 046f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2C00, Reserved exception. Termination Code: 0470011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2D00, Reserved exception. Termination Code: 0471011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2E00, Reserved exception. Termination Code: 0472011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2F00, Reserved exception. Termination Code: 04730167 Severity: Critical -- failure or failure imminent. Error encountered while building ADDRESS_MAP. Termination Code: 04740160 Severity: Critical -- failure or failure imminent. Fault Manager Event Log Packet Management Area not allocated. Termination Code: 0476013f Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was completed. Termination Code: 0477013f Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was initiated but not completed. Termination Code: 0478393f Severity: Warning -- not failed but attention recommended or required. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was not initiated, the HSV200 controller's PowerPC was spontaneously reset. Termination Code: 04790020 Severity: Normal -- informational in nature. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; manufacturing full memory test was executed. Termination Code: 047a013f Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; unexpected termination processing state. Termination Code: 047b0022 Severity: Normal -- informational in nature. The HSV200 controller has been requested to be uninitialize by the user. Termination Code: 04810130 Severity: Critical -- failure or failure imminent. The HSV200 controller inactivity watchdog timer expired. Termination Code: 0482206f Severity: Critical -- failure or failure imminent. Cache Memory VTT Voltage Failure. Termination Code: 0483206f Severity: Critical -- failure or failure imminent. Non-Volatile Cache Memory Voltage Failure. Termination Code: 0484206f Severity: Critical -- failure or failure imminent. Volatile Cache Memory Voltage Failure. Termination Code: 0485200f Severity: Critical -- failure or failure imminent. PowerPC Bus Data Parity Error. Termination Code: 04862010 Severity: Critical -- failure or failure imminent. PowerPC Bus Address Parity Error. Termination Code: 0487390e Severity: Warning -- not failed but attention recommended or required. PowerPC L1 Instruction Cache Error. Termination Code: 0488390e Severity: Warning -- not failed but attention recommended or required. PowerPC L1 Data Cache Error. Termination Code: 0489390e Severity: Warning -- not failed but attention recommended or required. PowerPC L2 Cache Tag Parity or L2 Cache Data Parity Error. Termination Code: 048a2015 Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer TimeOut Error. Termination Code: 048b0030 Severity: Normal -- informational in nature. Killed by Other Controller. Termination Code: 048c0030 Severity: Normal -- informational in nature. Software Restart. Termination Code: 048d0030 Severity: Normal -- informational in nature. Button Reset. Termination Code: 048e0114 Severity: Critical -- failure or failure imminent. Atlantis CPU Address Out of Range Error. Termination Code: 048f2015 Severity: Critical -- failure or failure imminent. Atlantis Transfer Type/Initial Value Violation Error. Termination Code: 04900114 Severity: Critical -- failure or failure imminent. Atlantis Access to a Protected Region Error. Termination Code: 04913915 Severity: Warning -- not failed but attention recommended or required. Atlantis Integrated SRAM Parity Error. Termination Code: 04922015 Severity: Critical -- failure or failure imminent. Uncorrectable Policy Memory ECC Error. Termination Code: 04930112 Severity: Critical -- failure or failure imminent. Atlantis Device Burst Violation Error. Termination Code: 04942013 Severity: Critical -- failure or failure imminent. Atlantis Device Ready Timeout Error. Termination Code: 04952013 Severity: Critical -- failure or failure imminent. Atlantis Device Address or Data Parity Error. Termination Code: 04960112 Severity: Critical -- failure or failure imminent. Atlantis DMA Failure to Decode Address Error. Termination Code: 04970112 Severity: Critical -- failure or failure imminent. Atlantis DMA Access Protection Violation Error. Termination Code: 04980112 Severity: Critical -- failure or failure imminent. Atlantis DMA Write Protect Violation Error. Termination Code: 04990112 Severity: Critical -- failure or failure imminent. Atlantis DMA Attempt to Access the Descriptor Owned by the CPU. Termination Code: 049a010f Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer Timeout on PCIX Error. Termination Code: 049b2010 Severity: Critical -- failure or failure imminent. Sprite PowerPC Last Entry Error. Termination Code: 049c2010 Severity: Critical -- failure or failure imminent. Sprite PowerPC Alignment Error. Termination Code: 049d3910 Severity: Warning -- not failed but attention recommended or required. Sprite Queue Read Data Parity Error. Termination Code: 049e010f Severity: Critical -- failure or failure imminent. Sprite PCIX Access Error - Not a 4-Byte Access. Termination Code: 049f2011 Severity: Critical -- failure or failure imminent. Sprite Queue Detected an Invalid Destination Error. Termination Code: 04a0011b Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - TimeOut Error. Termination Code: 04a1011b Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Start Frame Error. Termination Code: 04a2011b Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - End Frame Error. Termination Code: 04a3391c Severity: Warning -- not failed but attention recommended or required. Sprite XOR-DMA - Parity Error. Termination Code: 04a4011b Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Invalid Opcode Error. Termination Code: 04a5011b Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Count Error. Termination Code: 04a62011 Severity: Critical -- failure or failure imminent. Sprite Bad Write Data Error. Termination Code: 04a73911 Severity: Warning -- not failed but attention recommended or required. Sprite Command/Data Parity Error. Termination Code: 04a82011 Severity: Critical -- failure or failure imminent. Sprite New Command Bad Error. Termination Code: 04a92016 Severity: Critical -- failure or failure imminent. Uncorrectable Cache Memory ECC Error. Termination Code: 04aa2012 Severity: Critical -- failure or failure imminent. Sprite No Beginning-Of-Frame or Invalid Single Destination Error. Termination Code: 04ab2012 Severity: Critical -- failure or failure imminent. Sprite Transaction Length MisMatch Error. Termination Code: 04ac3912 Severity: Warning -- not failed but attention recommended or required. Sprite Transaction Entry Read Parity Error. Termination Code: 04ad0111 Severity: Critical -- failure or failure imminent. Sprite Bite-Count (BC) MisMatch Error (Transaction BC != BC in FIFO). Termination Code: 04ae0111 Severity: Critical -- failure or failure imminent. Sprite Target Retry-Count Exceeded Error. Termination Code: 04af0111 Severity: Critical -- failure or failure imminent. Sprite Initiator Retry-Count Exceeded Error. Termination Code: 04b00111 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Count Exceeded Error. Termination Code: 04b10111 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Error Message Received Error. Termination Code: 04b20111 Severity: Critical -- failure or failure imminent. Sprite UnExpected Split-Completion Error. Termination Code: 04b30111 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Invalid Termination Error. Termination Code: 04b40111 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Without a Previous Split-Response Error. Termination Code: 04b52012 Severity: Critical -- failure or failure imminent. Sprite PCIX PERR Asserted Error. Termination Code: 04b60112 Severity: Critical -- failure or failure imminent. Sprite performed a Master Abort Error. Termination Code: 04b72012 Severity: Critical -- failure or failure imminent. Sprite received a Target Abort Error. Termination Code: 04b82012 Severity: Critical -- failure or failure imminent. Sprite asserted SERR. Termination Code: 04b92012 Severity: Critical -- failure or failure imminent. Sprite detected SERR. Termination Code: 04ba011b Severity: Critical -- failure or failure imminent. Tachyon Unsupported Byte Enable Error. Termination Code: 04bb391b Severity: Warning -- not failed but attention recommended or required. Tachyon Outbound Parity Error. Termination Code: 04bc391b Severity: Warning -- not failed but attention recommended or required. Tachyon Inbound Parity Error. Termination Code: 04bd201c Severity: Critical -- failure or failure imminent. Tachyon Detected Parity Error. Termination Code: 04be201c Severity: Critical -- failure or failure imminent. Tachyon Signaled System Error (SERR). Termination Code: 04bf011b Severity: Critical -- failure or failure imminent. Tachyon Received Master Abort Error. Termination Code: 04c0201c Severity: Critical -- failure or failure imminent. Tachyon Received Target Abort Error. Termination Code: 04c1201c Severity: Critical -- failure or failure imminent. Tachyon Signaled Target Abort Error. Termination Code: 04c2201c Severity: Critical -- failure or failure imminent. Tachyon Master Data Parity Error. Termination Code: 04c3011b Severity: Critical -- failure or failure imminent. Tachyon Unexpected Split-Completion Error. Termination Code: 04c4011b Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Discarded Error. Termination Code: 04c5391c Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Split Related Transaction. Termination Code: 04c6391c Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Incoming Data. Termination Code: 04c7391c Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Outgoing Data. Termination Code: 04c8201c Severity: Critical -- failure or failure imminent. Tachyon Attribute Parity Error. Termination Code: 04c9011b Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Byte Count Excessive. Termination Code: 04ca011b Severity: Critical -- failure or failure imminent. Tachyon Read Byte Count Excessive Error. Termination Code: 04cb011b Severity: Critical -- failure or failure imminent. Tachyon Read FIFO Parity Error. Termination Code: 04cc011b Severity: Critical -- failure or failure imminent. Tachyon Write FIFO Parity Error. Termination Code: 04cd011b Severity: Critical -- failure or failure imminent. Tachyon Reserved Region Access Error. Termination Code: 04ce010d Severity: Critical -- failure or failure imminent. Tachyon Parity Error on Split Completion Error. Termination Code: 04cf011a Severity: Critical -- failure or failure imminent. Undecoded machine check. Termination Code: 04d00180 Severity: Critical -- failure or failure imminent. Manufacturing Event Analysis Log Commit Packet unexpectedly in use. Termination Code: 04f6013f Severity: Critical -- failure or failure imminent. User termination test all parameters. Termination Code: 04f70000 Severity: Normal -- informational in nature. Console requested restart with dump (not coupled) via CTRL-Z. Termination Code: 04f9017f Severity: Critical -- failure or failure imminent. Poweroff test. Termination Code: 04fa0100 Severity: Critical -- failure or failure imminent. User termination test no parameters. Termination Code: 04fb011f Severity: Critical -- failure or failure imminent. User termination test all parameters. Termination Code: 04fc0100 Severity: Critical -- failure or failure imminent. ISR termination test no parameters. Termination Code: 04fd011f Severity: Critical -- failure or failure imminent. ISR termination test all parameters. Termination Code: 04fe0100 Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 04ff011f Severity: Critical -- failure or failure imminent. EXEC_BUGCHECK statement executed. Termination Code: 06040100 Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ. Termination Code: 06150100 Severity: Critical -- failure or failure imminent. Failed memory allocation for Fibre Channel Services Crash Dump structure. Termination Code: 061c0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ. Termination Code: 061d0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for MFC copy buffer. Termination Code: 06200100 Severity: Critical -- failure or failure imminent. Invalid Completion Message type. Termination Code: 06230100 Severity: Critical -- failure or failure imminent. Class 2 Failure for outbound sequence. Termination Code: 0624011f Severity: Critical -- failure or failure imminent. Host Programming error. Termination Code: 06280100 Severity: Critical -- failure or failure imminent. Invalid Port Event Type. Termination Code: 06290100 Severity: Critical -- failure or failure imminent. Unknown FED type found. Termination Code: 062a0100 Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup. Termination Code: 062b0100 Severity: Critical -- failure or failure imminent. Fail status returned for timer start. Termination Code: 062c0100 Severity: Critical -- failure or failure imminent. Unexpected loop state. Termination Code: 062e0100 Severity: Critical -- failure or failure imminent. SEST programming error. Termination Code: 062f0100 Severity: Critical -- failure or failure imminent. SEST programming error. Termination Code: 06320100 Severity: Critical -- failure or failure imminent. Port chip failed to go Offline. Termination Code: 06330100 Severity: Critical -- failure or failure imminent. Out of Reserved FEDs. Termination Code: 06340100 Severity: Critical -- failure or failure imminent. Unsupported ELS requested. Termination Code: 06360100 Severity: Critical -- failure or failure imminent. Unsupported drive initialization sequence command. Termination Code: 06380100 Severity: Critical -- failure or failure imminent. Unsupported TDS requested. Termination Code: 063c0100 Severity: Critical -- failure or failure imminent. Command issued to an illegal LBA. Termination Code: 06410100 Severity: Critical -- failure or failure imminent. Unknown SCSI status byte. Termination Code: 06420100 Severity: Critical -- failure or failure imminent. No backend ports were available for a mirror cache transfer Termination Code: 06460100 Severity: Critical -- failure or failure imminent. Unsupported SES page for Receive Diagnostic Results. Termination Code: 06470100 Severity: Critical -- failure or failure imminent. Unsupported SES String In subpage for Receive Diagnostic Results. Termination Code: 06500080 Severity: Normal -- informational in nature. Unsupported SES page for Receive Diagnostic Results. Termination Code: 0651011f Severity: Critical -- failure or failure imminent. FED for handling MFC ACK was not on the In-process Queue as expected. Termination Code: 07000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 07010100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07020100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07030100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07070100 Severity: Critical -- failure or failure imminent. Failed reading QS. Termination Code: 070a0100 Severity: Critical -- failure or failure imminent. RSD allocation failed. Termination Code: 070b0100 Severity: Critical -- failure or failure imminent. LDSB ref_count is off Termination Code: 070c0100 Severity: Critical -- failure or failure imminent. Invalid Object Class for I/O request. Termination Code: 070d0100 Severity: Critical -- failure or failure imminent. Invalid I/O range for given object. Termination Code: 07110100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07130100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07140100 Severity: Critical -- failure or failure imminent. Invalid structure - Zero process. Termination Code: 07150100 Severity: Critical -- failure or failure imminent. Invalid structure - Zero process. Termination Code: 07160100 Severity: Critical -- failure or failure imminent. Invalid structure - ODWORK process. Termination Code: 07170100 Severity: Critical -- failure or failure imminent. Program buffer leak detected. Termination Code: 07180100 Severity: Critical -- failure or failure imminent. Buffer pool leak detected. Termination Code: 07190100 Severity: Critical -- failure or failure imminent. Code not yet implemented. Termination Code: 071a0100 Severity: Critical -- failure or failure imminent. Wrong LDSB returned to waiting abort requester. Termination Code: 071b0100 Severity: Critical -- failure or failure imminent. Wrong LDAD returned to waiting abort requester. Termination Code: 071c0100 Severity: Critical -- failure or failure imminent. Bad map type for read merge. Termination Code: 071d0100 Severity: Critical -- failure or failure imminent. Cache hit occurred while performing read merge. Termination Code: 071e0100 Severity: Critical -- failure or failure imminent. PSAR indicates invalid usage. Termination Code: 071f0100 Severity: Critical -- failure or failure imminent. Bad object class in Regen/Replace. Termination Code: 07200100 Severity: Critical -- failure or failure imminent. No Free CMAPs. Termination Code: 07220100 Severity: Critical -- failure or failure imminent. Invalid CS Drive Request. Termination Code: 07240100 Severity: Critical -- failure or failure imminent. No Free CS Req items. Termination Code: 07260100 Severity: Critical -- failure or failure imminent. Invalid Volnoid encountered. Termination Code: 07290100 Severity: Critical -- failure or failure imminent. Multiple Metadata Transactions Detected. Termination Code: 072a0100 Severity: Critical -- failure or failure imminent. I/O Failed in CS$RECOVER_TRANSACTIONS. Termination Code: 072b0100 Severity: Critical -- failure or failure imminent. Invalid Transaction type. Termination Code: 072d0100 Severity: Critical -- failure or failure imminent. No Transaction was found. Termination Code: 072f0100 Severity: Critical -- failure or failure imminent. Member State not supported in zero_rsdm. Termination Code: 07300100 Severity: Critical -- failure or failure imminent. Regen of Member should be complete, but is not. Termination Code: 07340100 Severity: Critical -- failure or failure imminent. Bad CS Req Object Class in handle CS Req. Termination Code: 07350100 Severity: Critical -- failure or failure imminent. Invalid CS Req Operation in handle CS Req. Termination Code: 07370100 Severity: Critical -- failure or failure imminent. Invalid Volnoid in Sparing Process. Termination Code: 07380100 Severity: Critical -- failure or failure imminent. No XDs available for cs_req operation Termination Code: 07390100 Severity: Critical -- failure or failure imminent. Invalid Raid Type in Regen/Reassign. Termination Code: 073b0100 Severity: Critical -- failure or failure imminent. Unknown CS Transaction type for Journaling. Termination Code: 073c0100 Severity: Critical -- failure or failure imminent. CS Journal Transaction inconsistency. Termination Code: 073d0100 Severity: Critical -- failure or failure imminent. Invalid CS Transaction type for Journaling operation. Termination Code: 073e0100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Leveling process. Termination Code: 073f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore Sparing process. Termination Code: 07400100 Severity: Critical -- failure or failure imminent. Invalid structure - CS Req process. Termination Code: 07410100 Severity: Critical -- failure or failure imminent. Invalid structure - PLDMC process. Termination Code: 07420100 Severity: Critical -- failure or failure imminent. No Free RLBs (RSD Lock Blocks). Termination Code: 07430100 Severity: Critical -- failure or failure imminent. RLB List is inconsistent. Termination Code: 07440100 Severity: Critical -- failure or failure imminent. RLB state is inconsistent. Termination Code: 07450100 Severity: Critical -- failure or failure imminent. Invalid structure - CS CSLD process. Termination Code: 07460100 Severity: Critical -- failure or failure imminent. Invalid structure - CS E-bit handler. Termination Code: 07480100 Severity: Critical -- failure or failure imminent. Illegal QS I/O by Non Storage System Master. Termination Code: 07490100 Severity: Critical -- failure or failure imminent. Illegal CSLD I/O by Non Storage System Master. Termination Code: 074a0100 Severity: Critical -- failure or failure imminent. Invalid structure - ACBW process. Termination Code: 074b0100 Severity: Critical -- failure or failure imminent. Invalid ACBW Opcode. Termination Code: 074c0100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 074f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RSS Migration process. Termination Code: 07500100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore Migration process. Termination Code: 07510100 Severity: Critical -- failure or failure imminent. Member State not supported. Termination Code: 07520100 Severity: Critical -- failure or failure imminent. Metadata is inaccessible; an inoperative condition has occurred. Termination Code: 07530100 Severity: Critical -- failure or failure imminent. An invalid structure was encountered on an ALB list. Termination Code: 07540100 Severity: Critical -- failure or failure imminent. LMAP does not point to RStore, and RStore not being allocated. Termination Code: 07550100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Allocation work process. Termination Code: 07570100 Severity: Critical -- failure or failure imminent. Realize or realize_temp failed. Termination Code: 07580100 Severity: Critical -- failure or failure imminent. Unrealize or unrealize_temp failed. Termination Code: 07590100 Severity: Critical -- failure or failure imminent. Unit realized before initial allocation completed Termination Code: 075b0100 Severity: Critical -- failure or failure imminent. An I/O that should NOT fail, did. Termination Code: 075d0100 Severity: Critical -- failure or failure imminent. Invalid structure - CS C-bit handler. Termination Code: 075e0100 Severity: Critical -- failure or failure imminent. Invalid structure - OD bg aloc process. Termination Code: 075f0100 Severity: Critical -- failure or failure imminent. DUB and RSS do not agree with each other. Termination Code: 07600100 Severity: Critical -- failure or failure imminent. Invalid LD type Termination Code: 07610100 Severity: Critical -- failure or failure imminent. Invalid DIP State in LD Termination Code: 07620100 Severity: Critical -- failure or failure imminent. Deallocation failed Termination Code: 07630100 Severity: Critical -- failure or failure imminent. Failure to validate reserved capacity on each rss member Termination Code: 07640100 Severity: Critical -- failure or failure imminent. Invalid structure - REBUILD PARITY MAIN Termination Code: 07680100 Severity: Critical -- failure or failure imminent. An RSS member has been removed unexpectedly. Termination Code: 07690102 Severity: Critical -- failure or failure imminent. An unsupported member manager state has occurred. Termination Code: 076a0100 Severity: Critical -- failure or failure imminent. No Quorum Disks have been discovered. Termination Code: 076b0100 Severity: Critical -- failure or failure imminent. Invalid/unknown pseg allocation type Termination Code: 076c0100 Severity: Critical -- failure or failure imminent. XMFC Failure - other controller gone during communication with it. Termination Code: 076d0100 Severity: Critical -- failure or failure imminent. Invalid XMFC operation. Termination Code: 076e0100 Severity: Critical -- failure or failure imminent. Invalid type in RSDM. Termination Code: 07700105 Severity: Critical -- failure or failure imminent. CHKDSK test failed Termination Code: 07710100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 07720100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 07730100 Severity: Critical -- failure or failure imminent. The RSD pointer should have been NULL but wasn't Termination Code: 07740100 Severity: Critical -- failure or failure imminent. Shadow initial synchronization encountered bad data Termination Code: 07750100 Severity: Critical -- failure or failure imminent. The LD should have not been realized but was Termination Code: 08010100 Severity: Critical -- failure or failure imminent. Bad status from CS$SET_EBIT Termination Code: 08020100 Severity: Critical -- failure or failure imminent. An abnormal member's member_state is not supported Termination Code: 08030100 Severity: Critical -- failure or failure imminent. A request was made to do I/O for an undefined RAID type. Termination Code: 08040100 Severity: Critical -- failure or failure imminent. Drive rewrite function is not supported Termination Code: 08050100 Severity: Critical -- failure or failure imminent. A sprite DMA transaction completed with an interrupt but the DMA context queue was empty Termination Code: 08060100 Severity: Critical -- failure or failure imminent. Unable to save DMA context because the Queue is full Termination Code: 08070100 Severity: Critical -- failure or failure imminent. Cannot dynamically allocate enough memory to store waiters for ptr 9687 fix. Termination Code: 08080100 Severity: Critical -- failure or failure imminent. Unsupported structure type passed into RS function Termination Code: 08090100 Severity: Critical -- failure or failure imminent. Sprite CDB memory has been corrupted Termination Code: 080a0100 Severity: Critical -- failure or failure imminent. Sprite returned an error that we don't know how to handle yet Termination Code: 080f0100 Severity: Critical -- failure or failure imminent. Sprite DMA context queue is out of sync with interrupts Termination Code: 09010100 Severity: Critical -- failure or failure imminent. EXEC_init_bque failed. Termination Code: 09020100 Severity: Critical -- failure or failure imminent. Memory allocation failed for Storage System Management Interface CP/RP (task block). Termination Code: 09040100 Severity: Critical -- failure or failure imminent. Storage System Management Interface detected an internal inconsistency. Termination Code: 09060100 Severity: Critical -- failure or failure imminent. Memory allocation failed for return buffer. Termination Code: 09080100 Severity: Critical -- failure or failure imminent. Insufficient resources available for SCMI Command Lock dynamic allocation. Termination Code: 09090100 Severity: Critical -- failure or failure imminent. Insufficient resources available for SCMI Command Lock initial allocation. Termination Code: 0b000100 Severity: Critical -- failure or failure imminent. Invalid XMFC Response Packet. Termination Code: 0b010100 Severity: Critical -- failure or failure imminent. Invalid MFC Vector (Index). Termination Code: 0b020100 Severity: Critical -- failure or failure imminent. Invalid System Activity Collection state. Termination Code: 0b040100 Severity: Critical -- failure or failure imminent. Invalid System Utility (Code Load or Resynchronization) state. Termination Code: 0b052001 Severity: Critical -- failure or failure imminent. Attempt to access EEPROM for UUID Range failed. Termination Code: 0b062001 Severity: Critical -- failure or failure imminent. UUID Range overflow. Termination Code: 0b080100 Severity: Critical -- failure or failure imminent. A resynchronization was requested at an inappropriate time. Termination Code: 0b092003 Severity: Critical -- failure or failure imminent. Attempt to access Operator Control Panel failed. Termination Code: 0b0a0100 Severity: Critical -- failure or failure imminent. Invalid XMFC State. Termination Code: 0b100021 Severity: Normal -- informational in nature. New glue code available, attempting a force load which requires a restart after the load is successful. Termination Code: 0b110020 Severity: Normal -- informational in nature. New boot code available, attempting a force load following restart. Termination Code: 0b12db60 Severity: Warning -- not failed but attention recommended or required. Attempt to load Non-ROHS compliant firmware onto a ROHS complaint controller or Non-CR2 firmware onto a CR2 controller was prevented. Termination Code: 0c010102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command. Termination Code: 0c03010c Severity: Critical -- failure or failure imminent. Invalid state exists for deleting a Group State Block. Termination Code: 0c040101 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The group sequence number node already exists. Termination Code: 0c050106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery write data was not in cache as expected. Termination Code: 0c060106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery write data found in cache was not marked dirty write-back cached data as expected. Termination Code: 0c070106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: Lookup of group sequence number node failed. Termination Code: 0c080106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected. Termination Code: 0c090106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: Not all group members were processed. Termination Code: 0c0a0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the primary was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected. Termination Code: 0c0b0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the primary was declared invalid: Not all group members were processed. Termination Code: 0c0c0104 Severity: Critical -- failure or failure imminent. A software problem was found when deleting the Group State Block: Transfers were not completely run down. Termination Code: 0c0d0104 Severity: Critical -- failure or failure imminent. A software problem was found when inserting a Group State Block into the active list: A Group State Block with this same Universal Unique Identifier is already on the active list. Termination Code: 0c0e0106 Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected in the transfer path upon remote write completion after the mirror controller was updated; A Full Copy of the affected Data Replication Group may be initiated upon the next controller restart. Termination Code: 0c0f0105 Severity: Critical -- failure or failure imminent. Setting the e-bit failed for a write long command on the destination unit. Termination Code: 0c100104 Severity: Critical -- failure or failure imminent. An attempt was made to acquire the Data Replication Manager Remote Response Waiter, but it was unexpectedly already in use. Termination Code: 0c110105 Severity: Critical -- failure or failure imminent. A Group Sequence Number Node was lost during mirror synchronization. Termination Code: 0c130105 Severity: Critical -- failure or failure imminent. An unexpected I/O failure occurred: Container Services was unable to write to the PLDMC on media. Termination Code: 0c140106 Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected in the transfer path on the mirror side upon remote write completion; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c150106 Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected upon controller restart or failover when building the list of incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c160106 Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected upon controller restart or failover when completing previously incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c170106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the received group sequence number was detected after a controller restarted, when synchonizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c180106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use and sent group sequence numbers was detected after a controller restarted, when synchronizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c190106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the received group sequence number was detected after a controller restarted, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c1a0106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use and sent group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c1b0106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c1c0107 Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected after a controller restart when synchronizing the mirror writes with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c200106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c210106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too high; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c220108 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c230105 Severity: Critical -- failure or failure imminent. A Data Replication Group member was detected to be in an unexpected cache state. Termination Code: 0c240107 Severity: Critical -- failure or failure imminent. Secondary controller selection failed. Termination Code: 0c270106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low. A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c280106 Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low. A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c290105 Severity: Critical -- failure or failure imminent. Data Replication Manager Dual State was not idle for MFC communication between the dual controllers during an add member operation. Termination Code: 0c2a0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management ADD SOURCE command. Termination Code: 0c2b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command when a process is waiting for the ACK. Termination Code: 0c2c0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command when a process is waiting for a DONE response. Termination Code: 0c2d0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating an ADD SOURCE dual controller management command. Termination Code: 0c2e0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating an SITE FAILOVER dual controller management command. Termination Code: 0c2f0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command requiring a DRRW response. Termination Code: 0c300105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating a multi-destinaton dual controller management command. Termination Code: 0c310105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating a dual controller management command that has only an ACK as a response and passes a group object as a parameter. Termination Code: 0c320101 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found in the main dispatch function for dual controller management commands. Termination Code: 0c330103 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found in the main processing function for dual controller management commands. Termination Code: 0c340101 Severity: Critical -- failure or failure imminent. An EETB resource needed for a Data Replication Manager Mirror Request dual controller management command is already in use by another command. Termination Code: 0c350101 Severity: Critical -- failure or failure imminent. An EETB resource expected in response to a Data Replication Manager Mirror Request dual controller management command is missing. Termination Code: 0c360102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while issuing a simple dual controller management command. Termination Code: 0c370102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing the response to a simple dual controller management command. Termination Code: 0c380102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a simple dual controller management command. Termination Code: 0c390102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management command which uses an SCVD object. Termination Code: 0c3a0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a unit related dual controller management command that does not require an additional response. Termination Code: 0c3b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a unit related dual controller management command that requires an additional response. Termination Code: 0c3c0102 Severity: Critical -- failure or failure imminent. An unexpected response to a dual controller management command was received during mirror controller crash cleanup. Termination Code: 0c3d0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a mirror request dual controller management command. Termination Code: 0c3e0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management command to be sent to the mirror controller. Termination Code: 0c3f0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management mirror response. Termination Code: 0c400102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management response to be sent to the mirror controller. Termination Code: 0c410102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while initiating a site failover. Termination Code: 0c420102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management synchronize buffers command. Termination Code: 0c430102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management MDW command. Termination Code: 0c450100 Severity: Critical -- failure or failure imminent. We should not have gone down this path. Termination Code: 0c460103 Severity: Critical -- failure or failure imminent. MFC frame corruption detected. Termination Code: 0c470104 Severity: Critical -- failure or failure imminent. Invalid attempt to associate host adapter ACB with Data Replication Manager destination DDCB. Termination Code: 0c480100 Severity: Critical -- failure or failure imminent. Insufficient free memory available to allocate required DDCB structures. Termination Code: 0c490100 Severity: Critical -- failure or failure imminent. Insufficient free memory available to allocate required RNSB structures. Termination Code: 0c4a0104 Severity: Critical -- failure or failure imminent. Invalid attempt to associate a temporary ACB with Data Replication Manager destination DDCB. Termination Code: 0e000020 Severity: Normal -- informational in nature. Found invalid battery subsystem state. Termination Code: 0e010020 Severity: Normal -- informational in nature. Found invalid battery system hold up time. Termination Code: 0e020020 Severity: Normal -- informational in nature. Found invalid battery brick number. Termination Code: 0e030020 Severity: Normal -- informational in nature. Found invalid battery brick state. Termination Code: 0e050020 Severity: Normal -- informational in nature. Found invalid blower number. Termination Code: 0e060020 Severity: Normal -- informational in nature. Found invalid blower state. Termination Code: 0e080020 Severity: Normal -- informational in nature. Found invalid temperature subsystem state. Termination Code: 0e090020 Severity: Normal -- informational in nature. Found invalid power supply number. Termination Code: 0e0a0020 Severity: Normal -- informational in nature. Found invalid power supply state. Termination Code: 0e0b0020 Severity: Normal -- informational in nature. A command was sent to the SDC microcontroller while it was still busy processing a previous command. Termination Code: 42000101 Severity: Critical -- failure or failure imminent. No memory for HP_init. Termination Code: 42050103 Severity: Critical -- failure or failure imminent. Unexpected Cache Node lock state for WRITE LONG. Termination Code: 42060105 Severity: Critical -- failure or failure imminent. Unexpected outstanding SCSI command on unit. Termination Code: 42070123 Severity: Critical -- failure or failure imminent. DD CDB function 0X42 received. Termination Code: 420801a3 Severity: Critical -- failure or failure imminent. DD CDB function 0X43 received. Termination Code: 420901c3 Severity: Critical -- failure or failure imminent. DD CDB function 0X86 received. Termination Code: 420c0184 Severity: Critical -- failure or failure imminent. Unknown build context received in remote SCSI MFC build routine. Termination Code: 420d0182 Severity: Critical -- failure or failure imminent. Unknown context received in remote SCSI MFC receive routine. Termination Code: 420e0181 Severity: Critical -- failure or failure imminent. ICOPS could not allocate necessary memory. Termination Code: 420f0182 Severity: Critical -- failure or failure imminent. Unknown build context in the ICOPS build routine. Termination Code: 42100182 Severity: Critical -- failure or failure imminent. Unknown receive context in the ICOPS receive routine. Termination Code: 42120104 Severity: Critical -- failure or failure imminent. Illegal structure on in process queue. Termination Code: 42130101 Severity: Critical -- failure or failure imminent. No host port command HTBs. Termination Code: 42140102 Severity: Critical -- failure or failure imminent. Invalid Context in hp_call_get_scsi_data. Termination Code: 42150102 Severity: Critical -- failure or failure imminent. HP_change_host_mode ACB-- not found. Termination Code: 42160102 Severity: Critical -- failure or failure imminent. HP_present_lun-- ACB not found. Termination Code: 42190104 Severity: Critical -- failure or failure imminent. CCB either already in use or improperly marked not used. Termination Code: 421b0102 Severity: Critical -- failure or failure imminent. A work request has an invalid type. Termination Code: 421c0101 Severity: Critical -- failure or failure imminent. Work request resources have run out. Termination Code: 421e0102 Severity: Critical -- failure or failure imminent. Allocated command HTB is already in use. Termination Code: 42230102 Severity: Critical -- failure or failure imminent. HP_unpresent_lun ACB not found. Termination Code: 42250104 Severity: Critical -- failure or failure imminent. Could not delete the ACB. Termination Code: 42260104 Severity: Critical -- failure or failure imminent. Did not have a Unit Attention table and units are presented. Termination Code: 42270108 Severity: Critical -- failure or failure imminent. Port event handler had an unknown port event. Termination Code: 42280102 Severity: Critical -- failure or failure imminent. Unknown completion message from the Tachyon. Termination Code: 42290103 Severity: Critical -- failure or failure imminent. Received an illegal SEST id. Termination Code: 422a0103 Severity: Critical -- failure or failure imminent. Received a bad AL_PA from the Tachyon on a point to point topology. Termination Code: 422b0103 Severity: Critical -- failure or failure imminent. Received an unknown error idle status from the Tachyon. Termination Code: 422c0003 Severity: Normal -- informational in nature. Received an unknown error idle status from the Tachyon. Termination Code: 422d010a Severity: Critical -- failure or failure imminent. Received an unknown I/O error value. Termination Code: 422e0104 Severity: Critical -- failure or failure imminent. Had a LUN with write only access. Termination Code: 422f0103 Severity: Critical -- failure or failure imminent. Received an unknown FCP inbound completion status. Termination Code: 42300103 Severity: Critical -- failure or failure imminent. Received an illegal script response. Termination Code: 42310102 Severity: Critical -- failure or failure imminent. Received an illegal error status in the error routine. Termination Code: 42320104 Severity: Critical -- failure or failure imminent. Requested to present a LUN that is already in existence or is illegal Termination Code: 4233010a Severity: Critical -- failure or failure imminent. An internal request was made to return a status of Not Ready for work created in the controller. Termination Code: 42340104 Severity: Critical -- failure or failure imminent. The state for a command with the Immed bit set in the CDB is incorrect. Termination Code: 42350104 Severity: Critical -- failure or failure imminent. A unit unquiesce was called without the corresponding quiesce. Termination Code: 42360102 Severity: Critical -- failure or failure imminent. A call to notify of new ELP encountered an invalid CSEL state. Termination Code: 42370183 Severity: Critical -- failure or failure imminent. Gap in Sequence Numbers for Event Logs. Termination Code: 4238011f Severity: Critical -- failure or failure imminent. The host port has detected a CSM reset after 60 minutes. Termination Code: 42390184 Severity: Critical -- failure or failure imminent. Invalid proxy io operation state Termination Code: 423a0102 Severity: Critical -- failure or failure imminent. Logical port number out of range to access S_pcb[] Termination Code: 423b0102 Severity: Critical -- failure or failure imminent. The tachyon chip is not responding. The controller will be restarted so that diagnostics can be executed. Termination Code: 423c0306 Severity: Undetermined -- more information needed to determine severity. An attempt was made to create a client using the remote port world wide name of a Data Replication Path.The controller will be restarted so this condition can be cleared. Termination Code: 83002061 Severity: Critical -- failure or failure imminent. DOG cannot branch to this routine. Termination Code: 83012079 Severity: Critical -- failure or failure imminent. DOG unexpected vector to error. Termination Code: 8302206b Severity: Critical -- failure or failure imminent. DOG non-fault tolerant hard error. Termination Code: 84032069 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in cache memory. Termination Code: 84042065 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in policy memory. EVENT INFORMATION PACKETS: Event Information Packet Type: 1 EIP01 - Fault Manager Termination Processing Recursive Entry Event A machine check occurred while a termination event was being processed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} union hdu Termination Event Information Header {lteihd (Active if Termination Event Information Header revision is greater than 3)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort size Structure size {} or hdu Termination Event Information Header {lteihd0 (Active if Termination Event Information Header revision is less than or equal to 3)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved {} utiny revision Structure revision number ushort size Structure size {} endunion hdu Termination Event Information Header union ru Termination Event Reporting Information {lter (Active if Termination Event Information Header revision greater than 3)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {} utiny[2] reserved Reserved {flags (Other Last Termination Event flags)} tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} or ru Termination Event Reporting Information {lter0 (Active if Termination Event Information Header revision is less than or equal to 3)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {} utiny[2] reserved Reserved utiny lg_send_sts Last Gasp send status utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} endunion ru Termination Event Reporting Information {rei (Recursive Entry Event Information)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong lr LR register ulong exception Exception code {} {} Event Information Packet Type: 2 EIP02 - Fault Manager Termination Processing Unexpected Event An unexpected event occurred while a termination event was being processed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} union hdu Termination Event Information Header {lteihd (Active if Termination Event Information Header revision is greater than 3)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort size Structure size {} or hdu Termination Event Information Header {lteihd0 (Active if Termination Event Information Header revision is less than or equal to 3)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved {} utiny revision Structure revision number ushort size Structure size {} endunion hdu Termination Event Information Header union ru Termination Event Reporting Information {lter (Active if Termination Event Information Header revision greater than 3)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {} utiny[2] reserved Reserved {flags (Other Last Termination Event flags)} tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} or ru Termination Event Reporting Information {lter0 (Active if Termination Event Information Header revision is less than or equal to 3)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {} utiny[2] reserved Reserved utiny lg_send_sts Last Gasp send status utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} endunion ru Termination Event Reporting Information {uei (Unexpected Event Information)} ulong type Unexpected event type ulong pto Post-Termination Operation Indicator ulong[5] param Unexpected event parameters {} {} Event Information Packet Type: 3 EIP03 - Fault Manager Management Event An event that affects Fault Manager operation occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} union ainfo Ancillary Information Union ulong events_not_reported Number of events not reported do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union ulong quiesce_type Quiesce type do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union {remote_event (Remote event header information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} endunion ainfo Ancillary Information Union union cinfo Control Block Information Union {scelcbi (Storage System Event Log Control Block Information)} ushort current_offset Current offset within event buffer {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} utiny status Maintenance status ulong current_edbn Current event data block number ulong start_edbn Storage System State Logical Disk-Storage System Event Log starting event data block number ulong end_edbn Storage System State Logical Disk-Storage System Event Log ending event data block number ulong seq_reset_edbn Event data block number where sequence number reset occurred ulong event_count Number of events contained in Storage System State Logical Disk-Storage System Event Log ulong event_count_wraps Event count overflow ulong sequence_number Last event sequence number used {} do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union {sctelcbi (Storage System Termination Event Log Control Block Information)} ushort reserved Reserved for future use {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 bctrlr_wrapped All termination event data blocks in use for "B" HSV200 controller tbits:1 bctrlr_valid "B" HSV200 controller's Storage System State Logical Disk-Storage System Termination Event Log information is valid tbits:1 actrlr_wrapped All termination event data blocks in use for "A" HSV200 controller tbits:1 actrlr_valid "A" HSV200 controller's Storage System State Logical Disk-Storage System Termination Event Log information is valid tbits:2 rsvd Pad to fill byte {} utiny status Maintenance status uuid actrlr_id "A" HSV200 controller's UUID ulong actrlr_mru_edbn "A" HSV200 controller's Storage System State Logical Disk-Storage System Termination Event Log most recently used event data block number uuid bctrlr_id "B" HSV200 controller's UUID ulong bctrlr_mru_edbn "B" HSV200 controller's Storage System State Logical Disk-Storage System Termination Event Log most recently used event data block number {} or cinfo Control Block Information Union {stats30 (Last 30 seconds activity summary)} {host (Host Activity,)} ulong rps Requests Per Second, ulong kbs KB/Second. {} {mirror (Mirror Activity,)} ulong rps Requests Per Second, ulong kbs KB/Second. {} {backend (Backend Activity,)} ulong rps Requests Per Second, ulong kbs KB/Second. {} {total (Total Activity,)} ulong rps Requests Per Second, ulong kbs KB/Second. {} {background (Background Activity.)} ulong rps Requests Per Second, ulong kbs KB/Second. {} {} do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union {mealcbi (Manufacturing Event Analysis Log Control Block information)} ushort current_offset Current offset within event buffer {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} utiny status Maintenance status ulong current_edbn Current event data block number ulong start_edbn Manufacturing Event Analysis Log starting event data block number ulong end_edbn Manufacturing Event Analysis Log ending event data block number ulong seq_reset_edbn Event data block number where sequence number reset occurred ulong event_count Number of events contained in Manufacturing Event Analysis Log ulong event_count_wraps Event count overflow ulong sequence_number Last event sequence number used {} do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) endunion cinfo Control Block Information Union union minfo Maintenance Information Union {scelmi (Storage System Event Log Maintenance Information)} ulong index Loop index *ptr *utp Zero test buffer pointer ulong current_eventp Pointer to the current event ulong current_edbn Current event data block number ulong current_seqn Current sequence number ushort previous_offset Previous event buffer offset ushort current_offset Current event buffer offset ulong previous_edbn Previous event data block number ulong previous_seqn Previous sequence number ulong end_found End of Storage System State Logical Disk-Storage System Event Log found flag ulong accept_new_to_old New to old transition acceptable flag ulong unequal_found Sequence number not as expected flag ulong iostatus I/O status {} or minfo Maintenance Information Union {sctelmi (Storage System Termination Event Log Maintenance Information)} ulong index Loop index ulong current_edbn Current event data block number ulong end_edbn End event data block number ulong actrlr If "A" HSV200 controller, TRUE ulong iostatus I/O status ulong hold_offset Hold buffer current offset {} do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union {lerinfo (Last Event Reported Information)} ulong reporting_interval Last event reporting interval ulong sequence_number Sequence number assigned to the event scmitim report_time Time event was reported {header (Event Header)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {} do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union {mealmi (Manufacturing Event Analysis Log Maintenance Information)} ulong index Loop index *ptr *utp Zero test buffer pointer ulong current_eventp Pointer to the current event ulong current_edbn Current event data block number ulong current_seqn Current sequence number ushort previous_offset Previous event buffer offset ushort current_offset Current event buffer offset ulong previous_edbn Previous event data block number ulong previous_seqn Previous sequence number ulong end_found End of Manufacturing Event Analysis Log found flag ulong accept_new_to_old New to old transition acceptable flag ulong unequal_found Sequence number not as expected flag ulong first_seqn First sequence number {} endunion minfo Maintenance Information Union {} Event Information Packet Type: 4 EIP04 - Fibre Channel Services Physical Disk Drive Error An error was encountered while accessing a physical disk drive. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag device UUID of physical disk drive associated with the event char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port ulong al_pa AL_PA of the physical disk drive or mirror port ushort dencl_num Enclosure where the physical disk drive is located ushort port HSV200 controller internal Fibre Channel port number attached to the physical disk drive or mirror port ushort rack_num Rack where physical disk drive is located ushort bay Enclosure bay where the physical disk drive is located char[16] pid Physical disk drive product identification string char[4] rev Current firmware level of physical disk drive {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} ulong bypass_reason Reason the physical disk drive at this location has been bypassed char[4] new_rev Latest known firmware level of physical disk drive ushort bypassb Mask showing bypass state for each slot in a shelf ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 5 EIP05 - Storage System Management Interface Entity State Change The state of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {event_type (Entity and Event type)} ushort scmi_object_type Entity type ushort scmi_object_event_type Event Information Packet type {} {value (New entity state)} ulong ul1 Additional information longword 1 ulong ul2 Additional information longword 2 {} scmi_obj_hnd handle Storage System Management Interface Handle of affected entity ulong secondary_id Alternate entity identification {attribute (Entity attributes)} ulong type Datatype used union value SCMI Attribute Union ushort[12] u16 As 16 bit words, or value SCMI Attribute Union ulong[6] u32 As 32 bit words, or value SCMI Attribute Union double_word[3] u64 As 64 bit words, or value SCMI Attribute Union {obj (As typed Storage System Management Interface object handle,)} ulong value scmi_obj_hnd handle {} or value SCMI Attribute Union char[24] str As character string endunion value SCMI Attribute Union {} scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface Handle) ulong[6] add_data Additional Data {} Event Information Packet Type: 7 EIP07 - Fibre Channel Services Fibre Channel Port Link Error Excessive link errors were detected on a Fibre Channel port. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port ushort reserved Reserved ushort port HSV200 controller internal Fibre Channel port number ulong loss_of_signal Number of times a loss of signal was detected ulong bad_rx_char Bad received character count ulong loss_of_sync Loss of synchronization count ulong link_fail Link failure count ulong rx_eofa The number of frames that have been received with an EOFa delimiter ulong dis_frm The number of frames that have been received and then discarded ulong bad_crc The number of frames that have been received with a Bad_CRC and a valid EOF ulong proto_err The number of N_Port protocol errors detected ulong exp_frm The number of outbound frames that have expired and therefore were discarded. {} Event Information Packet Type: 8 EIP08 - Fibre Channel Services Fibre Channel Port Link Failure A Fibre Channel port link has failed or a Drive Enclosure Environmental Monitoring Unit task has failed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port char[8] other_cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port {peb[0] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[1] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[2] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[3] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[4] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[5] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[6] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} {peb[7] (Fibre Channel port Event Blocks)} ulong type Error type code ulong context Error context {} ushort peq_prod_index Producer index ushort peq_frz_prod_index Error idle or freeze producer index ushort failure_cause Code indicating path to link failure ushort peq_cons_index Consumer index utiny reserved1 Reserved utiny time Used to represent a retry time or other time based element in the event. utiny other_port HSV200 controller internal Fibre Channel port number utiny port HSV200 controller internal Fibre Channel port number {recovery (Loop Recovery Operations)} ulong progress EWE Step for recovery process ulong shelf Physical Shelf being evaluated. ulong slot Physical Slot being evaluated. ulong cab Cabinet rack being evaluated. {} {} Event Information Packet Type: 9 EIP09 - Fibre Channel Services Physical Disk Drive/Mirror Port Error An error was encountered while attempting to access a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag device UUID of physical disk drive associated with the event char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port ushort exch_type Frame exchange type ushort port HSV200 controller internal Fibre Channel port number attached to the physical disk drive or mirror port ulong al_pa AL_PA of the physical disk drive or mirror port ushort dencl_num Enclosure where the physical disk drive is located ushort reserved Reserved ushort rack_num Rack where physical disk drive is located ushort bay Enclosure bay where the physical disk drive is located ulong fed_class Fibre Channel Exchange Descriptor class union cmd Command Descriptor Block issued utiny[16] bytes CDB as bytes or cmd Command Descriptor Block issued ulong[4] lw CDB as longwords or cmd Command Descriptor Block issued {cdb6 (6 Byte CDB by field)} utiny opcode Offset 0 -- Operation Code tbits:5 lba0 Offset 1, Bits 0-4 -- Logical Block Address[0] tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused) utiny lba1 Offset 2 -- Logical Block Address[1] utiny lba2 Offset 3 -- Logical Block Address[2] utiny length Offset 4 -- Length utiny control Offset 5 -- Control ushort padding Offsets 6-7 -- Pad to longword align {} do_not_display[8] union_pad Union Element Padding (DO NOT DISPLAY!) or cmd Command Descriptor Block issued {cdb10 (10 Byte CDB by field)} utiny opcode Offset 0 -- Operation Code tbits:5 reserved Offset 1, Bits 0-4 -- Reserved tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused) utiny lba0 Offset 2 -- Logical Block Address[0] utiny lba1 Offset 3 -- Logical Block Address[1] utiny lba2 Offset 4 -- Logical Block Address[2] utiny lba3 Offset 5 -- Logical Block Address[3] utiny reserved6 Offset 6 -- Reserved utiny length0 Offset 7 -- Length[0] utiny length1 Offset 8 -- Length[1] utiny control Offset 9 -- Control ushort padding Offsets 10-11 -- Pad to longword align {} do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or cmd Command Descriptor Block issued {cdb12 (12 Byte CDB by field)} utiny opcode Offset 0 -- Operation Code tbits:5 reserved Offset 1, Bits 0-4 -- Reserved tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused) utiny lba0 Offset 2 -- Logical Block Address[0] utiny lba1 Offset 3 -- Logical Block Address[1] utiny lba2 Offset 4 -- Logical Block Address[2] utiny lba3 Offset 5 -- Logical Block Address[3] utiny length0 Offset 6 -- Length[0] utiny length1 Offset 7 -- Length[1] utiny length2 Offset 8 -- Length[2] utiny length3 Offset 9 -- Length[3] utiny reserved10 Offset 10 -- Reserved utiny control Offset 11 -- Control {} do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or cmd Command Descriptor Block issued {cdb16 (16 Byte CDB by field)} utiny opcode Offset 0 -- Operation Code utiny parameter Offset 1 -- Command specific parameters utiny lba0 Offset 2 -- Logical Block Address[0] utiny lba1 Offset 3 -- Logical Block Address[1] utiny lba2 Offset 4 -- Logical Block Address[2] utiny lba3 Offset 5 -- Logical Block Address[3] utiny lba4 Offset 6 -- Logical Block Address[4] or Operation Length[0] utiny lba5 Offset 7 -- Logical Block Address[5] or Operation Length[1] utiny lba6 Offset 8 -- Logical Block Address[6] or Operation Length[2] utiny lba7 Offset 9 -- Logical Block Address[7] or Operation Length[3] utiny length0 Offset 10 -- Length[0] utiny length1 Offset 11 -- Length[1] utiny length2 Offset 12 -- Length[2] utiny length3 Offset 13 -- Length[3] utiny reserved Offsets 14 -- Reserved utiny control Offset 15 -- Control {} endunion cmd Command Descriptor Block issued union error Sense data reported by the physical disk drive utiny[20] bytes Sense data as bytes or error Sense data reported by the physical disk drive ulong[5] lw Sense data as longwords or error Sense data reported by the physical disk drive {sense_data (Sense data by field)} tbits:7 error_code Offset 0, Bits 0-6 -- Error Code tbits:1 valid Offset 0, Bit 7 -- Valid utiny segment Offset 1 -- Segment tbits:4 sense_key Offset 2, Bits 0-3 -- Sense Key tbits:1 reserved_1 Offset 2, Bit 4 -- Reserved tbits:1 ili Offset 2, Bit 5 -- Incorrect Length Indicator tbits:1 eom Offset 2, Bit 6 -- End of Medium tbits:1 filemark Offset 2, Bit 7 -- Filemark utiny info_0 Offset 3 -- Information[0] utiny info_1 Offset 4 -- Information[1] utiny info_2 Offset 5 -- Information[2] utiny info_3 Offset 6 -- Information[3] utiny add_length Offset 7 -- Additional Sense Length utiny[4] cmd_specific Offsets 8-11 -- Command Specific Information union asc_ascq ASC/ASCQ Union {asc_ascqb (Offsets 12-13 -- Additional Sense Code (ASC)/Additional Sense Code Qualifier (ASCQ))} utiny asc Offset 12 -- ASC utiny asq Offset 13 -- ASCQ {} or asc_ascq ASC/ASCQ Union ushort asc_ascqw Offsets 12-13 -- Combined ASC/ASCQ endunion asc_ascq ASC/ASCQ Union utiny fru_code Offset 14 -- Field Replaceable Unit Code tbits:7 sks_0 Offset 15, Bits 0-6 -- Sense Key Specific[0] tbits:1 sksv Offset 15, Bit 7 -- Sense Key Specific Valid utiny[2] sks Offsets 16-17 -- Sense Key Specific[1-2] ushort padding Offsets 18-19 -- Pad to longword align {} endunion error Sense data reported by the physical disk drive {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} ushort bypassb Mask showing bypass state for each slot in a shelf ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: a EIP0A - Storage System State Services State Change A Storage System state change occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {node_name (World Wide Name of HSV200 controller)} ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} tag scell_tag UUID of Storage System ulong dimm_size Size of this HSV200 controller's DIMM in megabytes ulong debug_flags DebugFlags of HSV200 controller ulong print_flags PrintFlags of HSV200 controller {} Event Information Packet Type: b EIP0B - Storage System State Services Physical Disk Drive State Change A physical disk drive state change occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} uuid device UUID of physical disk drive char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive ushort reason_code Code identifying cause of the physical disk drive being marked inoperative or why event is being reported ushort port HSV200 controller internal Fibre Channel port number attached to the physical disk drive or mirror port ushort dencl_num Enclosure where the physical disk drive is located {rss_flags (Redundant Storage Set member state flags)} tbits:1 member_migrating Migrating tbits:1 member_missing Missing or never existed tbits:1 member_abnormal Abnormal tbits:5 reserved Reserved for future use {} {flags (Information validity flags)} tbits:1 inq_state SCSI INQUIRY data is valid tbits:1 quorum_disk Is Storage System quorum disk tbits:6 reserved Reserved for future use {} ushort rack_num Rack where the physical disk drive is located ushort bay Enclosure bay where the physical disk drive is located {inq_data (Last SCSI INQUIRY data read during discovery (Note: The inquiry data is truncated after the Version Descriptor 1 field.))} tbits:5 per_dev_typ Peripheral Device-type tbits:3 per_qual Peripheral Qualifier tbits:7 reserved_1 Reserved tbits:1 rmb Removable Medium bit tbits:8 version Version tbits:4 response_data Response data format ( 1 = SCSI-1, 2 = SCSI-2, 3 = SCSI-3) tbits:1 hisup Hierarchical Support bit tbits:1 normaca Normal ACA bit tbits:1 obsolete Obsolete tbits:1 aerc Asynchronous Event Reporting Capability bit utiny add_length Additional Length tbits:7 reserved_3 Reserved tbits:1 sccs SCC Supported bit tbits:1 addr16 Address 16 bit tbits:2 obsolete_1 Reserved tbits:1 mchngr Medium Changer bit tbits:1 multip Multiport bit tbits:1 vs_1 Vendor Specific tbits:1 encserv Enclosure Services bit tbits:1 bque Basic Queuing bit tbits:1 vs Vendor Specific tbits:1 cmdque Command Queuing bit tbits:1 reserved_2 Reserved tbits:1 linked Linked Command bit tbits:1 sync Synchronous Transfer bit tbits:1 wbus16 Wide Bus 16 bit tbits:1 wbus32 Wide Bus 32 bit tbits:1 reladr Relative Addressing bit char[8] vendor_id Vendor Identification char[16] product_id Product Identification char[4] product_rev Product Revision Level ulong[5] vendor_36_55 Vendor-specific ushort reserved_56_57 Reserved ushort vd1 Version Descriptor 1 {} ulong quorum_sequence Quorum Space Write Sequence (i.e., quorum disk 1, 2, or 3) ulong capacity LUN capacity (blocks) ulong member_state Redundant Storage Set member state uuid second_device UUID of other physical disk drive ulong second_fnb_ptr Address of fnb for other physical disk drive ushort volnoid Volume of other physical disk drive ushort poid NOID of other physical disk drive {} Event Information Packet Type: c EIP0C - Data Replication Manager State Change A Data Replication Manager state change occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag group_name_uuid Group Name UUID tag peer_scell_uuid Peer Storage System UUID tag group_uuid Data Replication Group UUID tag source_scvd_uuid Source Storage System Virtual Disk UUID tag dest_scvd_uuid If eip0c.flags.remote_adapter_wwn is set equal to 1, this field contains the WWN of the remote adapter. Otherwise, this field contains the Destination Storage System Virtual Disk UUID. ushort blocks Number of blocks in error ushort status Error status value ulong vda Virtual Disk Address in error char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port utiny reserved Reserved for future use {flags (Field use flags)} tbits:7 reserved Reserved for future use tbits:1 remote_adapter_wwn dest_scvd_uuid contains remote adapter WWN {} utiny side Remote HSV200 controller used by Data Replication Manager tunnel: 0 => A; 1 => B utiny port HSV200 controller internal Fibre Channel port number ulong[2] reserved1 Reserved for future use {} Event Information Packet Type: d EIP0D - Executive Services System Time Change A change in system time occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} utiny[3] unused Unused utiny action Action code ulong[2] reserved Reserved scmitim ctime Current time value scmitim ptime Previous time value {} Event Information Packet Type: e EIP0E - Storage System Management Interface Entity Creation or Deletion A Storage System Management Interface entity was created or deleted. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {event_type (Entity and Event type)} ushort scmi_object_type Entity type ushort scmi_object_event_type Event Information Packet type {} scmi_obj_hnd handle Storage System Management Interface Handle of affected entity scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface Handle) {attribute (Entity attributes)} ulong type Datatype used union value SCMI Attribute Union ushort[12] u16 As 16 bit words, or value SCMI Attribute Union ulong[6] u32 As 32 bit words, or value SCMI Attribute Union double_word[3] u64 As 64 bit words, or value SCMI Attribute Union {obj (As typed Storage System Management Interface object handle,)} ulong value scmi_obj_hnd handle {} or value SCMI Attribute Union char[24] str As character string endunion value SCMI Attribute Union {} scmi_obj_hnd add_handle2 Additional SCMI object handle (2) ulong[4] add_data Additional Data {} Event Information Packet Type: f EIP0F - Storage System Management Interface Entity Attribute Change An attribute of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {event_type (Entity and Event type)} ushort scmi_object_type Entity type ushort scmi_object_event_type Event Information Packet type {} union secondary_id Secondary identification ulong Id Alternate entity identification or secondary_id Secondary identification {rss_data (Redundant Storage Set information)} ushort Id Redundant Storage Set identification ushort Index Redundant Storage Set index {} endunion secondary_id Secondary identification {old_attr (Old attribute information)} ulong type Datatype used union value SCMI Attribute Union ushort[12] u16 As 16 bit words, or value SCMI Attribute Union ulong[6] u32 As 32 bit words, or value SCMI Attribute Union double_word[3] u64 As 64 bit words, or value SCMI Attribute Union {obj (As typed Storage System Management Interface object handle,)} ulong value scmi_obj_hnd handle {} or value SCMI Attribute Union char[24] str As character string endunion value SCMI Attribute Union {} {new_attr (New attribute information)} ulong type Datatype used union value SCMI Attribute Union ushort[12] u16 As 16 bit words, or value SCMI Attribute Union ulong[6] u32 As 32 bit words, or value SCMI Attribute Union double_word[3] u64 As 64 bit words, or value SCMI Attribute Union {obj (As typed Storage System Management Interface object handle,)} ulong value scmi_obj_hnd handle {} or value SCMI Attribute Union char[24] str As character string endunion value SCMI Attribute Union {} scmi_obj_hnd handle Storage System Management Interface Handle of affected entity scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface ulong reserved reserved for future use {} Event Information Packet Type: 10 EIP10 - System Services HSV200 Controller State Change A controller state change occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {node_name (World Wide Name of HSV200 controller)} ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} {information (State change information)} ulong pc Program counter ulong flags Flags ulong code Code {} {} Event Information Packet Type: 11 EIP11 - Disk Enclosure Environmental Monitoring Unit Services Status Change. Status of a disk enclosure element has changed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {event_type (Entity and Event type)} ushort scmi_object_type Entity type ushort scmi_object_event_type Event Information Packet type {} scmi_obj_hnd handle Storage System Management Interface Handle of affected disk enclosure ulong rack_num Rack number ulong dencl_num Disk enclosure number union alarm_error_code Alarm code ulong value As longword or alarm_error_code Alarm code {field (By field)} utiny reserved Reserved for future use utiny ec Error code utiny en Element number utiny et Element type code {} endunion alarm_error_code Alarm code utiny[3] rsvd1 Reserved for future use utiny loop Loop number {enclosures[1] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[0] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[3] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[2] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[5] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[4] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[7] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[6] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[9] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[8] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} ulong[12] rsvd Reserved for future use {} Event Information Packet Type: 12 EIP12 - Fibre Channel Services Physical Disk Drive/Mirror Port Unexpected Work Encountered Unexpected work was received from a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag device UUID of the physical disk drive or HSV200 controller associated with the event char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port ulong al_pa AL_PA of the physical disk drive or the mirror port ushort dencl_num Enclosure where the physical disk drive is located ushort port HSV200 controller internal Fibre Channel port number attached to the physical disk drive or mirror port ushort rack_num Rack where the physical disk drive is located ushort bay Enclosure bay where the physical disk drive is located ulong[14] hdr_cdb Command Descriptor Block issued and Fibre Channel Header ushort bypassb Mask showing bypass state for each slot in a shelf ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 13 EIP13 - Fibre Channel Services Physical Disk Drive/Mirror Port/Drive Enclosure Environmental Monitoring Unit Error summary. Summary of errors encountered while attempting to access a physical disk drive, the mirror port, or a Drive Enclosure Environmental Monitoring Unit. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag device UUID of the physical disk drive, HSV200 controller, or Drive Enclosure Environmental Monitoring Unit associated with the event char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port ulong al_pa AL_PA of the physical disk drive or the mirror port ushort dencl_num Enclosure where the physical disk drive is located ushort port HSV200 controller internal Fibre Channel port number attached to the physical disk drive or mirror port ushort rack_num Rack where the physical disk drive is located ushort bay Enclosure bay where the physical disk drive is located ulong fed_class Fibre Channel Exchange Descriptor class ulong num_times Number of occurrences of the error. {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} {enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} utiny rack_num Rack were enclosure is located utiny dencl_num Enclosure number {} char[8] missing_cerp_id HSV200 controller enclosure rear panel Fibre Channel port that cannot connect to physical disk drive or mirror port ushort bypassa Mask showing bypass state for each slot in a shelf ushort missing_port HSV200 controller internal Fibre Channel port number that cannont connect to the physical disk drive or mirror port ushort switch_type Used to represent the type of switch detected (SES or non-SES compliant) ushort bypassb Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 14 EIP14 - Diagnostic Operations Generator Detected Failure. A failure was detected during the execution of a diagnostic. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {eep_error (Diagnostic error EEPROM data)} utiny padding Pad to longword align this structure utiny count Duplicate error count utiny test_num Test number utiny TE_num TE number ulong Z_code Z's code ulong error_code Error code ulong address Address of Error ulong expected Expected Data ulong actual Actual Data ulonglong uptime Uptime of error {} ulong dimm_size Size of this HSV200 controller's DIMM in megabytes {} Event Information Packet Type: 15 EIP15 - Container Services Management Operation has started or completed. An operation on a Disk Group has started or completed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag tag1 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event tag tag2 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event ulong state Event-specific state value ulong status Event-specific operation status {} Event Information Packet Type: 16 EIP16 - Data Replication Manager Time Report. An Data Replication Manager time synchronization event has occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} uuid sender Enterprise Virtual Array controller initiating time report message uuid receiver Peer controller receiving time report message uuid receiver_partner Other controller in sending or receiving Storage System scmitim sent_time Time message was sent scmitim received_time Time message was received {} Event Information Packet Type: 17 EIP17 - Fibre Channel Services Fibre Channel Port Loop Config A new device map has been generated on a Fibre Channel port. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} char[8] cerp_id HSV200 controller enclosure rear panel Fibre Channel port ulong map_id Multi-page map identifier (all pages containing this identifier comprise this map) utiny entries Number of map entries (AL_PAs) in this map utiny total_pages Total pages containing portions of this map utiny page Page number of this loop map event utiny port HSV200 controller internal Fibre Channel port number utiny[92] loop_map Loop configuration information {} Event Information Packet Type: 18 EIP18 - Storage System State Services Redundant Storage Set State Change A Redundant Storage Set state change occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag ldad_tag Tag of the Disk Group associated with the event ushort target_rss Migration target ushort source_rss Migration source ushort target_migr Migration flags for target ushort source_migr Migration flags for source utiny[16] smembers Volumes in source utiny[16] tmembers Volumes in target {} Event Information Packet Type: 19 EIP19 - System Data Center Services Status Change Status of a System Data Center element has changed. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {event_type (Entity and Event type)} ushort scmi_object_type Entity type ushort scmi_object_event_type Event Information Packet type {} scmi_obj_hnd handle Storage System Management Interface {state (State of SDC monitored component)} ulong old Previous State ulong cur Current State {} {status_code (Status code of SDC monitored component)} ulong old Previous Status Code ulong cur Current Status Code {} {status_data (Status data of SDC monitored component)} ulong old Previous Additional Status Data ulong cur Current Additional Status Data {} ulong[4] comp_states States of SDC monitored components ulong[4] comp_status_codes Status codes of SDC monitored components ulong[4] comp_status_data Status data of SDC monitored components {} Event Information Packet Type: 1a EIP1A - System Services Code Load Operation Update A code load operation has occurred. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} char[40] state State information char[36] hardware Hardware information char[32] versions Version information {} Event Information Packet Type: 1b EIP1B - Host Port Event A Host Port Event Occurred {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag ld_tag Virtual Disk UUID tag scvd_tag Associated Storage System Virtual Disk UUID {} Event Information Packet Type: 1c EIP1C - Fault Manager Termination Event HSV200 controller operation terminated event report. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {lteihd (Last Termination Event Information Header)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort size Structure size {} {lter (Last Termination Event Report Block)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {params (Termination Parameters)} ulong[31] param Termination Parameters {} {} utiny[2] reserved Reserved {flags (Other Last Termination Event flags)} tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} {} Event Information Packet Type: 1d EIP1D - Fault Manager Termination Event (old Termination Event Information Header) HSV200 controller operation terminated event report. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {lteihd (Last Termination Event Information Header)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved {} utiny revision Structure revision number ushort size Structure size {} {lter (Nonstandard Last Termination Event Report Block)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {} utiny[2] reserved Reserved utiny lg_send_sts Last Gasp send status utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} {} Event Information Packet Type: 1e EIP1E - General Storage System State Services State Information Event General Storage System state information to be reported. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} char[12] info Informational String ulong[24] data Informational Data {} Event Information Packet Type: 1f EIP1F - A Storage System Virtual Disk has changed controller mastership. {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag ld_tag Logical disk tag du_tag Derived unit tag scvd_tag Storage System Virtual Disk {prev_wwn (Previous Controller)} ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} {current_wwn (Current Controller)} ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} {} Event Information Packet Type: 20 EIP20 - Storage System State Services Controller FC Port event {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} {node_name (World Wide Name of HSV200 controller)} ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} ulong port Loop port number ulong data Event-specific data {} Event Information Packet Type: 21 EIP21 - General purpose SCS Logical Disk synchronization event {Event Log Packet Event Specific Information} {flags (Flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort count Event specific information size in bytes ulong sequence_number Sequence number assigned to the event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV200 controller that reported the event scmitim report_time Time event was reported ulong report_location Location of event report call {header (Header Information)} union u Event Code Union {ec (Event Code)} utiny eiptype Event Information Packet Type Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Event Code Union ulong value Event Code Value endunion u Event Code Union utiny revision Packet revision number utiny type Packet type ushort count Number of bytes in packet {} tag target_tag Target Tag tag parent_tag Parent Tag ulong operation Operation ulong status Status ulong prev_state Previous State ulong new_state New State ulong redundancy Redundancy Type double_word size LD Size tag aux_tag Auxillary Tag {} TERMINATION EVENT BLOCK: {Termination Event Block} union u Last Termination Event Block Union {data (Termination Event Block Data)} {ltei (Last Termination Event Information)} {lteihd (Last Termination Event Information Header)} {flags (Last Termination Event flags)} tbits:1 time_set Time has been set on this HSV200 controller tbits:1 time_synched Time has been synchronized with all HSV200 controllers in the Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV200 controller (Note: Not valid until Storage System primary HSV200 controller is elected) tbits:1 spsctrlr Single power supply HSV200 controller {} utiny revision Structure revision number ushort size Structure size {} {lter (Last Termination Event Report Block)} ulong seq Sequence number assigned to the termination event char[4] sw_version HSV200 controller software version number string char[12] baselevel_id HSV200 controller baselevel build string char[8] ctrlr_model_id HSV200 controller model string scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV200 controller that terminated operation scmitim termination_time Time termination event occurred {termination_event (Termination event information)} ulong termination_location Location of termination event report call union u Termination Code Union {code (Termination Code)} tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code cacode cac Corrective Action Code utiny evnum Event Number utiny scid HSV200 Controller Software Component Identification {} or u Termination Code Union ulong value Termination Code Value endunion u Termination Code Union {params (Termination Parameters)} ulong[31] param Termination Parameters {} {} utiny[2] reserved Reserved {flags (Other Last Termination Event flags)} tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index ulonglong uptime Number of seconds HSV200 controller has run functional code {} {sa (Exception save area)} ulong[32] registers R0-R31 ulong srr0 SRR0 ulong srr1 SRR1 ulong cr CR ulong xer XER ulong ctr CTR ulong lr LR ulong exception Exception Code union optional Machine check or DSI exception values {mcp (Machine check values)} ulong mc_count Exception Count ulong msssr0 MSSSR0 Register {} or optional Machine check or DSI exception values {dsi (DSI exception values)} ulong dsisr DSISR Register ulong dar DAR Register {} endunion optional Machine check or DSI exception values {} char[8] current_process Current process name {stack (Stack information)} ulong stack_depth Total calls made {stack[0] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[1] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[2] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[3] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[4] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[5] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[6] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[7] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[8] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[9] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[10] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[11] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[12] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[13] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[14] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[15] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[16] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[17] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[18] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[19] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[20] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[21] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[22] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[23] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[24] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[25] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[26] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[27] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[28] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[29] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[30] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} {stack[31] (Stack entries)} ulong bc Back chain (old stack pointer) ulong slr Saved link register {} *ptr *bad_stack_ptr Bad stack address ulong system_stack_guard System stack guard intact flags (set to 1 if not intact) ulong[16] stack_guard Process stack guard intact flags (set to 1 if not intact) {} {hardware (Hardware registers)} {flags (Hardware registers gathered flags)} lbits:1 uartdrd SC28L194 Quad UART d data registers gathered lbits:1 uartdrc SC28L194 Quad UART c data registers gathered lbits:1 uartdrb SC28L194 Quad UART b data registers gathered lbits:1 uartdra SC28L194 Quad UART a data registers gathered lbits:1 uartcrd SC28L194 Quad UART d control registers gathered lbits:1 uartcrc SC28L194 Quad UART c control registers gathered lbits:1 uartcrb SC28L194 Quad UART b control registers gathered lbits:1 uartcra SC28L194 Quad UART a control registers gathered lbits:1 sprite_csr Sprite Chip CSR registers gathered lbits:1 glue_csr Glue Chip CSR registers gathered lbits:1 toyclock DS1557 4MEG NV Y2KC Timekeeping RAM registers gathered lbits:1 decoder_csr Decoder lbits:1 atlantis_csr Atlantis (Crash Dump only) lbits:1 atlantis_mcs Atlantis machine check specific registers (Termination event only) lbits:1 atlantis_a1 Atlantis Area 1 miscellaneous registers (Termination event only) lbits:1 aa2 Atlantis registers--Area 2 (Termination event only) lbits:1 aa3 Atlantis registers--Area 3 (Termination event only) lbits:15 rsvd Reserved {} {tach_flags (Tachyon registers gathered flags)} lbits:1 tachyon9_csr Tachyon 9 CSR registers gathered lbits:1 tachyon9_pcicfg Tachyon 9 PCI Configuration lbits:1 tachyon9_gbic Tachyon 9 GBIC Small Form Factor ID lbits:1 tachyon8_csr Tachyon 8 CSR registers gathered lbits:1 tachyon8_pcicfg Tachyon 8 PCI Configuration lbits:1 tachyon8_gbic Tachyon 8 GBIC Small Form Factor ID lbits:1 tachyon7_csr Tachyon 7 CSR registers gathered lbits:1 tachyon7_pcicfg Tachyon 7 PCI Configuration lbits:1 tachyon7_gbic Tachyon 7 GBIC Small Form Factor ID lbits:1 tachyon6_csr Tachyon 6 CSR registers gathered lbits:1 tachyon6_pcicfg Tachyon 6 PCI Configuration lbits:1 tachyon6_gbic Tachyon 6 GBIC Small Form Factor ID lbits:1 tachyon3_csr Tachyon 3 CSR registers gathered lbits:1 tachyon3_pcicfg Tachyon 3 PCI Configuration lbits:1 tachyon3_gbic Tachyon 3 GBIC Small Form Factor ID lbits:1 tachyon2_csr Tachyon 2 CSR registers gathered lbits:1 tachyon2_pcicfg Tachyon 2 PCI Configuration lbits:1 tachyon2_gbic Tachyon 2 GBIC Small Form Factor ID lbits:14 rsvd Reserved {} {tach_ncfg_flags (Tachyon non-configuration registers gathered flags)} lbits:1 tachyon9_ncfghi Tachyon 9 Non-configuration--high registers gathered lbits:1 tachyon9_ncfglo Tachyon 9 Non-configuration--low registers gathered lbits:1 tachyon8_ncfghi Tachyon 8 Non-configuration--high registers gathered lbits:1 tachyon8_ncfglo Tachyon 8 Non-configuration--low registers gathered lbits:1 tachyon7_ncfghi Tachyon 7 Non-configuration--high registers gathered lbits:1 tachyon7_ncfglo Tachyon 7 Non-configuration--low registers gathered lbits:1 tachyon6_ncfghi Tachyon 6 Non-configuration--high registers gathered lbits:1 tachyon6_ncfglo Tachyon 6 Non-configuration--low registers gathered lbits:1 tachyon3_ncfghi Tachyon 3 Non-configuration--high registers gathered lbits:1 tachyon3_ncfglo Tachyon 3 Non-configuration--low registers gathered lbits:1 tachyon2_ncfghi Tachyon 2 Non-configuration--high registers gathered lbits:1 tachyon2_ncfglo Tachyon 2 Non-configuration--low registers gathered lbits:20 rsvd Reserved {} {aa3 (Atlantis registers--Area3)} ulong[518] reserved Reserved for future use {} {aa2 (Atlantis registers--Area2)} ulong[200] reserved Reserved for future use {} {atlantis_a1 (Atlantis Area 1 miscellaneous registers)} union cpu_configuration (Offset 0x0000) CPU Configuration {field (By field)} lbits:8 nomatchcnt RW CPU Address Miss Counter lbits:1 nomatchcnten RW CPU Address Miss Counter Enable lbits:1 nomatchcntext RW CPU address miss counter MSB lbits:1 reserved4 RES Reserved lbits:1 singlecpu RW 0 = Dual CPU. 1 = Single CPU lbits:1 endianess RW CPU Bus Byte Orientation. Must be 0 lbits:1 pipeline RW Pipeline Enable lbits:3 reserved3 RES Reserved lbits:1 stopretry RW Stop to retry transactions from PCI lbits:1 multigtdec RW Multi-GT Address Decode lbits:1 dpvalid RW CPU DP[0-7] Connection lbits:2 reserved2 RES Reserved lbits:1 perrprop RW Parity Error Propagation lbits:2 reserved1 RES Reserved lbits:1 aackdelay2 RW AACK# earliest assertion following TS# lbits:1 apvalid RW CPU AP[0-3] Connection lbits:1 remapwrdis RW Address Remap Registers Write Control lbits:4 reserved0 RES Reserved {} or cpu_configuration (Offset 0x0000) CPU Configuration ulong value As longword endunion cpu_configuration (Offset 0x0000) CPU Configuration union cs_0_base_address (Offset 0x0008) CS[0]# Base Address {field (By field)} lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_0_base_address (Offset 0x0008) CS[0]# Base Address ulong value As longword endunion cs_0_base_address (Offset 0x0008) CS[0]# Base Address union cs_0_size (Offset 0x0010) CS[0]# Size {field (By field)} lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_0_size (Offset 0x0010) CS[0]# Size ulong value As longword endunion cs_0_size (Offset 0x0010) CS[0]# Size union cs_2_base_address (Offset 0x0018) CS[2]# Base Address {field (By field)} lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_2_base_address (Offset 0x0018) CS[2]# Base Address ulong value As longword endunion cs_2_base_address (Offset 0x0018) CS[2]# Base Address union cs_2_size (Offset 0x0020) CS[2]# Size {field (By field)} lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_2_size (Offset 0x0020) CS[2]# Size ulong value As longword endunion cs_2_size (Offset 0x0020) CS[2]# Size union cs_1_base_address (Offset 0x0208) CS[1]# Base Address {field (By field)} lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_1_base_address (Offset 0x0208) CS[1]# Base Address ulong value As longword endunion cs_1_base_address (Offset 0x0208) CS[1]# Base Address union cs_1_size (Offset 0x0210) CS[1]# Size {field (By field)} lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_1_size (Offset 0x0210) CS[1]# Size ulong value As longword endunion cs_1_size (Offset 0x0210) CS[1]# Size union cs_3_base_address (Offset 0x0218) CS[3]# Base Address {field (By field)} lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_3_base_address (Offset 0x0218) CS[3]# Base Address ulong value As longword endunion cs_3_base_address (Offset 0x0218) CS[3]# Base Address union cs_3_size (Offset 0x0220) CS[3]# Size {field (By field)} lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_3_size (Offset 0x0220) CS[3]# Size ulong value As longword endunion cs_3_size (Offset 0x0220) CS[3]# Size union base_address_enable (Offset 0x0278) Base Address Enable {field (By field)} lbits:1 encs_0 RW CS[0] base address enable lbits:1 encs_1 RW CS[1] base address enable lbits:1 encs_2 RW CS[2] base address enable lbits:1 encs_3 RW CS[3] base address enable lbits:1 endevcs_0 RW DevCS[0] base address enable lbits:1 endevcs_1 RW DevCS[1] base address enable lbits:1 endevcs_2 RW DevCS[2] base address enable lbits:1 endevcs_3 RW DevCS[3] base address enable lbits:1 enbootcs RW BootCS base address enable lbits:1 enpci_0_io RW PCI_0 I/O base address enable lbits:1 enpci_0_mem0 RW PCI_0 Mem0 base address enable lbits:1 enpci_0_mem1 RW PCI_0 Mem1 base address enable lbits:1 enpci_0_mem2 RW PCI_0 Mem2 base address enable lbits:1 enpci_0_mem3 RW PCI_0 Mem3 base address enable lbits:1 enpci_1_io RW PCI_1 I/O base address enable lbits:1 enpci_1_mem0 RW PCI_1 Mem0 base address enable lbits:1 enpci_1_mem1 RW PCI_1 Mem1 base address enable lbits:1 enpci_1_mem2 RW PCI_1 Mem2 base address enable lbits:1 enpci_1_mem3 RW PCI_1 Mem3 base address enable lbits:1 enintegr_sram RW Integrated SRAM base address enable lbits:1 eninter_space RW Internal Space base address enable lbits:11 reserved0 RES Reserved {} or base_address_enable (Offset 0x0278) Base Address Enable ulong value As longword endunion base_address_enable (Offset 0x0278) Base Address Enable union idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count {field (By field)} lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count ulong value As longword endunion idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count union idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count {field (By field)} lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count ulong value As longword endunion idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count union idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count {field (By field)} lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count ulong value As longword endunion idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count union idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count {field (By field)} lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count ulong value As longword endunion idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count union idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address {field (By field)} lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address ulong value As longword endunion idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address union idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address {field (By field)} lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address ulong value As longword endunion idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address union idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address {field (By field)} lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address ulong value As longword endunion idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address union idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address {field (By field)} lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address ulong value As longword endunion idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address union idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address {field (By field)} lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address ulong value As longword endunion idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address union idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address {field (By field)} lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address ulong value As longword endunion idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address union idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address {field (By field)} lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address ulong value As longword endunion idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address union idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address {field (By field)} lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address ulong value As longword endunion idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address union idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer {field (By field)} lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer ulong value As longword endunion idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer union idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer {field (By field)} lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer ulong value As longword endunion idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer union idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer {field (By field)} lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer ulong value As longword endunion idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer union idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer {field (By field)} lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer ulong value As longword endunion idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer union idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) {field (By field)} lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) ulong value As longword endunion idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) union idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) {field (By field)} lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) ulong value As longword endunion idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) union idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) {field (By field)} lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) ulong value As longword endunion idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) union idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) {field (By field)} lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) ulong value As longword endunion idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) union idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control {field (By field)} lbits:2 arb0 RW Slice 0 of 'pizza arbiter' lbits:2 arb1 RW Slice 1 of 'pizza arbiter' lbits:2 arb2 RW Slice 2 of 'pizza arbiter' lbits:2 arb3 RW Slice 3 of 'pizza arbiter' lbits:2 arb4 RW Slice 4 of 'pizza arbiter' lbits:2 arb5 RW Slice 5 of 'pizza arbiter' lbits:2 arb6 RW Slice 6 of 'pizza arbiter' lbits:2 arb7 RW Slice 7 of 'pizza arbiter' lbits:2 arb8 RW Slice 8 of 'pizza arbiter' lbits:2 arb9 RW Slice 9 of 'pizza arbiter' lbits:2 arb10 RW Slice 10 of 'pizza arbiter' lbits:2 arb11 RW Slice 11 of 'pizza arbiter' lbits:2 arb12 RW Slice 12 of 'pizza arbiter' lbits:2 arb13 RW Slice 13 of 'pizza arbiter' lbits:2 arb14 RW Slice 14 of 'pizza arbiter' lbits:2 arb15 RW Slice 15 of 'pizza arbiter' {} or idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control ulong value As longword endunion idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control union idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 ulong value As longword endunion idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 union idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 ulong value As longword endunion idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 union idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 ulong value As longword endunion idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 union idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 ulong value As longword endunion idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 union idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 ulong value As longword endunion idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 union idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 ulong value As longword endunion idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 union idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 ulong value As longword endunion idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 union idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 ulong value As longword endunion idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 union idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 ulong value As longword endunion idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 union idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 ulong value As longword endunion idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 union idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 ulong value As longword endunion idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 union idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 ulong value As longword endunion idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 union idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 ulong value As longword endunion idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 union idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 ulong value As longword endunion idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 union idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 {field (By field)} lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved union attr Target specific attributes {dramti (DRAM Target Interface)} tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes {dbti (Device Bus Target Interface)} tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes {pci01ti (PCI0/1 Target Interface)} tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes utiny value As byte endunion attr Target specific attributes lbits:16 base RW Base Address {} or idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 ulong value As longword endunion idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 union idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 {field (By field)} lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 ulong value As longword endunion idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 union idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable {field (By field)} lbits:1 en0 RW Address window 0 enable lbits:1 en1 RW Address window 1 enable lbits:1 en2 RW Address window 2 enable lbits:1 en3 RW Address window 3 enable lbits:1 en4 RW Address window 4 enable lbits:1 en5 RW Address window 5 enable lbits:1 en6 RW Address window 6 enable lbits:1 en7 RW Address window 7 enable lbits:24 reserved0 RO Reserved, read only {} or idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable ulong value As longword endunion idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable union sdram_configuration (Offset 0x1400) SDRAM Configuration {field (By field)} lbits:14 refresh Refresh rate of DIMM lbits:1 pinter Physical interleaving lbits:1 vinter Virtual interleaving lbits:1 reserved1 Reserved lbits:1 regdram Registered DRAM lbits:1 ecc Enable ECC lbits:1 reserved2 Reserved lbits:2 dqs # DQS pins lbits:4 reserved3 Reserved lbits:6 rdbuff Read Buffer assignment {} or sdram_configuration (Offset 0x1400) SDRAM Configuration ulong value As longword endunion sdram_configuration (Offset 0x1400) SDRAM Configuration union dunit_control_low (Offset 0x1404) Dunit Control (Low) {field (By field)} lbits:1 clksync RW Clock Domains Synchronization lbits:1 rdsyncsel RW Read Data Synchronization Select lbits:1 rdctrltdel RW Read Control Logic Delay lbits:1 rddatadel RW Read Data Delay lbits:2 ctrlpipe RW Number of pipeline stages in the Dunit control path lbits:1 ctrlpos RW Address/Control Output Timing lbits:1 rdpipe RW Number of pipeline stages in the read data path lbits:1 rdsyncen RW Read Data Path Synchronization lbits:1 rmwsyncen RW RMW Path Synchronization lbits:1 cpupriority RW CPU priority assignment lbits:1 pci_0priority RW PCI_0 priority assignment lbits:1 pci_1priority RW PCI_1 priority assignment lbits:1 mpscpriority RW MPSC priority assignment lbits:1 idmapriority RW IDMA priority assignment lbits:1 gbpriority RW Gb priority assignment lbits:4 lcnt RW Arbiter Low Priority Counter lbits:4 hcnt RW Arbiter High Priority Counter lbits:3 stburstdel RW Number of sample stages on StartBurstIn lbits:1 stburstneg RW StartBurstIn is first sampled on the falling edge of clock lbits:1 stburstsrc RW StartBurst source lbits:1 rddataneg RW Read data is first sampled with falling edge of clock lbits:2 reserved0 RES Reserved {} or dunit_control_low (Offset 0x1404) Dunit Control (Low) ulong value As longword endunion dunit_control_low (Offset 0x1404) Dunit Control (Low) union atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) {field (By field)} lbits:4 Tdqss Write to DQS lbits:4 Trcd Activate to command lbits:4 Trp Precharge command period lbits:4 Twr Write command to precharge lbits:4 Twtr Write command to read command lbits:4 Tras Minimum row active time lbits:4 Trrd Activate bank A to activate bank B lbits:4 reserved Reserved {} or atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) ulong value As longword endunion atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) union atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) {field (By field)} lbits:4 Trfc Refresh command period lbits:2 Trd2rd Minimum gap between DRAM read accesses lbits:2 Trd2wr Minimum gap between DRAM read and write accesses lbits:24 reserved Write command to precharge {} or atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) ulong value As longword endunion atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) union sdram_address_control (Offset 0x1410) SDRAM Address Control {field (By field)} lbits:4 addrsel RW SDRAM Address Select lbits:2 dcfg RW SDRAM Device Configuration lbits:26 reserved0 RES Reserved {} or sdram_address_control (Offset 0x1410) SDRAM Address Control ulong value As longword endunion sdram_address_control (Offset 0x1410) SDRAM Address Control union sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control {field (By field)} lbits:1 ope0 RW Open Page Enable CS[0]# bank0 lbits:1 ope1 RW Open Page Enable CS[0]# bank1 lbits:1 ope2 RW Open Page Enable CS[0]# bank2 lbits:1 ope3 RW Open Page Enable CS[0]# bank3 lbits:1 ope4 RW Open Page Enable CS[1]# bank0 lbits:1 ope5 RW Open Page Enable CS[1]# bank1 lbits:1 ope6 RW Open Page Enable CS[1]# bank2 lbits:1 ope7 RW Open Page Enable CS[1]# bank3 lbits:1 ope8 RW Open Page Enable CS[2]# bank0 lbits:1 ope9 RW Open Page Enable CS[2]# bank1 lbits:1 ope10 RW Open Page Enable CS[2]# bank2 lbits:1 ope11 RW Open Page Enable CS[2]# bank3 lbits:1 ope12 RW Open Page Enable CS[3]# bank0 lbits:1 ope13 RW Open Page Enable CS[3]# bank1 lbits:1 ope14 RW Open Page Enable CS[3]# bank2 lbits:1 ope15 RW Open Page Enable CS[3]# bank3 lbits:16 reserved0 RES Reserved {} or sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control ulong value As longword endunion sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control union sdram_operation (Offset 0x1418) SDRAM Operation {field (By field)} lbits:3 cmd RW DRAM Mode Select lbits:29 reserved0 RES Reserved {} or sdram_operation (Offset 0x1418) SDRAM Operation ulong value As longword endunion sdram_operation (Offset 0x1418) SDRAM Operation union sdram_mode (Offset 0x141C) SDRAM Mode {field (By field)} lbits:3 bl RW Burst Length lbits:1 bt RW Burst Type/Init Val lbits:3 cl RW CAS Latency lbits:7 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or sdram_mode (Offset 0x141C) SDRAM Mode ulong value As longword endunion sdram_mode (Offset 0x141C) SDRAM Mode union extsdram_mode (Offset 0x1420) Extended SDRAM Mode {field (By field)} lbits:1 dll RW DRAM DLL Enable lbits:1 ds RW DRAM Drive Strength lbits:1 qfc RW QFC Signal Enable lbits:11 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or extsdram_mode (Offset 0x1420) Extended SDRAM Mode ulong value As longword endunion extsdram_mode (Offset 0x1420) Extended SDRAM Mode union dunit_control_high (Offset 0x1424) Dunit Control (High) {field (By field)} lbits:4 wrbuff RW Reserved lbits:4 rdbuff RW Reserved lbits:4 txque RW Reserved lbits:4 wrtrig RW Reserved lbits:4 rdtrig RW Reserved lbits:4 rmwtrig RW Reserved lbits:1 snooppipe RW Snoops pipeline enable lbits:4 snoopdepth RW Reserved lbits:3 reserved0 RES Reserved {} or dunit_control_high (Offset 0x1424) Dunit Control (High) ulong value As longword endunion dunit_control_high (Offset 0x1424) Dunit Control (High) union sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low) {field (By field)} lbits:4 arb0 RW Slice 0 of the device controller 'pizza' arbiter lbits:4 arb1 RW Slice 1 of the device controller 'pizza' arbiter lbits:4 arb2 RW Slice 2 of the device controller 'pizza' arbiter lbits:4 arb3 RW Slice 3 of the device controller 'pizza' arbiter lbits:4 arb4 RW Slice 4 of the device controller 'pizza' arbiter lbits:4 arb5 RW Slice 5 of the device controller 'pizza' arbiter lbits:4 arb6 RW Slice 6 of the device controller 'pizza' arbiter lbits:4 arb7 RW Slice 7 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low) ulong value As longword endunion sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low) union sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High) {field (By field)} lbits:4 arb8 RW Slice 8 of the device controller 'pizza' arbiter lbits:4 arb9 RW Slice 9 of the device controller 'pizza' arbiter lbits:4 arb10 RW Slice 10 of the device controller 'pizza' arbiter lbits:4 arb11 RW Slice 11 of the device controller 'pizza' arbiter lbits:4 arb12 RW Slice 12 of the device controller 'pizza' arbiter lbits:4 arb13 RW Slice 13 of the device controller 'pizza' arbiter lbits:4 arb14 RW Slice 14 of the device controller 'pizza' arbiter lbits:4 arb15 RW Slice 15 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High) ulong value As longword endunion sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High) union sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout {field (By field)} lbits:8 timeout RW CrossBar Arbiter Timeout Preset Value lbits:8 reserved1 RES Reserved lbits:1 timeouten RW CrossBar Arbiter Timer Enable lbits:15 reserved0 RES Reserved {} or sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout ulong value As longword endunion sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout union dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 {field (By field)} lbits:8 updwin RW The window size, after the refresh command, in which DFCDL update is allowed lbits:5 reserved1 RES Reserved lbits:1 forceupdsync RW Forces the delay line update as soon as DFCDL is synchronized lbits:1 forceupdw RW Forces delay line update as soon as update window arrives lbits:1 blockupd RW Disables delay line update (unless using ForceUpdSync or ForceUpdW bits) lbits:1 updnosync RW Enables dynamic update without reaching sync condition lbits:1 updnowin RW Enables dynamic update without reaching update window lbits:1 forceacc RW Forces the filter state machine to accept bad values lbits:9 maxdiff RW Maximum difference between consecutive updates Filtering is performed on values multiplied by 4 lbits:4 reserved0 RES Reserved {} or dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 ulong value As longword endunion dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 union dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 {field (By field)} lbits:6 delpval RW Delay counter preset value lbits:1 fourcell RW Delay unit selects lbits:1 isense RW Multiply by two the value found by the search machine lbits:6 phased RW Delay Counter Phase Delta lbits:1 singlephase RW Search machine only searches for first phase lbits:1 reserved1 RES Reserved lbits:1 phasemode RW Phase Mode Jump lbits:1 reserved0 RES Reserved lbits:2 avg RW Average Value Calculation for Filter Process lbits:2 goodhits RW For the sync machine to enter the previous sync state, the number of times the good value must be received after the bad value lbits:2 goodsync RW For the sync machine to enter sync state, the number of times the good value must be received after loss of sync lbits:1 forcesync RW Forces the sync machine to enter the sync state lbits:1 holdsync RW Forces the sync machine to maintain this state lbits:1 resync RW Forces the sync machine to enter a loss of sync state lbits:2 avgrd RW Average used for read address of the SRAM lbits:1 stopimid RW Forces the filter machine to enter stop state lbits:1 stopsync RW Forces it to enter stop state, if there is sync condition lbits:1 goinit RW Forces it to remain in this state {} or dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 ulong value As longword endunion dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 union sram_address (Offset 0x1490) SRAM Address {field (By field)} lbits:32 addr RW SRAM address {} or sram_address (Offset 0x1490) SRAM Address ulong value As longword endunion sram_address (Offset 0x1490) SRAM Address union sram_data0 (Offset 0x1494) SRAM Data0 {field (By field)} lbits:32 data RW SRAM Write Data to initialize the DFCDL SRAM {} or sram_data0 (Offset 0x1494) SRAM Data0 ulong value As longword endunion sram_data0 (Offset 0x1494) SRAM Data0 union dfcdl_probe (Offset 0x14A0) DFCDL Probe {field (By field)} lbits:4 bussel RW Select DFCDL bus to be probed lbits:1 proben RW Probe Enabled lbits:27 reserved0 RES Reserved {} or dfcdl_probe (Offset 0x14A0) DFCDL Probe ulong value As longword endunion dfcdl_probe (Offset 0x14A0) DFCDL Probe union sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration {field (By field)} lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration ulong value As longword endunion sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration union sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration {field (By field)} lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration ulong value As longword endunion sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration union twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address {field (By field)} lbits:1 gce RW General Call Enable lbits:7 saddr RW Slave address lbits:24 reserved0 RES Reserved {} or twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address ulong value As longword endunion twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address union twsi_data (Offset 0xC004) Two-Wire Serial Interface Data {field (By field)} lbits:8 data RW Data/Address byte to be transmitted by the TWSI master or slave, or data byte received lbits:24 reserved0 RES Reserved {} or twsi_data (Offset 0xC004) Two-Wire Serial Interface Data ulong value As longword endunion twsi_data (Offset 0xC004) Two-Wire Serial Interface Data union twsi_control (Offset 0xC008) Two-Wire Serial Interface Control {field (By field)} lbits:2 reserved1 RES Reserved, read only lbits:1 ack RW Acknowledge lbits:1 iflg RW Interrupt Flag lbits:1 stop RW Stop lbits:1 start RW Start lbits:1 twsien RW TWSI enable lbits:1 inten RW Interrupt Enable lbits:24 reserved0 RES Reserved {} or twsi_control (Offset 0xC008) Two-Wire Serial Interface Control ulong value As longword endunion twsi_control (Offset 0xC008) Two-Wire Serial Interface Control union twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate {status (Status value)} lbits:8 stat RO TWSI Status lbits:24 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate {br (Baud rate)} lbits:3 n WO SCL frequency power of 2 lbits:4 m WO SCL frequency multiplier lbits:25 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate ulong value As longword endunion twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate union twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address {field (By field)} lbits:8 saddr RW Bits[7:0] of the 10-bit slave address lbits:24 reserved0 RES Reserved {} or twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address ulong value As longword endunion twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address union twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset {field (By field)} lbits:32 rst WO Write to this register resets the TWSI logic and sets all TWSI registers to their reset values {} or twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset ulong value As longword endunion twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset {} {atlantis_mcs (Atlantis machine check specific registers)} union main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) {field (By field)} lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) ulong value As longword endunion main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) union main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) {field (By field)} lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) ulong value As longword endunion main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) union cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) {field (By field)} lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) ulong value As longword endunion cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) union cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) {field (By field)} lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) ulong value As longword endunion cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) union cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) {field (By field)} lbits:32 erraddr RO Latched address bits [31:0] of a CPU transaction: illegal address (failed address decoding), access protection violation, bad data parity, bad address parity {} or cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) ulong value As longword endunion cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) union cpu_error_address_high (Offset 0x0078) CPU Error Address (High) {field (By field)} lbits:4 erraddr_h R Error Address bits [35:32] lbits:5 errpar R Address Parity bits lbits:1 hit R 1=HIT# asserted (cached) lbits:22 reserved R Reserved {} or cpu_error_address_high (Offset 0x0078) CPU Error Address (High) ulong value As longword endunion cpu_error_address_high (Offset 0x0078) CPU Error Address (High) union cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) {field (By field)} lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) ulong value As longword endunion cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) union cpu_error_data_high (Offset 0x0130) CPU Error Data (High) {field (By field)} lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_high (Offset 0x0130) CPU Error Data (High) ulong value As longword endunion cpu_error_data_high (Offset 0x0130) CPU Error Data (High) union cpu_error_parity (Offset 0x0138) CPU Error Parity {field (By field)} lbits:8 perrpar RO Latched data parity bus in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus lbits:2 gronk ?? Atlantis spec. error, Table 273--these bits are not defined!!! lbits:22 reserved0 RES Reserved {} or cpu_error_parity (Offset 0x0138) CPU Error Parity ulong value As longword endunion cpu_error_parity (Offset 0x0138) CPU Error Parity union cpu_error_cause (Offset 0x0140) CPU Error Cause {field (By field)} lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured {} or cpu_error_cause (Offset 0x0140) CPU Error Cause ulong value As longword endunion cpu_error_cause (Offset 0x0140) CPU Error Cause union cpu0_error_mask (Offset 0x0148) CPU0 Error Mask {field (By field)} lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured {} or cpu0_error_mask (Offset 0x0148) CPU0 Error Mask ulong value As longword endunion cpu0_error_mask (Offset 0x0148) CPU0 Error Mask union sram_configuration (Offset 0x0380) SRAM Configuration {field (By field)} lbits:2 ccen R/W Cache Coherency Enable lbits:2 reserved2 R Reserved lbits:1 paren R/W Parity Enable (gen. & check) lbits:1 perrpropen R/W Parity Error Propagate Enable lbits:1 forceparen R/W Force Parity Enable (debug) lbits:1 park R/W Arbiter Park on cross bar lbits:8 forcepar R/W Forced Parity Byte Value lbits:3 rtc R Reserved by Marvell (0x6) lbits:2 wtc R Reserved by Marvell (0x2) lbits:11 reserved1 R Reserved {} or sram_configuration (Offset 0x0380) SRAM Configuration ulong value As longword endunion sram_configuration (Offset 0x0380) SRAM Configuration union sram_error_cause (Offset 0x0388) SRAM Error Cause {field (By field)} lbits:1 perr0_7 R/W0C Parity Error Byte [7:0] lbits:1 perr8_15 R/W0C Parity Error Byte [15:8] lbits:1 perr16_23 R/W0C Parity Error Byte [23:16] lbits:1 perr24_31 R/W0C Parity Error Byte [31:24] lbits:1 perr32_39 R/W0C Parity Error Byte [39:32] lbits:1 perr40_47 R/W0C Parity Error Byte [47:40] lbits:1 perr48_55 R/W0C Parity Error Byte [55:48] lbits:1 perr56_63 R/W0C Parity Error Byte [63:56] lbits:24 reserved R Reserved {} or sram_error_cause (Offset 0x0388) SRAM Error Cause ulong value As longword endunion sram_error_cause (Offset 0x0388) SRAM Error Cause union sram_error_address (Offset 0x0390) SRAM Error Address {field (By field)} lbits:32 addr RW Error Address bits[31:0] {} or sram_error_address (Offset 0x0390) SRAM Error Address ulong value As longword endunion sram_error_address (Offset 0x0390) SRAM Error Address union sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) {field (By field)} lbits:32 data RW Error data {} or sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) ulong value As longword endunion sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) union sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) {field (By field)} lbits:32 data RW Error data {} or sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) ulong value As longword endunion sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) union sram_error_parity (Offset 0x03A8) SRAM Error Parity {field (By field)} lbits:8 par RW Error parity lbits:24 reserved0 RES Reserved {} or sram_error_parity (Offset 0x03A8) SRAM Error Parity ulong value As longword endunion sram_error_parity (Offset 0x03A8) SRAM Error Parity union sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) {field (By field)} lbits:4 addr RW Error Address bits[35:32] Latched upon SRAM parity error detection lbits:28 reserved0 RES Reserved {} or sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) ulong value As longword endunion sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) union device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause {field (By field)} lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause ulong value As longword endunion device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause union device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask {field (By field)} lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask ulong value As longword endunion device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask union device_error_address (Offset 0x04D8) Device Error Address {field (By field)} lbits:32 addr RW Latched Address Upon Device Error Condition {} or device_error_address (Offset 0x04D8) Device Error Address ulong value As longword endunion device_error_address (Offset 0x04D8) Device Error Address union device_error_data (Offset 0x04DC) Device Error Data {field (By field)} lbits:32 data RW Latched data upon parity error detection {} or device_error_data (Offset 0x04DC) Device Error Data ulong value As longword endunion device_error_data (Offset 0x04DC) Device Error Data union device_error_parity (Offset 0x04E0) Device Error Parity {field (By field)} lbits:4 par RW Latched parity upon parity error detection lbits:28 reserved0 RES Reserved, read only {} or device_error_parity (Offset 0x04E0) Device Error Parity ulong value As longword endunion device_error_parity (Offset 0x04E0) Device Error Parity union idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause {field (By field)} lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause ulong value As longword endunion idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause union idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask {field (By field)} lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask ulong value As longword endunion idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask union idma_error_address (Offset 0x08C8) IDMA Error Address {field (By field)} lbits:32 erraddr RW Bits[31:0] of Error Address {} or idma_error_address (Offset 0x08C8) IDMA Error Address ulong value As longword endunion idma_error_address (Offset 0x08C8) IDMA Error Address union sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) {field (By field)} lbits:32 eccdata RW Sampled 32 high bits of the last data with ECC error {} or sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) ulong value As longword endunion sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) union sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) {field (By field)} lbits:32 eccdata RW Sampled 32 low bits of the last data with ECC error {} or sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) ulong value As longword endunion sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) union sdram_received_ecc (Offset 0x1448) SDRAM Received ECC {field (By field)} lbits:8 eccreg RW ECC code being read from SDRAM lbits:24 reserved0 RES Reserved {} or sdram_received_ecc (Offset 0x1448) SDRAM Received ECC ulong value As longword endunion sdram_received_ecc (Offset 0x1448) SDRAM Received ECC union sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC {field (By field)} lbits:8 ecccalc RW ECC code calculated by Dunit lbits:24 reserved0 RES Reserved {} or sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC ulong value As longword endunion sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC union sdram_error_address (Offset 0x1450) SDRAM Error Address {field (By field /* NOTE: WOC just clears the dramerr)} lbits:1 errtype R/W0C Err Type (0=CDEs>limit, 1=UDE) lbits:2 bank R/W0C DIMM Bank (0-3) lbits:29 eccaddr R/W0C Address of Error [31:3] (NOTE: Atlantis spec. error, Table 303--indicates this field is 30 bits [31:2]; changed to 29 bits [31:3]) {} or sdram_error_address (Offset 0x1450) SDRAM Error Address ulong value As longword /* bit in the lower cause reg. endunion sdram_error_address (Offset 0x1450) SDRAM Error Address union sdram_ecc_control (Offset 0x1454) SDRAM ECC Control {field (By field)} lbits:8 forceecc R/W Forced ECC Byte Value lbits:1 forceeccen R/W Write 'forceecc' Enable (debug) lbits:1 perrpropen R/W Propagate PERR to ECC mem. Err lbits:6 reserved2 R Reserved lbits:8 threcc R/W Threshold for reporting CDEs lbits:8 reserved1 R Reserved {} or sdram_ecc_control (Offset 0x1454) SDRAM ECC Control ulong value As longword endunion sdram_ecc_control (Offset 0x1454) SDRAM ECC Control union sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter {field (By field)} lbits:32 count R Number of single bit ECC errors detected {} or sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter ulong value As longword endunion sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter {} {decoder (Decoder)} {rsvd (03 Reserved)} utiny value {} union gpo_c 02 GPO C: Enet Card Reset.. {field (By field)} tbits:7 rsvd R Reserved tbits:1 enet_card_rst R/W Ethernet Card Reset {} or gpo_c 02 GPO C: Enet Card Reset.. utiny value As utiny endunion gpo_c 02 GPO C: Enet Card Reset.. union gpi 01 GPI B: Module Type.. {field (By field)} tbits:4 mod_type R Module Type tbits:3 rsvd R Reserved tbits:1 enet_gpi R/W Ethernet Card GPI {} or gpi 01 GPI B: Module Type.. utiny value As utiny endunion gpi 01 GPI B: Module Type.. union mod_rev 00 GPI A: Module Revision {field (By field)} tbits:3 rev R Revision tbits:5 eco_level R ECO Level {} or mod_rev 00 GPI A: Module Revision utiny value As utiny endunion mod_rev 00 GPI A: Module Revision {rsvd1[1] (06-FC Reserved)} utiny value {} {rsvd1[0] (06-FC Reserved)} utiny value {} union gpo_bstat1 05 GPO E: Boot Status LEDs.. {field (By field)} tbits:1 led8 R/W Boot Status LED 8 tbits:1 led9 R/W Boot Status LED 9 tbits:6 rsvd R Reserved {} or gpo_bstat1 05 GPO E: Boot Status LEDs.. utiny value As utiny endunion gpo_bstat1 05 GPO E: Boot Status LEDs.. union bstat0 04 GPO D: Boot Status LEDs {field (By field)} tbits:1 led0 R/W Boot Status LED 8 tbits:1 led1 R/W Boot Status LED 9 tbits:1 led2 R/W Boot Status LED 9 tbits:1 led3 R/W Boot Status LED 9 tbits:1 led4 R/W Boot Status LED 9 tbits:1 led5 R/W Boot Status LED 9 tbits:1 led6 R/W Boot Status LED 9 tbits:1 led7 R/W Boot Status LED 9 {} or bstat0 04 GPO D: Boot Status LEDs utiny value As utiny endunion bstat0 04 GPO D: Boot Status LEDs {rsvd1[5] (06-FC Reserved)} utiny value {} {rsvd1[4] (06-FC Reserved)} utiny value {} {rsvd1[3] (06-FC Reserved)} utiny value {} {rsvd1[2] (06-FC Reserved)} utiny value {} {rsvd1[9] (06-FC Reserved)} utiny value {} {rsvd1[8] (06-FC Reserved)} utiny value {} {rsvd1[7] (06-FC Reserved)} utiny value {} {rsvd1[6] (06-FC Reserved)} utiny value {} {rsvd1[13] (06-FC Reserved)} utiny value {} {rsvd1[12] (06-FC Reserved)} utiny value {} {rsvd1[11] (06-FC Reserved)} utiny value {} {rsvd1[10] (06-FC Reserved)} utiny value {} {rsvd1[17] (06-FC Reserved)} utiny value {} {rsvd1[16] (06-FC Reserved)} utiny value {} {rsvd1[15] (06-FC Reserved)} utiny value {} {rsvd1[14] (06-FC Reserved)} utiny value {} {rsvd1[21] (06-FC Reserved)} utiny value {} {rsvd1[20] (06-FC Reserved)} utiny value {} {rsvd1[19] (06-FC Reserved)} utiny value {} {rsvd1[18] (06-FC Reserved)} utiny value {} {rsvd1[25] (06-FC Reserved)} utiny value {} {rsvd1[24] (06-FC Reserved)} utiny value {} {rsvd1[23] (06-FC Reserved)} utiny value {} {rsvd1[22] (06-FC Reserved)} utiny value {} {rsvd1[29] (06-FC Reserved)} utiny value {} {rsvd1[28] (06-FC Reserved)} utiny value {} {rsvd1[27] (06-FC Reserved)} utiny value {} {rsvd1[26] (06-FC Reserved)} utiny value {} {rsvd1[33] (06-FC Reserved)} utiny value {} {rsvd1[32] (06-FC Reserved)} utiny value {} {rsvd1[31] (06-FC Reserved)} utiny value {} {rsvd1[30] (06-FC Reserved)} utiny value {} {rsvd1[37] (06-FC Reserved)} utiny value {} {rsvd1[36] (06-FC Reserved)} utiny value {} {rsvd1[35] (06-FC Reserved)} utiny value {} {rsvd1[34] (06-FC Reserved)} utiny value {} {rsvd1[41] (06-FC Reserved)} utiny value {} {rsvd1[40] (06-FC Reserved)} utiny value {} {rsvd1[39] (06-FC Reserved)} utiny value {} {rsvd1[38] (06-FC Reserved)} utiny value {} {rsvd1[45] (06-FC Reserved)} utiny value {} {rsvd1[44] (06-FC Reserved)} utiny value {} {rsvd1[43] (06-FC Reserved)} utiny value {} {rsvd1[42] (06-FC Reserved)} utiny value {} {rsvd1[49] (06-FC Reserved)} utiny value {} {rsvd1[48] (06-FC Reserved)} utiny value {} {rsvd1[47] (06-FC Reserved)} utiny value {} {rsvd1[46] (06-FC Reserved)} utiny value {} {rsvd1[53] (06-FC Reserved)} utiny value {} {rsvd1[52] (06-FC Reserved)} utiny value {} {rsvd1[51] (06-FC Reserved)} utiny value {} {rsvd1[50] (06-FC Reserved)} utiny value {} {rsvd1[57] (06-FC Reserved)} utiny value {} {rsvd1[56] (06-FC Reserved)} utiny value {} {rsvd1[55] (06-FC Reserved)} utiny value {} {rsvd1[54] (06-FC Reserved)} utiny value {} {rsvd1[61] (06-FC Reserved)} utiny value {} {rsvd1[60] (06-FC Reserved)} utiny value {} {rsvd1[59] (06-FC Reserved)} utiny value {} {rsvd1[58] (06-FC Reserved)} utiny value {} {rsvd1[65] (06-FC Reserved)} utiny value {} {rsvd1[64] (06-FC Reserved)} utiny value {} {rsvd1[63] (06-FC Reserved)} utiny value {} {rsvd1[62] (06-FC Reserved)} utiny value {} {rsvd1[69] (06-FC Reserved)} utiny value {} {rsvd1[68] (06-FC Reserved)} utiny value {} {rsvd1[67] (06-FC Reserved)} utiny value {} {rsvd1[66] (06-FC Reserved)} utiny value {} {rsvd1[73] (06-FC Reserved)} utiny value {} {rsvd1[72] (06-FC Reserved)} utiny value {} {rsvd1[71] (06-FC Reserved)} utiny value {} {rsvd1[70] (06-FC Reserved)} utiny value {} {rsvd1[77] (06-FC Reserved)} utiny value {} {rsvd1[76] (06-FC Reserved)} utiny value {} {rsvd1[75] (06-FC Reserved)} utiny value {} {rsvd1[74] (06-FC Reserved)} utiny value {} {rsvd1[81] (06-FC Reserved)} utiny value {} {rsvd1[80] (06-FC Reserved)} utiny value {} {rsvd1[79] (06-FC Reserved)} utiny value {} {rsvd1[78] (06-FC Reserved)} utiny value {} {rsvd1[85] (06-FC Reserved)} utiny value {} {rsvd1[84] (06-FC Reserved)} utiny value {} {rsvd1[83] (06-FC Reserved)} utiny value {} {rsvd1[82] (06-FC Reserved)} utiny value {} {rsvd1[89] (06-FC Reserved)} utiny value {} {rsvd1[88] (06-FC Reserved)} utiny value {} {rsvd1[87] (06-FC Reserved)} utiny value {} {rsvd1[86] (06-FC Reserved)} utiny value {} {rsvd1[93] (06-FC Reserved)} utiny value {} {rsvd1[92] (06-FC Reserved)} utiny value {} {rsvd1[91] (06-FC Reserved)} utiny value {} {rsvd1[90] (06-FC Reserved)} utiny value {} {rsvd1[97] (06-FC Reserved)} utiny value {} {rsvd1[96] (06-FC Reserved)} utiny value {} {rsvd1[95] (06-FC Reserved)} utiny value {} {rsvd1[94] (06-FC Reserved)} utiny value {} {rsvd1[101] (06-FC Reserved)} utiny value {} {rsvd1[100] (06-FC Reserved)} utiny value {} {rsvd1[99] (06-FC Reserved)} utiny value {} {rsvd1[98] (06-FC Reserved)} utiny value {} {rsvd1[105] (06-FC Reserved)} utiny value {} {rsvd1[104] (06-FC Reserved)} utiny value {} {rsvd1[103] (06-FC Reserved)} utiny value {} {rsvd1[102] (06-FC Reserved)} utiny value {} {rsvd1[109] (06-FC Reserved)} utiny value {} {rsvd1[108] (06-FC Reserved)} utiny value {} {rsvd1[107] (06-FC Reserved)} utiny value {} {rsvd1[106] (06-FC Reserved)} utiny value {} {rsvd1[113] (06-FC Reserved)} utiny value {} {rsvd1[112] (06-FC Reserved)} utiny value {} {rsvd1[111] (06-FC Reserved)} utiny value {} {rsvd1[110] (06-FC Reserved)} utiny value {} {rsvd1[117] (06-FC Reserved)} utiny value {} {rsvd1[116] (06-FC Reserved)} utiny value {} {rsvd1[115] (06-FC Reserved)} utiny value {} {rsvd1[114] (06-FC Reserved)} utiny value {} {rsvd1[121] (06-FC Reserved)} utiny value {} {rsvd1[120] (06-FC Reserved)} utiny value {} {rsvd1[119] (06-FC Reserved)} utiny value {} {rsvd1[118] (06-FC Reserved)} utiny value {} {rsvd1[125] (06-FC Reserved)} utiny value {} {rsvd1[124] (06-FC Reserved)} utiny value {} {rsvd1[123] (06-FC Reserved)} utiny value {} {rsvd1[122] (06-FC Reserved)} utiny value {} {rsvd1[129] (06-FC Reserved)} utiny value {} {rsvd1[128] (06-FC Reserved)} utiny value {} {rsvd1[127] (06-FC Reserved)} utiny value {} {rsvd1[126] (06-FC Reserved)} utiny value {} {rsvd1[133] (06-FC Reserved)} utiny value {} {rsvd1[132] (06-FC Reserved)} utiny value {} {rsvd1[131] (06-FC Reserved)} utiny value {} {rsvd1[130] (06-FC Reserved)} utiny value {} {rsvd1[137] (06-FC Reserved)} utiny value {} {rsvd1[136] (06-FC Reserved)} utiny value {} {rsvd1[135] (06-FC Reserved)} utiny value {} {rsvd1[134] (06-FC Reserved)} utiny value {} {rsvd1[141] (06-FC Reserved)} utiny value {} {rsvd1[140] (06-FC Reserved)} utiny value {} {rsvd1[139] (06-FC Reserved)} utiny value {} {rsvd1[138] (06-FC Reserved)} utiny value {} {rsvd1[145] (06-FC Reserved)} utiny value {} {rsvd1[144] (06-FC Reserved)} utiny value {} {rsvd1[143] (06-FC Reserved)} utiny value {} {rsvd1[142] (06-FC Reserved)} utiny value {} {rsvd1[149] (06-FC Reserved)} utiny value {} {rsvd1[148] (06-FC Reserved)} utiny value {} {rsvd1[147] (06-FC Reserved)} utiny value {} {rsvd1[146] (06-FC Reserved)} utiny value {} {rsvd1[153] (06-FC Reserved)} utiny value {} {rsvd1[152] (06-FC Reserved)} utiny value {} {rsvd1[151] (06-FC Reserved)} utiny value {} {rsvd1[150] (06-FC Reserved)} utiny value {} {rsvd1[157] (06-FC Reserved)} utiny value {} {rsvd1[156] (06-FC Reserved)} utiny value {} {rsvd1[155] (06-FC Reserved)} utiny value {} {rsvd1[154] (06-FC Reserved)} utiny value {} {rsvd1[161] (06-FC Reserved)} utiny value {} {rsvd1[160] (06-FC Reserved)} utiny value {} {rsvd1[159] (06-FC Reserved)} utiny value {} {rsvd1[158] (06-FC Reserved)} utiny value {} {rsvd1[165] (06-FC Reserved)} utiny value {} {rsvd1[164] (06-FC Reserved)} utiny value {} {rsvd1[163] (06-FC Reserved)} utiny value {} {rsvd1[162] (06-FC Reserved)} utiny value {} {rsvd1[169] (06-FC Reserved)} utiny value {} {rsvd1[168] (06-FC Reserved)} utiny value {} {rsvd1[167] (06-FC Reserved)} utiny value {} {rsvd1[166] (06-FC Reserved)} utiny value {} {rsvd1[173] (06-FC Reserved)} utiny value {} {rsvd1[172] (06-FC Reserved)} utiny value {} {rsvd1[171] (06-FC Reserved)} utiny value {} {rsvd1[170] (06-FC Reserved)} utiny value {} {rsvd1[177] (06-FC Reserved)} utiny value {} {rsvd1[176] (06-FC Reserved)} utiny value {} {rsvd1[175] (06-FC Reserved)} utiny value {} {rsvd1[174] (06-FC Reserved)} utiny value {} {rsvd1[181] (06-FC Reserved)} utiny value {} {rsvd1[180] (06-FC Reserved)} utiny value {} {rsvd1[179] (06-FC Reserved)} utiny value {} {rsvd1[178] (06-FC Reserved)} utiny value {} {rsvd1[185] (06-FC Reserved)} utiny value {} {rsvd1[184] (06-FC Reserved)} utiny value {} {rsvd1[183] (06-FC Reserved)} utiny value {} {rsvd1[182] (06-FC Reserved)} utiny value {} {rsvd1[189] (06-FC Reserved)} utiny value {} {rsvd1[188] (06-FC Reserved)} utiny value {} {rsvd1[187] (06-FC Reserved)} utiny value {} {rsvd1[186] (06-FC Reserved)} utiny value {} {rsvd1[193] (06-FC Reserved)} utiny value {} {rsvd1[192] (06-FC Reserved)} utiny value {} {rsvd1[191] (06-FC Reserved)} utiny value {} {rsvd1[190] (06-FC Reserved)} utiny value {} {rsvd1[197] (06-FC Reserved)} utiny value {} {rsvd1[196] (06-FC Reserved)} utiny value {} {rsvd1[195] (06-FC Reserved)} utiny value {} {rsvd1[194] (06-FC Reserved)} utiny value {} {rsvd1[201] (06-FC Reserved)} utiny value {} {rsvd1[200] (06-FC Reserved)} utiny value {} {rsvd1[199] (06-FC Reserved)} utiny value {} {rsvd1[198] (06-FC Reserved)} utiny value {} {rsvd1[205] (06-FC Reserved)} utiny value {} {rsvd1[204] (06-FC Reserved)} utiny value {} {rsvd1[203] (06-FC Reserved)} utiny value {} {rsvd1[202] (06-FC Reserved)} utiny value {} {rsvd1[209] (06-FC Reserved)} utiny value {} {rsvd1[208] (06-FC Reserved)} utiny value {} {rsvd1[207] (06-FC Reserved)} utiny value {} {rsvd1[206] (06-FC Reserved)} utiny value {} {rsvd1[213] (06-FC Reserved)} utiny value {} {rsvd1[212] (06-FC Reserved)} utiny value {} {rsvd1[211] (06-FC Reserved)} utiny value {} {rsvd1[210] (06-FC Reserved)} utiny value {} {rsvd1[217] (06-FC Reserved)} utiny value {} {rsvd1[216] (06-FC Reserved)} utiny value {} {rsvd1[215] (06-FC Reserved)} utiny value {} {rsvd1[214] (06-FC Reserved)} utiny value {} {rsvd1[221] (06-FC Reserved)} utiny value {} {rsvd1[220] (06-FC Reserved)} utiny value {} {rsvd1[219] (06-FC Reserved)} utiny value {} {rsvd1[218] (06-FC Reserved)} utiny value {} {rsvd1[225] (06-FC Reserved)} utiny value {} {rsvd1[224] (06-FC Reserved)} utiny value {} {rsvd1[223] (06-FC Reserved)} utiny value {} {rsvd1[222] (06-FC Reserved)} utiny value {} {rsvd1[229] (06-FC Reserved)} utiny value {} {rsvd1[228] (06-FC Reserved)} utiny value {} {rsvd1[227] (06-FC Reserved)} utiny value {} {rsvd1[226] (06-FC Reserved)} utiny value {} {rsvd1[233] (06-FC Reserved)} utiny value {} {rsvd1[232] (06-FC Reserved)} utiny value {} {rsvd1[231] (06-FC Reserved)} utiny value {} {rsvd1[230] (06-FC Reserved)} utiny value {} {rsvd1[237] (06-FC Reserved)} utiny value {} {rsvd1[236] (06-FC Reserved)} utiny value {} {rsvd1[235] (06-FC Reserved)} utiny value {} {rsvd1[234] (06-FC Reserved)} utiny value {} {rsvd1[241] (06-FC Reserved)} utiny value {} {rsvd1[240] (06-FC Reserved)} utiny value {} {rsvd1[239] (06-FC Reserved)} utiny value {} {rsvd1[238] (06-FC Reserved)} utiny value {} {rsvd1[245] (06-FC Reserved)} utiny value {} {rsvd1[244] (06-FC Reserved)} utiny value {} {rsvd1[243] (06-FC Reserved)} utiny value {} {rsvd1[242] (06-FC Reserved)} utiny value {} {decoder_major_rev (FF Decoder Major Revision)} utiny value {} {decoder_minor_rev (FE Decoder Minor Revision)} utiny value {} {scratch (FD Scratch Register)} utiny value {} {rsvd1[246] (06-FC Reserved)} utiny value {} {} {toyclock (DS1557 4MEG NV Y2KC Timekeeping RAM)} union alarm_minutes Alarm Minutes Union utiny value Alarm Minutes as byte or alarm_minutes Alarm Minutes Union {bits (Alarm Minutes by field)} tbits:4 minutes tbits:3 ten_minutes tbits:1 am2 {} endunion alarm_minutes Alarm Minutes Union union alarm_seconds Alarm Seconds Union utiny value Alarm Seconds as byte or alarm_seconds Alarm Seconds Union {bits (Alarm Seconds by field)} tbits:4 seconds tbits:3 ten_seconds tbits:1 am1 {} endunion alarm_seconds Alarm Seconds Union utiny unused union flag Alarm Enable/Status and Battery Status Flags Union utiny value Alarm Enable/Status and Battery Status Flags as byte or flag Alarm Enable/Status and Battery Status Flags Union {bits (Alarm Enable/Status and Battery Status Flags by field)} tbits:4 unused2 tbits:1 bat_low tbits:1 unused1 tbits:1 alarm tbits:1 alarm_enable {} endunion flag Alarm Enable/Status and Battery Status Flags Union union watchdog Watchdog Timer Control Flags Union utiny value Watchdog Timer Control Flags as byte or watchdog Watchdog Timer Control Flags Union {bits (Watchdog Timer Control Flags by field)} tbits:7 multiplier tbits:1 steering_bit {} endunion watchdog Watchdog Timer Control Flags Union union interrupts Alarm Interrupt Enables Union utiny value Alarm Interrupt Enables as byte or interrupts Alarm Interrupt Enables Union {bits (Alarm Interrupt Enables by field)} tbits:5 unused2 tbits:1 alarm_enable_in_bat tbits:1 unused1 tbits:1 alarm_enable {} endunion interrupts Alarm Interrupt Enables Union union alarm_date Alarm Date Union utiny value Alarm Date as byte or alarm_date Alarm Date Union {bits (Alarm Date by field)} tbits:4 date tbits:2 ten_date tbits:1 unused tbits:1 am4 {} endunion alarm_date Alarm Date Union union alarm_hours Alarm Hours Union utiny value Alarm Hours as byte or alarm_hours Alarm Hours Union {alarm_hours (Alarm Hours by field)} tbits:4 hours tbits:2 ten_hours tbits:1 unused tbits:1 am3 {} endunion alarm_hours Alarm Hours Union union hour Hour Union utiny value Hour as byte or hour Hour Union {bits (Hour by field)} tbits:6 hour tbits:2 unused {} endunion hour Hour Union union minutes Minutes Union utiny value Minutes as byte or minutes Minutes Union {bits (Minutes by field)} tbits:7 minutes tbits:1 unused {} endunion minutes Minutes Union union seconds Seconds/Oscillator Control Union utiny value Seconds/Oscillator Control as byte or seconds Seconds/Oscillator Control Union {bits (Seconds/Oscillator Control by field)} tbits:7 seconds tbits:1 osc {} endunion seconds Seconds/Oscillator Control Union union control TOY Control Flags/Century Union utiny value TOY Control Flags/Century as byte or control TOY Control Flags/Century Union {bits (TOY Control Flags/Century by field)} tbits:6 century tbits:1 read_bit tbits:1 write_bit {} endunion control TOY Control Flags/Century Union utiny year Year as byte union month Month Union utiny value Month as byte or month Month Union {bits (Month by field)} tbits:5 month tbits:3 unused {} endunion month Month Union union date Date Union utiny value Date as byte or date Date Union {bits (Date by field)} tbits:6 date tbits:2 unused {} endunion date Date Union union day Day Union utiny value Day/Frequency Test as byte or day Day Union {bits (Day/Frequency Test by field)} tbits:3 day tbits:3 unused2 tbits:1 freq_test tbits:1 unused1 {} endunion day Day Union {} {glue (Glue register save area)} union csr Glue CSR Registers ulong[256] csra Glue CSR Registers As Longwords or csr Glue CSR Registers {csrfield (Glue CSR Registers By Field)} {rsvd[0] (03-0F Reserved)} utiny value {} {self_reset (02 Self Reset (0xD1))} utiny value {} union reset_in 01 Reset Inputs {field (By field)} tbits:1 button_self R/W Button or Self Reset tbits:1 kill_other R/W Other, Kill Reset tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset tbits:1 swd R/W SW Watchdog Reset tbits:3 rsvd R Reserved {} or reset_in 01 Reset Inputs utiny value As utiny endunion reset_in 01 Reset Inputs union reset_dis 00 Reset Disables {field (By field)} tbits:1 button_self R/W Button or Self Reset tbits:1 kill_other R/W Other, Kill Reset tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset tbits:1 swd R/W SW Watchdog Reset tbits:3 rsvd R Reserved {} or reset_dis 00 Reset Disables utiny value As utiny endunion reset_dis 00 Reset Disables {rsvd[4] (03-0F Reserved)} utiny value {} {rsvd[3] (03-0F Reserved)} utiny value {} {rsvd[2] (03-0F Reserved)} utiny value {} {rsvd[1] (03-0F Reserved)} utiny value {} {rsvd[8] (03-0F Reserved)} utiny value {} {rsvd[7] (03-0F Reserved)} utiny value {} {rsvd[6] (03-0F Reserved)} utiny value {} {rsvd[5] (03-0F Reserved)} utiny value {} {rsvd[12] (03-0F Reserved)} utiny value {} {rsvd[11] (03-0F Reserved)} utiny value {} {rsvd[10] (03-0F Reserved)} utiny value {} {rsvd[9] (03-0F Reserved)} utiny value {} {rsvd1[0] (13-21 Reserved)} utiny value {} union req 12 Request {field (By field)} tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or req 12 Request utiny value As utiny endunion req 12 Request union gnt 11 Grant {field (By field)} tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or gnt 11 Grant utiny value As utiny endunion gnt 11 Grant union arb 10 Arbitration Control & Status {field (By field)} tbits:2 ctrl0 R/W PCIX0 Arb Control tbits:2 state0 R PCIX0 Arb State tbits:2 ctrl1 R/W PCIX1 Arb Control tbits:2 state1 R PCIX1 Arb State {} or arb 10 Arbitration Control & Status utiny value As utiny endunion arb 10 Arbitration Control & Status {rsvd1[4] (13-21 Reserved)} utiny value {} {rsvd1[3] (13-21 Reserved)} utiny value {} {rsvd1[2] (13-21 Reserved)} utiny value {} {rsvd1[1] (13-21 Reserved)} utiny value {} {rsvd1[8] (13-21 Reserved)} utiny value {} {rsvd1[7] (13-21 Reserved)} utiny value {} {rsvd1[6] (13-21 Reserved)} utiny value {} {rsvd1[5] (13-21 Reserved)} utiny value {} {rsvd1[12] (13-21 Reserved)} utiny value {} {rsvd1[11] (13-21 Reserved)} utiny value {} {rsvd1[10] (13-21 Reserved)} utiny value {} {rsvd1[9] (13-21 Reserved)} utiny value {} {swd_tp (23 SW Watchdog Timer Trip Pt.)} utiny value {} {swd_ct (22 SW Watchdog Current Time)} utiny value {} {rsvd1[14] (13-21 Reserved)} utiny value {} {rsvd1[13] (13-21 Reserved)} utiny value {} {rsvd2[0] (27-3F Reserved)} utiny value {} union timer_ctrl 26 Timer Control {field (By field)} tbits:1 mbd_ok R/W Driven Lo when Watchdog Expires tbits:1 rsvd1 R Reserved tbits:1 ena_swd R/W SW Watchdog Timer Enable tbits:1 ena_ppc R/W PPC Bus Snoop Timer Enable tbits:3 rsvd R Reserved tbits:1 swd_rst R/W1R SW Watchdog Reset/Restart {} or timer_ctrl 26 Timer Control utiny value As utiny endunion timer_ctrl 26 Timer Control {ppc_sv (25 PPC " " Timer Start Value)} utiny value {} {ppc_ct (24 PPC Bus Snoop Current Value)} utiny value {} {rsvd2[4] (27-3F Reserved)} utiny value {} {rsvd2[3] (27-3F Reserved)} utiny value {} {rsvd2[2] (27-3F Reserved)} utiny value {} {rsvd2[1] (27-3F Reserved)} utiny value {} {rsvd2[8] (27-3F Reserved)} utiny value {} {rsvd2[7] (27-3F Reserved)} utiny value {} {rsvd2[6] (27-3F Reserved)} utiny value {} {rsvd2[5] (27-3F Reserved)} utiny value {} {rsvd2[12] (27-3F Reserved)} utiny value {} {rsvd2[11] (27-3F Reserved)} utiny value {} {rsvd2[10] (27-3F Reserved)} utiny value {} {rsvd2[9] (27-3F Reserved)} utiny value {} {rsvd2[16] (27-3F Reserved)} utiny value {} {rsvd2[15] (27-3F Reserved)} utiny value {} {rsvd2[14] (27-3F Reserved)} utiny value {} {rsvd2[13] (27-3F Reserved)} utiny value {} {rsvd2[20] (27-3F Reserved)} utiny value {} {rsvd2[19] (27-3F Reserved)} utiny value {} {rsvd2[18] (27-3F Reserved)} utiny value {} {rsvd2[17] (27-3F Reserved)} utiny value {} {rsvd2[24] (27-3F Reserved)} utiny value {} {rsvd2[23] (27-3F Reserved)} utiny value {} {rsvd2[22] (27-3F Reserved)} utiny value {} {rsvd2[21] (27-3F Reserved)} utiny value {} {supply_a_off (43 Supply A Turn Off (0xA5))} utiny value {} {rsvd3 (42 Reserved)} utiny value {} {kill_other (41 Kill Other Controller (0x37))} utiny value {} union dis_ctrl 40 Disable Control {field (By field)} tbits:1 ena_kill_other R/W Kill Other Controller - Enable tbits:1 rsvd1 R Reserved tbits:1 ena_ps_a_off R/W Power Supply A Off - Enable tbits:1 ena_ps_b_off R/W Power Supply B Off - Enable tbits:1 amb_ps_a_led R/W Amber Power Supply A Failure LED {E1} tbits:1 amb_ps_b_led R/W Amber Power Supply B Failure LED {E2} tbits:2 rsvd R Reserved {} or dis_ctrl 40 Disable Control utiny value As utiny endunion dis_ctrl 40 Disable Control union iic_bus_ctrl 47 Atlantis IIC Bus Control {field (By field Bus: A B C D)} tbits:3 iic_sel R/W IIC Bus Select {AA9, AB9, W9, Y9} tbits:5 rsvd R Reserved {} or iic_bus_ctrl 47 Atlantis IIC Bus Control utiny value As utiny endunion iic_bus_ctrl 47 Atlantis IIC Bus Control {rsvdz[1] (45-46 Reserved)} utiny value {} {rsvdz[0] (45-46 Reserved)} utiny value {} {supply_b_off (44 Supply B Turn Off (0xB5))} utiny value {} {rsvd4[3] (48-4F Reserved)} utiny value {} {rsvd4[2] (48-4F Reserved)} utiny value {} {rsvd4[1] (48-4F Reserved)} utiny value {} {rsvd4[0] (48-4F Reserved)} utiny value {} {rsvd4[7] (48-4F Reserved)} utiny value {} {rsvd4[6] (48-4F Reserved)} utiny value {} {rsvd4[5] (48-4F Reserved)} utiny value {} {rsvd4[4] (48-4F Reserved)} utiny value {} {rsvd5[2] (51-5F Reserved)} utiny value {} {rsvd5[1] (51-5F Reserved)} utiny value {} {rsvd5[0] (51-5F Reserved)} utiny value {} union int_out 50 Interrupt Out {field (By field)} tbits:1 other_l R/W Int. to Other Ctrllr (Int=0) {V12} tbits:1 rsvd1 R Reserved {U12} tbits:1 smi_l R/W System Management Int. (Int=0) {B6} tbits:1 mcp_l R/W Machine Check Interrupt (Int=0) {A6} tbits:4 rsvd R Reserved {} or int_out 50 Interrupt Out utiny value As utiny endunion int_out 50 Interrupt Out {rsvd5[6] (51-5F Reserved)} utiny value {} {rsvd5[5] (51-5F Reserved)} utiny value {} {rsvd5[4] (51-5F Reserved)} utiny value {} {rsvd5[3] (51-5F Reserved)} utiny value {} {rsvd5[10] (51-5F Reserved)} utiny value {} {rsvd5[9] (51-5F Reserved)} utiny value {} {rsvd5[8] (51-5F Reserved)} utiny value {} {rsvd5[7] (51-5F Reserved)} utiny value {} {rsvd5[14] (51-5F Reserved)} utiny value {} {rsvd5[13] (51-5F Reserved)} utiny value {} {rsvd5[12] (51-5F Reserved)} utiny value {} {rsvd5[11] (51-5F Reserved)} utiny value {} union int_smi_3 63 SMI Interrupt 31:24 (Int=1) {field (By field)} tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_smi_3 63 SMI Interrupt 31:24 (Int=1) utiny value As utiny endunion int_smi_3 63 SMI Interrupt 31:24 (Int=1) union int_smi_2 62 SMI Interrupt 23:16 (Int=1) {field (By field)} tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_smi_2 62 SMI Interrupt 23:16 (Int=1) utiny value As utiny endunion int_smi_2 62 SMI Interrupt 23:16 (Int=1) union int_smi_1 61 SMI Interrupt 15:08 (Int=1) {field (By field)} tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_smi_1 61 SMI Interrupt 15:08 (Int=1) utiny value As utiny endunion int_smi_1 61 SMI Interrupt 15:08 (Int=1) union int_smi_0 60 SMI Interrupt 07:00 (Int=1) {field (By field)} tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_smi_0 60 SMI Interrupt 07:00 (Int=1) utiny value As utiny endunion int_smi_0 60 SMI Interrupt 07:00 (Int=1) union ena_smi_2 67 SMI Enables 23:16 {field (By field)} tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_smi_2 67 SMI Enables 23:16 utiny value As utiny endunion ena_smi_2 67 SMI Enables 23:16 union ena_smi_1 66 SMI Enables 15:08 {field (By field)} tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_smi_1 66 SMI Enables 15:08 utiny value As utiny endunion ena_smi_1 66 SMI Enables 15:08 union ena_smi_0 65 SMI Enables 07:00 {field (By field)} tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_smi_0 65 SMI Enables 07:00 utiny value As utiny endunion ena_smi_0 65 SMI Enables 07:00 union int_smi_4 64 SMI Interrupt 39:32 (Int=1) {field (By field)} tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_smi_4 64 SMI Interrupt 39:32 (Int=1) utiny value As utiny endunion int_smi_4 64 SMI Interrupt 39:32 (Int=1) union int_mcp_1 6B MCP Interrupt 15:08 (Int=1) {field (By field)} tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_mcp_1 6B MCP Interrupt 15:08 (Int=1) utiny value As utiny endunion int_mcp_1 6B MCP Interrupt 15:08 (Int=1) union int_mcp_0 6A MCP Interrupt 07:00 (Int=1) {field (By field)} tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_mcp_0 6A MCP Interrupt 07:00 (Int=1) utiny value As utiny endunion int_mcp_0 6A MCP Interrupt 07:00 (Int=1) union ena_smi_4 69 SMI Enables 39:32 {field (By field)} tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_smi_4 69 SMI Enables 39:32 utiny value As utiny endunion ena_smi_4 69 SMI Enables 39:32 union ena_smi_3 68 SMI Enables 31:24 {field (By field)} tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_smi_3 68 SMI Enables 31:24 utiny value As utiny endunion ena_smi_3 68 SMI Enables 31:24 union ena_mcp_0 6F MCP Enables 07:00 {field (By field)} tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_mcp_0 6F MCP Enables 07:00 utiny value As utiny endunion ena_mcp_0 6F MCP Enables 07:00 union int_mcp_4 6E MCP Interrupt 39:32 (Int=1) {field (By field)} tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_mcp_4 6E MCP Interrupt 39:32 (Int=1) utiny value As utiny endunion int_mcp_4 6E MCP Interrupt 39:32 (Int=1) union int_mcp_3 6D MCP Interrupt 31:24 (Int=1) {field (By field)} tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_mcp_3 6D MCP Interrupt 31:24 (Int=1) utiny value As utiny endunion int_mcp_3 6D MCP Interrupt 31:24 (Int=1) union int_mcp_2 6C MCP Interrupt 23:16 (Int=1) {field (By field)} tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_mcp_2 6C MCP Interrupt 23:16 (Int=1) utiny value As utiny endunion int_mcp_2 6C MCP Interrupt 23:16 (Int=1) union ena_mcp_4 73 MCP Enables 39:32 {field (By field)} tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_mcp_4 73 MCP Enables 39:32 utiny value As utiny endunion ena_mcp_4 73 MCP Enables 39:32 union ena_mcp_3 72 MCP Enables 31:24 {field (By field)} tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_mcp_3 72 MCP Enables 31:24 utiny value As utiny endunion ena_mcp_3 72 MCP Enables 31:24 union ena_mcp_2 71 MCP Enables 23:16 {field (By field)} tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_mcp_2 71 MCP Enables 23:16 utiny value As utiny endunion ena_mcp_2 71 MCP Enables 23:16 union ena_mcp_1 70 MCP Enables 15:08 {field (By field)} tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_mcp_1 70 MCP Enables 15:08 utiny value As utiny endunion ena_mcp_1 70 MCP Enables 15:08 union int_in_3 77 Interrupt Inputs 31:24 {field (By field)} tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_in_3 77 Interrupt Inputs 31:24 utiny value As utiny endunion int_in_3 77 Interrupt Inputs 31:24 union int_in_2 76 Interrupt Inputs 23:16 {field (By field)} tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_in_2 76 Interrupt Inputs 23:16 utiny value As utiny endunion int_in_2 76 Interrupt Inputs 23:16 union int_in_1 75 Interrupt Inputs 15:08 {field (By field)} tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_in_1 75 Interrupt Inputs 15:08 utiny value As utiny endunion int_in_1 75 Interrupt Inputs 15:08 union int_in_0 74 Interrupt Inputs 07:00 {field (By field)} tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_in_0 74 Interrupt Inputs 07:00 utiny value As utiny endunion int_in_0 74 Interrupt Inputs 07:00 union int_mcp_5 7B MCP Interrupt 43:40 {field (By field)} tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:5 rsvd Reserved {} or int_mcp_5 7B MCP Interrupt 43:40 utiny value As utiny endunion int_mcp_5 7B MCP Interrupt 43:40 union int_in_5 7A Interrupt Inputs 43:40 {field (By field)} tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:5 rsvd Reserved {} or int_in_5 7A Interrupt Inputs 43:40 utiny value As utiny endunion int_in_5 7A Interrupt Inputs 43:40 union int_smi_pulsed 79 SMI Latched Pulse Interrupts {field (By field)} tbits:2 rsvd2 Reserved tbits:1 sdc_int SDC Latched Int. (Int=1) tbits:1 rsvd1 Reserved tbits:1 lcd_int LCD Latched Int. (Int=1) tbits:3 rsvd Reserved {} or int_smi_pulsed 79 SMI Latched Pulse Interrupts utiny value As utiny endunion int_smi_pulsed 79 SMI Latched Pulse Interrupts union int_in_4 78 Interrupt Inputs 39:32 {field (By field)} tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_in_4 78 Interrupt Inputs 39:32 utiny value As utiny endunion int_in_4 78 Interrupt Inputs 39:32 {rsvda[2] (7D-7F Reserved)} utiny value {} {rsvda[1] (7D-7F Reserved)} utiny value {} {rsvda[0] (7D-7F Reserved)} utiny value {} union ena_mcp_5 7C MCP Enables 43:40 {field (By field)} tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:5 rsvd Reserved {} or ena_mcp_5 7C MCP Enables 43:40 utiny value As utiny endunion ena_mcp_5 7C MCP Enables 43:40 {int_sci_3 (83 State Change Interrupt 31:24)} utiny value {} union int_sci_2 82 State Change Interrupt 23:16 {field (By field)} tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or int_sci_2 82 State Change Interrupt 23:16 utiny value As utiny endunion int_sci_2 82 State Change Interrupt 23:16 union int_sci_1 81 State Change Interrupt 15:08 {field (By field)} tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or int_sci_1 81 State Change Interrupt 15:08 utiny value As utiny endunion int_sci_1 81 State Change Interrupt 15:08 union int_sci_0 80 State Change Interrupt 07:00 {field (By field)} tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 other_dcok_l Other Controller DC OK Lo {M5} tbits:1 other_cable_l Other Controller cable present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or int_sci_0 80 State Change Interrupt 07:00 utiny value As utiny endunion int_sci_0 80 State Change Interrupt 07:00 union ena_sci_1 87 State Change Int Enable 15:08 {field (By field)} tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or ena_sci_1 87 State Change Int Enable 15:08 utiny value As utiny endunion ena_sci_1 87 State Change Int Enable 15:08 union ena_sci_0 86 State Change Int Enable 07:00 {field (By field)} tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 other_dcok_l Other Controller DC OK Lo {M5} tbits:1 other_cable_l Other Controller cable present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or ena_sci_0 86 State Change Int Enable 07:00 utiny value As utiny endunion ena_sci_0 86 State Change Int Enable 07:00 {rsvdb (85 Reserved)} utiny value {} union int_sci_4 84 State Change Interrupt 39:32 {field (By field)} tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or int_sci_4 84 State Change Interrupt 39:32 utiny value As utiny endunion int_sci_4 84 State Change Interrupt 39:32 {rsvdc (8B Reserved)} utiny value {} union ena_sci_4 8A State Change Int Enable 39:32 {field (By field)} tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or ena_sci_4 8A State Change Int Enable 39:32 utiny value As utiny endunion ena_sci_4 8A State Change Int Enable 39:32 {ena_sci_3 (89 State Change Int Enable 31:24)} utiny value {} union ena_sci_2 88 State Change Int Enable 23:16 {field (By field)} tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or ena_sci_2 88 State Change Int Enable 23:16 utiny value As utiny endunion ena_sci_2 88 State Change Int Enable 23:16 {sc_in_3 (8F State Change Inputs 31:24)} utiny value {} union sc_in_2 8E State Change Inputs 23:16 {field (By field)} tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or sc_in_2 8E State Change Inputs 23:16 utiny value As utiny endunion sc_in_2 8E State Change Inputs 23:16 union sc_in_1 8D State Change Inputs 15:08 {field (By field)} tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or sc_in_1 8D State Change Inputs 15:08 utiny value As utiny endunion sc_in_1 8D State Change Inputs 15:08 union sc_in_0 8C State Change Inputs 07:00 {field (By field)} tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 other_dcok_l Other Controller DC OK Lo {M5} tbits:1 other_cable_l Other Controller cable present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or sc_in_0 8C State Change Inputs 07:00 utiny value As utiny endunion sc_in_0 8C State Change Inputs 07:00 {rsvdd[0] (93-9F Reserved)} utiny value {} {batt_good_tp (92 Battery Good Trip Point)} utiny value {} {batt_lo_tp (91 Battery Low Trip Point)} utiny value {} {melt_down (90 Meltdown Temp.)} utiny value {} {rsvdd[4] (93-9F Reserved)} utiny value {} {rsvdd[3] (93-9F Reserved)} utiny value {} {rsvdd[2] (93-9F Reserved)} utiny value {} {rsvdd[1] (93-9F Reserved)} utiny value {} {rsvdd[8] (93-9F Reserved)} utiny value {} {rsvdd[7] (93-9F Reserved)} utiny value {} {rsvdd[6] (93-9F Reserved)} utiny value {} {rsvdd[5] (93-9F Reserved)} utiny value {} {rsvdd[12] (93-9F Reserved)} utiny value {} {rsvdd[11] (93-9F Reserved)} utiny value {} {rsvdd[10] (93-9F Reserved)} utiny value {} {rsvdd[9] (93-9F Reserved)} utiny value {} union reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 {field (By field)} tbits:1 dx2_a_l DX2 A Reset Lo {M21} tbits:1 dx2_b_l DX2 B Reset Lo {M20} tbits:1 dx2_c_l DX2 C Reset Lo {M19} tbits:1 dx2_d_l DX2 D Reset Lo {M18} tbits:1 sprite_l SPRITE Reset Lo {D1} tbits:1 uart_l UART Reset Lo {W17} tbits:1 enet1_l Ethernet 1 Reset Lo {Y17} tbits:1 enet2_l Ethernet 2 Reset Lo {AA18} {} or reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 utiny value As utiny endunion reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 union reprog_misc A2 GPO C: Reprog. & Misc. Ctrl {field (By field)} tbits:1 prog_sdc SDC reprogram mode (prog=1) {Y13} tbits:1 prog_can CAN reprogram mode (prog=1) {W13} tbits:1 prog_lcd LCD reprogram mode (prog=1) {V13} tbits:1 rpgm_clk Shared PIC reprogram clock {U13} tbits:1 rpgm_data Shared PIC reprogram data {U14} tbits:1 dx2_e_l DX2 E Reset L {V14} tbits:1 sdc_wdt SDC watchdog enable {Y5} tbits:1 rsvd R Reserved {G2} {} or reprog_misc A2 GPO C: Reprog. & Misc. Ctrl utiny value As utiny endunion reprog_misc A2 GPO C: Reprog. & Misc. Ctrl union sfp_laser A1 GPO B: SFP Laser Disable Ctrl {field (By field)} tbits:1 disable_0 SFP Laser 0 Disable (dis=1) {E18} tbits:1 disable_1 SFP Laser 1 Disable (dis=1) {F18} tbits:1 disable_2 SFP Laser 2 Disable (dis=1) {G22} tbits:1 disable_3 SFP Laser 3 Disable (dis=1) {G21} tbits:1 disable_4 SFP Laser 4 Disable (dis=1) {H22} tbits:1 disable_5 SFP Laser 5 Disable (dis=1) {H21} tbits:1 disable_6 SFP Laser 6 Disable (dis=1) {H20} tbits:1 disable_7 SFP Laser 7 Disable (dis=1) {H19} {} or sfp_laser A1 GPO B: SFP Laser Disable Ctrl utiny value As utiny endunion sfp_laser A1 GPO B: SFP Laser Disable Ctrl union pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals {field (By field)} tbits:1 bus0_stop_l Bus 0 STOP Lo {C22} tbits:1 bus0_trdy_l Bus 0 TRDY Lo {C21} tbits:1 bus0_devsel_l Bus 0 DEVSEL0 Lo {D22} tbits:1 bus0_req64_l Bus 0 REQ64 Lo {D21} tbits:2 rsvd1 Reserved tbits:1 pcix1_cfg_en PCIX1 Configuration Enable {E20} tbits:1 rsvd Reserved {} or pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals utiny value As utiny endunion pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals union gbic_act A7 GPI I: GBIC active {field (By field)} tbits:1 dx2a_f0 DX2A F0 ACTIVE {W1} tbits:1 dx2b_f0 DX2B F0 ACTIVE {W2} tbits:1 dx2c_f0 DX2C F0 ACTIVE {V3} tbits:1 dx2d_f0 DX2D F0 ACTIVE {V4} tbits:1 dx2e_f0 DX2E F0 ACTIVE {H2} tbits:1 temp0_ovr_thresh Temp Sensor 0 Over Threshold {AB19} tbits:1 temp1_ovr_thresh Temp Sensor 1 Over Threshold {AA17} tbits:1 temp2_ovr_thresh Temp Sensor 2 Over Threshold {Y18} {} or gbic_act A7 GPI I: GBIC active utiny value As utiny endunion gbic_act A7 GPI I: GBIC active union gbic_led A6 GPO G: GBIC LED Control {field (By field)} tbits:1 amb0_l R/W Amber 0 LED FLASH OFF Lo {E16} tbits:1 amb1_l R/W Amber 1 LED FLASH OFF Lo {E17} tbits:1 amb2_l R/W Amber 2 LED FLASH OFF Lo {A17} tbits:1 amb3_l R/W Amber 3 LED FLASH OFF Lo {B17} tbits:1 amb4_l R/W Amber 4 LED FLASH OFF Lo {C17} tbits:1 amb5_l R/W Amber 5 LED FLASH OFF Lo {D17} tbits:1 amb6_l R/W Amber 6 LED FLASH OFF Lo {A18} tbits:1 amb7_l R/W Amber 7 LED FLASH OFF Lo {B18} {} or gbic_led A6 GPO G: GBIC LED Control utiny value As utiny endunion gbic_led A6 GPO G: GBIC LED Control union gp_in A5 GPI F: Kills, msref_req, etc. {field (By field)} tbits:1 other_kill_2 Other Kill 2 {AB15} tbits:1 other_kill_1 Other Kill 1 {AA15} tbits:1 rsvd Reserved {AB17} tbits:1 spr_debug2 Sprite Debug Bit2 {B8} tbits:1 msref_req_l MSREF_REQ Sense Line (0=SelfRef){AB14} tbits:1 lcd_ready LCD Ready {L22} tbits:1 spr_debug3 Sprite Debug Bit3 {A8} tbits:1 rpgm_data_in Shared PIC reprogram data in {W14} {} or gp_in A5 GPI F: Kills, msref_req, etc. utiny value As utiny endunion gp_in A5 GPI F: Kills, msref_req, etc. union reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 {field (By field)} tbits:1 agent_l AGENT Reset Lo {AB5} tbits:1 sdc_l SDC Reset Lo {AA5} tbits:1 can_l CAN Reset Lo {Y6} tbits:1 lcd_l LCD Reset Lo {W6} tbits:1 toy_l TOY Reset Lo {V6} tbits:1 rsvd1 Reserved {V7} tbits:1 dpm_rdy PPC not accessing DPM {AB19} tbits:1 sdc_int_l glue to sdc interrupt (Int=0) {AB18} {} or reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 utiny value As utiny endunion reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 {rsvde[2] (A9-AE Reserved)} utiny value {} {rsvde[1] (A9-AE Reserved)} utiny value {} {rsvde[0] (A9-AE Reserved)} utiny value {} union gbic_led8 A8 GPO H: GBIC LED Control {field (By field)} tbits:1 amb8_l R/W Amber 8 LED FLASH OFF Lo {Y2} tbits:1 amb9_l R/W Amber 9 LED FLASH OFF Lo {Y1} tbits:1 disable_8 SFP Laser 8 Disable (dis=1) {U5} tbits:1 disable_9 SFP Laser 9 Disable (dis=1) {V5} tbits:4 unused unused {} or gbic_led8 A8 GPO H: GBIC LED Control utiny value As utiny endunion gbic_led8 A8 GPO H: GBIC LED Control union cache_ctrl AF Cache DIMM Control {field (By field)} tbits:1 msref_req_l R/W MSREF_REQ (0=Self-Refresh) {AB8} tbits:1 dimm0_rst_l R/W DIMM 0 Reset Lo {D10} tbits:1 dimm1_rst_l R/W DIMM 1 Reset Lo {C10} tbits:1 dimm2_rst_l R/W DIMM 2 Reset Lo {B10} tbits:1 dimm3_rst_l R/W DIMM 3 Reset Lo {A10} tbits:1 bbu_dcok_clear R/W BBU DIMM DC OK LATCH CLEAR {AA8} tbits:1 batt_on_l R/W Battery Turn ON Lo (to preset) {Y8} tbits:1 batt_off_l R/W Battery Turn OFF Lo (to clear) {W8} {} or cache_ctrl AF Cache DIMM Control utiny value As utiny endunion cache_ctrl AF Cache DIMM Control {rsvde[5] (A9-AE Reserved)} utiny value {} {rsvde[4] (A9-AE Reserved)} utiny value {} {rsvde[3] (A9-AE Reserved)} utiny value {} {ppc_data[2] (B1-B4 PPC command data)} utiny value {} {ppc_data[1] (B1-B4 PPC command data)} utiny value {} {ppc_data[0] (B1-B4 PPC command data)} utiny value {} {ppc_cmd (B0 PPC command to SDC)} utiny value {} {sdc_toy[1] (B6-BC sdc toy data)} utiny value {} {sdc_toy[0] (B6-BC sdc toy data)} utiny value {} {rsvb5 (B5 Reserved)} utiny value {} {ppc_data[3] (B1-B4 PPC command data)} utiny value {} {sdc_toy[5] (B6-BC sdc toy data)} utiny value {} {sdc_toy[4] (B6-BC sdc toy data)} utiny value {} {sdc_toy[3] (B6-BC sdc toy data)} utiny value {} {sdc_toy[2] (B6-BC sdc toy data)} utiny value {} union blower_led BF Blower LED Override Control {field (By field)} tbits:1 grn_blwr_a R/W Green Blower A LED tbits:1 amb_blwr_a R/W Amber Blower A LED tbits:1 grn_blwr_b R/W Green Blower B LED tbits:1 amb_blwr_b R/W Amber Blower B LED tbits:4 rsvd R Reserved {} or blower_led BF Blower LED Override Control utiny value As utiny endunion blower_led BF Blower LED Override Control union batt_led BE Battery LED Override Control {field (By field)} tbits:1 grn_brk0 R/W Green Brick 0 LED tbits:1 amb_brk0 R/W Amber Brick 0 LED tbits:1 grn_brk1 R/W Green Brick 1 LED tbits:1 amb_brk1 R/W Amber Brick 1 LED tbits:1 grn_brk2 R/W Green Brick 2 LED tbits:1 amb_brk2 R/W Amber Brick 2 LED tbits:1 grn_brk3 R/W Green Brick 3 LED tbits:1 amb_brk3 R/W Amber Brick 3 LED {} or batt_led BE Battery LED Override Control utiny value As utiny endunion batt_led BE Battery LED Override Control {rsvbd (BD Reserved)} utiny value {} {sdc_toy[6] (B6-BC sdc toy data)} utiny value {} {batt_mod_rev[3] (C0-C3 Battery Mod. Rev.)} utiny value {} {batt_mod_rev[2] (C0-C3 Battery Mod. Rev.)} utiny value {} {batt_mod_rev[1] (C0-C3 Battery Mod. Rev.)} utiny value {} {batt_mod_rev[0] (C0-C3 Battery Mod. Rev.)} utiny value {} {avg_temp (C7 Average Temperature)} utiny value {} {temp_sensor[2] (C4-C6 Temp. Sensors 1, 2, & 3)} utiny value {} {temp_sensor[1] (C4-C6 Temp. Sensors 1, 2, & 3)} utiny value {} {temp_sensor[0] (C4-C6 Temp. Sensors 1, 2, & 3)} utiny value {} {backup_time[1] (CA-CB backup time in x Watt-Sec)} utiny value {} {backup_time[0] (CA-CB backup time in x Watt-Sec)} utiny value {} {blower_rpm[1] (C8-C9 RPMs, Blowers 0 & 1)} utiny value {} {blower_rpm[0] (C8-C9 RPMs, Blowers 0 & 1)} utiny value {} {rsvcf (CF Spare Read Registers)} utiny value {} {volts_12v (CE 12V Level)} utiny value {} {sdc_major_rev (CD SDC Major Revision)} utiny value {} {sdc_minor_rev (CC SDC Minor Revision)} utiny value {} {brick_status[1] (D2-D5 brick interrupt status)} utiny value {} {brick_status[0] (D2-D5 brick interrupt status)} utiny value {} union sdc_int_cause1 D1 SDC interrupt cause1 {field (By field)} tbits:1 rsvd R/WA0 Reserved tbits:1 cmd_processed R/WA0 PPC command has been processed tbits:2 rsvd1 R/WA0 Reserved tbits:1 hut_changed R/WA0 Hold up time changed tbits:2 rsvd2 R/WA0 Reserved tbits:1 time_req R/WA0 SDC time request {} or sdc_int_cause1 D1 SDC interrupt cause1 utiny value As utiny endunion sdc_int_cause1 D1 SDC interrupt cause1 union sdc_int_cause0 D0 SDC interrupt cause0 {field (By field)} tbits:1 brick0 R/WA0 Brick 0 tbits:1 brick1 R/WA0 Brick 1 tbits:1 brick2 R/WA0 Brick 2 tbits:1 brick3 R/WA0 Brick 3 tbits:1 blower0 R/WA0 Blower 0 tbits:1 blower1 R/WA0 Blower 1 tbits:1 temperature R/WA0 Temperature tbits:1 rsvd R/WA0 Reserved {} or sdc_int_cause0 D0 SDC interrupt cause0 utiny value As utiny endunion sdc_int_cause0 D0 SDC interrupt cause0 {blower_status[1] (D6-D7 blower interrupt status)} utiny value {} {blower_status[0] (D6-D7 blower interrupt status)} utiny value {} {brick_status[3] (D2-D5 brick interrupt status)} utiny value {} {brick_status[2] (D2-D5 brick interrupt status)} utiny value {} {sdc_cmd_status (DB Battery Hold Up Time)} utiny value {} union fru_detect DA fru detect bits {field (By field)} tbits:1 brick0_present R tbits:1 brick1_present R tbits:1 brick2_present R tbits:1 brick3_present R tbits:1 blower0_present R tbits:1 blower1_present R tbits:2 rsvd R {} or fru_detect DA fru detect bits utiny value As utiny endunion fru_detect DA fru detect bits {sdc_status (D9 SDC codeload and brick test results)} utiny value {} {tmp_status (D8 temperature interrupt status)} utiny value {} {sdc_cmd_data[3] (DC-DF Reserved)} utiny value {} {sdc_cmd_data[2] (DC-DF Reserved)} utiny value {} {sdc_cmd_data[1] (DC-DF Reserved)} utiny value {} {sdc_cmd_data[0] (DC-DF Reserved)} utiny value {} {scratch[3] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[2] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[1] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[0] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[7] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[6] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[5] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[4] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[11] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[10] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[9] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[8] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[15] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[14] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[13] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {scratch[12] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)} utiny value {} {rsvd12[3] (F0-FD Reserved)} utiny value {} {rsvd12[2] (F0-FD Reserved)} utiny value {} {rsvd12[1] (F0-FD Reserved)} utiny value {} {rsvd12[0] (F0-FD Reserved)} utiny value {} {rsvd12[7] (F0-FD Reserved)} utiny value {} {rsvd12[6] (F0-FD Reserved)} utiny value {} {rsvd12[5] (F0-FD Reserved)} utiny value {} {rsvd12[4] (F0-FD Reserved)} utiny value {} {rsvd12[11] (F0-FD Reserved)} utiny value {} {rsvd12[10] (F0-FD Reserved)} utiny value {} {rsvd12[9] (F0-FD Reserved)} utiny value {} {rsvd12[8] (F0-FD Reserved)} utiny value {} {glue_major_rev (FF Glue Major Revision)} utiny value {} {glue_minor_rev (FE Glue Minor Revision)} utiny value {} {rsvd12[13] (F0-FD Reserved)} utiny value {} {rsvd12[12] (F0-FD Reserved)} utiny value {} {} do_not_display[768] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Glue CSR Registers {} {sprite (Sprite register save area)} union csr Sprite CSR Registers ulong[256] csra Sprite CSR Registers As Longwords or csr Sprite CSR Registers {csrfield (Sprite CSR Registers By Field)} union pc_cba 000 ppc chip base address {field (By field)} lbits:4 rev R Revision of Sprite lbits:5 rsvd R Reserved lbits:23 reg_base_addr R/W Register Base Address {} or pc_cba 000 ppc chip base address ulong value As longword endunion pc_cba 000 ppc chip base address union pc_m0_a 004 ppc to DDR memory window 0 description {field (By field)} lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m0_a 004 ppc to DDR memory window 0 description ulong value As longword endunion pc_m0_a 004 ppc to DDR memory window 0 description union pc_m1_a 008 ppc to DDR memory window 1 description {field (By field)} lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m1_a 008 ppc to DDR memory window 1 description ulong value As longword endunion pc_m1_a 008 ppc to DDR memory window 1 description union pc_m2_a 00c ppc to DDR memory window 2 description {field (By field)} lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m2_a 00c ppc to DDR memory window 2 description ulong value As longword endunion pc_m2_a 00c ppc to DDR memory window 2 description union pc_m3_a 010 ppc to DDR memory window 3 description {field (By field)} lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m3_a 010 ppc to DDR memory window 3 description ulong value As longword endunion pc_m3_a 010 ppc to DDR memory window 3 description union pc_p0_a 014 ppc to PCIX0 memory space window description {field (By field)} lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p0_a 014 ppc to PCIX0 memory space window description ulong value As longword endunion pc_p0_a 014 ppc to PCIX0 memory space window description {pc_p0_ua (018 ppc to PCIX0 upper address)} ulong value {} union pc_p1_a 01c ppc to PCIX1 memory space window description {field (By field)} lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p1_a 01c ppc to PCIX1 memory space window description ulong value As longword endunion pc_p1_a 01c ppc to PCIX1 memory space window description {pc_p1_ua (020 ppc to PCIX1 upper address)} ulong value {} union pc_io_a 024 ppc lower IO address description {field (By field)} lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd R Reserved lbits:30 base_addr R/W Sets bits 31:02 of base address {} or pc_io_a 024 ppc lower IO address description ulong value As longword endunion pc_io_a 024 ppc lower IO address description union pc_dls 028 mirror data has left sprite counter {field (By field)} lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or pc_dls 028 mirror data has left sprite counter ulong value As longword endunion pc_dls 028 mirror data has left sprite counter union pc_cfg_add 02c ppc configuration address phase description {field (By field)} lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd1 R Reserved lbits:6 Register R/W Register Number lbits:3 Function R/W Function Number lbits:5 device R/W Device Number lbits:8 bus R/W Bus Number lbits:8 rsvd R Reserved {} or pc_cfg_add 02c ppc configuration address phase description ulong value As longword endunion pc_cfg_add 02c ppc configuration address phase description union pc_wtt 030 ppc watchdog transfer timeout {field (By field)} lbits:19 wd_lo R Lower Bits of Count Value lbits:8 wd_hi R/W Programmable Extra Count Value lbits:4 rsvd R Reserved lbits:1 wd_ena R/W Watchdog Enable {} or pc_wtt 030 ppc watchdog transfer timeout ulong value As longword endunion pc_wtt 030 ppc watchdog transfer timeout union pc_tt 034 ppc transfer timeout {field (By field)} lbits:16 ttcounter R/W Transfer Timeout Counter lbits:16 rsvd R Reserved {} or pc_tt 034 ppc transfer timeout ulong value As longword endunion pc_tt 034 ppc transfer timeout union pc_csr 038 ppc control and status {field (By field)} lbits:1 esum_ddr_me R/CLL DDR Memory Error Summary lbits:1 esum_mir_me R/CLL Mirror Memory Error Summary lbits:1 esum_xor_dma R/CLL XOR-DMA Error Summary lbits:1 esum_que R/CLL Queue Error Summary lbits:1 esum_pcix1 R/CLL PCIX1 Error Summary lbits:1 esum_pcix0 R/CLL PCIX0 Error Summary lbits:1 err_pcixae R/W1C PCIX Access Error lbits:1 err_qrdpe R/W1C Queue Read Data Parity Error lbits:1 err_ppcttoe R/W1C PowerPC Transfer TimeOut Error lbits:1 err_ppcae R/W1C PowerPC Alignment Error lbits:1 err_ppcwdpe R/W1C PowerPC Write Data Parity Err lbits:1 err_ppcape R/W1C PowerPC Address Parity Error lbits:1 err_ppclee R/W1C PowerPC Last Entry Error lbits:1 err_ppc2pcixtoe R/W1C PowerPC-PCIX Transfer Timeout lbits:1 ena_pcixae R/W Enable PCIX Access Error lbits:1 ena_qrdpe R/W Enable Queue Rd Data Parity Er lbits:1 ena_ppcttoe R/W Enable PPC Transfer T.O. Error lbits:1 ena_ppcae R/W Enable PPC Alignment Error lbits:1 ena_ppcwdpe R/W Enable PPC Wrt Data Parity Err lbits:1 ena_ppcape R/W Enable PPC Address Parity Err lbits:1 ena_ppclee R/W Enable PPC Last Entry Error lbits:1 ena_ppc2pcixtoe R/W Enable PPC-PCIX Transfer T.O. lbits:1 ena_p_int1 R/W Ena PPC errs on INT1_L to Glue lbits:1 ena_p_int0 R/W Ena PPC errs on INT0_L to Glue lbits:1 sel_pcixae R/W Select P_INT(0/1)_L for pcixae lbits:1 sel_qrddpe R/W Select P_INT(0/1)_L for qrddpe lbits:1 sel_ppcttoe R/W Select P_INT(0/1)_L for ppcttoe lbits:1 sel_ppcae R/W Select P_INT(0/1)_L for ppcae lbits:1 sel_ppcwdpe R/W Select P_INT(0/1)_L for ppcwdpe lbits:1 sel_ppcape R/W Select P_INT(0/1)_L for ppcape lbits:1 sel_ppclee R/W Select P_INT(0/1)_L for ppclee lbits:1 sel_ppc2pcixtoe R/W Sel P_INT(0/1)_L 4 ppc2pcixtoe {} or pc_csr 038 ppc control and status ulong value As longword endunion pc_csr 038 ppc control and status union pc_err 03c ppc error status {field (By field)} lbits:1 hlt_mirror R/W Halt Mirror Block lbits:1 hlt_pcix1 R/W Halt PCIX 1 Block lbits:1 hlt_pcix0 R/W Halt PCIX 0 Block lbits:1 hlt_queue R/W Halt Queue Block lbits:1 hlt_ddrm R/W Halt DDR Memory Block lbits:1 hlt_dma R/W Halt DMA Block lbits:1 ena_tea R/W Enable Transfer Err Ack (TEA) lbits:1 rsvd1 R Reserved lbits:1 chk_even_ap R/W Set to Check Even Addr Parity lbits:1 chk_even_wrp R/W Set to Check Even WR Parity lbits:1 chk_even_rdp R/W Set to Check Even RD Parity lbits:1 gen_even_wrp R/W Set to Generate Even WR Parity lbits:1 gen_even_rdp R/W Set to Generate Even RD Parity lbits:1 ppc_mode R/W PowerPC Mode (1=7450 / 0=other) lbits:1 clr_hltd_mirror R/W Clear Mirror Halted Condition lbits:1 clr_hltd_pcix1 R/W Clear PCIX 1 Halted Condition lbits:1 clr_hltd_pcix0 R/W Clear PCIX 0 Halted Condition lbits:1 clr_hltd_ddq R/W Clear dma,ddrm,queue Halt Cond. lbits:8 rsvd R Reserved lbits:1 hltd_mirror R Mirror Halted lbits:1 hltd_pcix1 R PCIX 1 Halted lbits:1 hltd_pcix0 R PCIX 0 Halted lbits:1 hltd_queue R Queue Halted lbits:1 hltd_ddrm R DDR Memory Halted lbits:1 hltd_dma R DMA Halted {} or pc_err 03c ppc error status ulong value As longword endunion pc_err 03c ppc error status {pc_io_data (040 ppc IO data (not configured; do not read))} ulong value {} {pc_cfg_data (044 ppc configuration data)} ulong value {} {pc_addr (048 ppc error address)} ulong value {} {pc_rev (04c sprite3 hardware build revision)} ulong value {} union pc_gen 050 sprite3 gpio control {field (By field)} lbits:1 gbic_amb0_l R/W GBIC Amber LED0 Lo lbits:1 gbic_amb1_l R/W GBIC Amber LED1 Lo lbits:1 gbic_amb2_l R/W GBIC Amber LED2 Lo lbits:1 gbic_amb3_l R/W GBIC Amber LED3 Lo lbits:1 gbic_amb4_l R/W GBIC Amber LED4 Lo lbits:1 gbic_amb5_l R/W GBIC Amber LED5 Lo lbits:1 gbic_amb6_l R/W GBIC Amber LED6 Lo lbits:1 gbic_amb7_l R/W GBIC Amber LED7 Lo lbits:1 gbic_amb8_l R/W GBIC Amber LED8 Lo lbits:1 gbic_amb9_l R/W GBIC Amber LED9 Lo lbits:1 sfp_dis_0 R/W SFP Laser 0 Disable (dis=1) lbits:1 sfp_dis_1 R/W SFP Laser 1 Disable (dis=1) lbits:1 sfp_dis_2 R/W SFP Laser 2 Disable (dis=1) lbits:1 sfp_dis_3 R/W SFP Laser 3 Disable (dis=1) lbits:1 sfp_dis_4 R/W SFP Laser 4 Disable (dis=1) lbits:1 sfp_dis_5 R/W SFP Laser 5 Disable (dis=1) lbits:1 sfp_dis_6 R/W SFP Laser 6 Disable (dis=1) lbits:1 sfp_dis_7 R/W SFP Laser 7 Disable (dis=1) lbits:1 sfp_dis_8 R/W SFP Laser 8 Disable (dis=1) lbits:1 sfp_dis_9 R/W SFP Laser 9 Disable (dis=1) lbits:6 rsvd1 R/W Reserved 3.3V LVTTL lbits:6 rsvd R/W Reserved 2.5V CMOS {} or pc_gen 050 sprite3 gpio control ulong value As longword endunion pc_gen 050 sprite3 gpio control union pc_pll 054 sprite3 pll config {field (By field)} lbits:2 pll_phase_m_cnt R/W PLL phase shift for m counter lbits:2 pll_phase_c0 R/W PLL phase shift for clock C0 lbits:2 pll_phase_c1 R/W PLL phase shift for clock C1 lbits:2 pll_phase_c2 R/W PLL phase shift for clock C2 lbits:2 pll_phase_c3 R/W PLL phase shift for clock C3 lbits:2 pll_phase_c4 R/W PLL phase shift for clock C4 lbits:2 pll_phase_c5 R/W PLL phase shift for clock C5 lbits:1 rsvd1 R/W Reserved lbits:1 e_scan_done_ck R/W Enable scan done check lbits:7 pll_delay_parms R/W PLL delay parameters lbits:8 rsvd R/W Reserved lbits:1 pll_recon_w_e R/W PLL reconfig write enable {} or pc_pll 054 sprite3 pll config ulong value As longword endunion pc_pll 054 sprite3 pll config {rsvd2[0] (058 - 05c unused)} ulong value {} {rsvd2[1] (058 - 05c unused)} ulong value {} union p0_mem_0 060 pcix0 to DDR window 0 description {field (By field)} lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_0 060 pcix0 to DDR window 0 description ulong value As longword endunion p0_mem_0 060 pcix0 to DDR window 0 description union p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits ulong value As longword endunion p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits union p0_tra_0 068 pcix0 to DDR window 0 address translation value {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_0 068 pcix0 to DDR window 0 address translation value ulong value As longword endunion p0_tra_0 068 pcix0 to DDR window 0 address translation value union p0_mem_1 06c pcix0 to DDR window 1 description {field (By field)} lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_1 06c pcix0 to DDR window 1 description ulong value As longword endunion p0_mem_1 06c pcix0 to DDR window 1 description union p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits ulong value As longword endunion p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits union p0_tra_1 074 pcix0 to DDR window 1 address translation value {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_1 074 pcix0 to DDR window 1 address translation value ulong value As longword endunion p0_tra_1 074 pcix0 to DDR window 1 address translation value union p0_csr 078 pcix0 control and status {field (By field)} lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p0_csr 078 pcix0 control and status ulong value As longword endunion p0_csr 078 pcix0 control and status union p0_ecr 07c pcix0 error counters {field (By field)} lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or p0_ecr 07c pcix0 error counters ulong value As longword endunion p0_ecr 07c pcix0 error counters union p0_edr 080 pcix0 error disables {field (By field)} lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p0_edr 080 pcix0 error disables ulong value As longword endunion p0_edr 080 pcix0 error disables union p0_pcix_atr 084 pcix0 attributes {field (By field)} lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p0_pcix_atr 084 pcix0 attributes ulong value As longword endunion p0_pcix_atr 084 pcix0 attributes union p0_csr2 088 pcix0 control and status continued {field (By field previous Split-Response)} lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr) {} or p0_csr2 088 pcix0 control and status continued ulong value As longword endunion p0_csr2 088 pcix0 control and status continued {rsvd3[0] (08c - 09c unused)} ulong value {} {rsvd3[1] (08c - 09c unused)} ulong value {} {rsvd3[2] (08c - 09c unused)} ulong value {} {rsvd3[3] (08c - 09c unused)} ulong value {} {rsvd3[4] (08c - 09c unused)} ulong value {} union p1_mem_0 0a0 pcix1 to DDR window 0 description {field (By field)} lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_0 0a0 pcix1 to DDR window 0 description ulong value As longword endunion p1_mem_0 0a0 pcix1 to DDR window 0 description union p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits ulong value As longword endunion p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits union p1_tra_0 0a8 pcix1 to DDR window 0 address translation value {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_0 0a8 pcix1 to DDR window 0 address translation value ulong value As longword endunion p1_tra_0 0a8 pcix1 to DDR window 0 address translation value union p1_mem_1 0ac pcix1 to DDR window 1 description {field (By field)} lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_1 0ac pcix1 to DDR window 1 description ulong value As longword endunion p1_mem_1 0ac pcix1 to DDR window 1 description union p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits ulong value As longword endunion p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits union p1_tra_1 0b4 pcix1 to DDR window 1 address translation value {field (By field)} lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_1 0b4 pcix1 to DDR window 1 address translation value ulong value As longword endunion p1_tra_1 0b4 pcix1 to DDR window 1 address translation value union p1_csr 0b8 pcix1 control and status {field (By field)} lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p1_csr 0b8 pcix1 control and status ulong value As longword endunion p1_csr 0b8 pcix1 control and status union p1_ecr 0bc pcix1 error counters {field (By field)} lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or p1_ecr 0bc pcix1 error counters ulong value As longword endunion p1_ecr 0bc pcix1 error counters union p1_edr 0c0 pcix1 error disables {field (By field)} lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p1_edr 0c0 pcix1 error disables ulong value As longword endunion p1_edr 0c0 pcix1 error disables union p1_pcix_atr 0c4 pcix1 attributes {field (By field)} lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p1_pcix_atr 0c4 pcix1 attributes ulong value As longword endunion p1_pcix_atr 0c4 pcix1 attributes union p1_csr2 0c8 pcix1 control and status continued {field (By field previous Split-Response)} lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr) {} or p1_csr2 0c8 pcix1 control and status continued ulong value As longword endunion p1_csr2 0c8 pcix1 control and status continued {rsvd4[0] (0cc - 0dc unused)} ulong value {} {rsvd4[1] (0cc - 0dc unused)} ulong value {} {rsvd4[2] (0cc - 0dc unused)} ulong value {} {rsvd4[3] (0cc - 0dc unused)} ulong value {} {rsvd4[4] (0cc - 0dc unused)} ulong value {} union q_mir 0e0 mirror window description {field (By field)} lbits:12 size R/W Window size, 32MB -> 32GB lbits:9 rsvd R Reserved lbits:11 base_addr R/W Sets bits 35:25 of base address {} or q_mir 0e0 mirror window description ulong value As longword endunion q_mir 0e0 mirror window description union q_wsb 0e4 write sensitive base {field (By field)} lbits:1 ena_perf_int R/W Enable Performance Interrupt lbits:31 base_addr R/W Sets bits 35:5 of base address {} or q_wsb 0e4 write sensitive base ulong value As longword endunion q_wsb 0e4 write sensitive base union q_pint 0e8 performance interrupt {field (By field)} lbits:1 wsa000 R/W1C Write Sensitive Area 0x000 lbits:1 wsa020 R/W1C Write Sensitive Area 0x020 lbits:1 wsa040 R/W1C Write Sensitive Area 0x040 lbits:1 wsa060 R/W1C Write Sensitive Area 0x060 lbits:1 wsa080 R/W1C Write Sensitive Area 0x080 lbits:1 wsa0A0 R/W1C Write Sensitive Area 0x0A0 lbits:1 wsa0C0 R/W1C Write Sensitive Area 0x0C0 lbits:1 wsa0E0 R/W1C Write Sensitive Area 0x0E0 lbits:1 wsa100 R/W1C Write Sensitive Area 0x100 lbits:1 wsa120 R/W1C Write Sensitive Area 0x120 lbits:1 wsa140 R/W1C Write Sensitive Area 0x140 lbits:1 wsa160 R/W1C Write Sensitive Area 0x160 lbits:1 wsa180 R/W1C Write Sensitive Area 0x180 lbits:1 wsa1A0 R/W1C Write Sensitive Area 0x1A0 lbits:1 wsa1C0 R/W1C Write Sensitive Area 0x1C0 lbits:1 wsa1E0 R/W1C Write Sensitive Area 0x1E0 lbits:1 wsa200 R/W1C Write Sensitive Area 0x200 lbits:1 wsa220 R/W1C Write Sensitive Area 0x220 lbits:1 wsa240 R/W1C Write Sensitive Area 0x240 lbits:1 wsa260 R/W1C Write Sensitive Area 0x260 lbits:1 wsa280 R/W1C Write Sensitive Area 0x280 lbits:1 wsa2A0 R/W1C Write Sensitive Area 0x2A0 lbits:1 wsa2C0 R/W1C Write Sensitive Area 0x2C0 lbits:1 wsa2E0 R/W1C Write Sensitive Area 0x2E0 lbits:1 wsa300 R/W1C Write Sensitive Area 0x300 lbits:1 wsa320 R/W1C Write Sensitive Area 0x320 lbits:1 wsa340 R/W1C Write Sensitive Area 0x340 lbits:1 wrt_mir_dls R/W1C Write to Mirror Data has Left Sprite register lbits:1 dma_cmp_err R/W1C XOR-DMA Compare Error lbits:1 dma_complete R/W1C XOR-DMA Operation Completed lbits:1 int1 R/W1C INT_IN_1_L is asserted lbits:1 int0 R/W1C INT_IN_0_L is asserted {} or q_pint 0e8 performance interrupt ulong value As longword endunion q_pint 0e8 performance interrupt union q_csr 0ec queue control and status {field (By field)} lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK lbits:1 err_qdid R/W1C Queue Detected an Invalid Destination lbits:6 rsvd2 R Reserved lbits:1 ena_mir_bad R/W Enable mir_bad to error & halt lbits:1 ena_qdid R/W Enable qdid to error & halt lbits:6 rsvd1 R Reserved lbits:1 sel_mir_bad R/W Select P_INT(0/1)_L for mir_bad lbits:1 sel_qdid R/W Select P_INT(0/1)_L for qdid lbits:12 rsvd R Reserved lbits:1 gp2ppc_rd R/W Give priority to PowerPC Read transactions lbits:1 max_xfer_len R/W Max. Xfer Length 0=1K, 1=2K {} or q_csr 0ec queue control and status ulong value As longword endunion q_csr 0ec queue control and status union q_egen 0f0 error generation {field (By field)} lbits:3 pdf R/W Port Detector Field lbits:1 qrice R/W Queue Received an Invalid Command Entry lbits:1 tmpdb R/W Transaction Missing Proper Destination Bit lbits:1 twalanob R/W Transaction With a Low Actual Number of Bytes lbits:1 peifte R/W Parity Error in First Transaction Entry lbits:1 twnleb R/W Transaction With No Last-Entry Bit lbits:1 twnfeb R/W Transaction With No First-Entry Bit lbits:23 rsvd R Reserved {} or q_egen 0f0 error generation ulong value As longword endunion q_egen 0f0 error generation union q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 {field (By field)} lbits:2 ctrl1 R/W PCIX0 Arb Control lbits:2 state1 R PCIX0 Arb State lbits:2 ctrl0 R/W PCIX1 Arb Control lbits:2 state0 R PCIX1 Arb State lbits:16 rsvd2 R Reserved lbits:1 pcix1_init_stop_l R/W PCIX1 Initialization value for Stop_l lbits:1 pcix1_init_trdy_l R/W PCIX1 Initialization value for Trdy_l lbits:1 rsvd1 R Reserved lbits:1 pcix1_init_req64_l R/W PCIX1 Initialization value for Req64_l lbits:1 pcix0_init_stop_l R/W PCIX0 Initialization value for Stop_l lbits:1 pcix0_init_trdy_l R/W PCIX0 Initialization value for Trdy_l lbits:1 rsvd R Reserved lbits:1 pcix0_init_req64_l R/W PCIX0 Initialization value for Req64_l {} or q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 ulong value As longword endunion q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 {rsvd5[0] (0f8 - 0fc unused)} ulong value {} {rsvd5[1] (0f8 - 0fc unused)} ulong value {} union mir_csr 100 mirror control and status {field (By field)} lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or mir_csr 100 mirror control and status ulong value As longword endunion mir_csr 100 mirror control and status union mir_ecr 104 mirror error counters {field (By field)} lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or mir_ecr 104 mirror error counters ulong value As longword endunion mir_ecr 104 mirror error counters union mir_edr 108 mirror error disables {field (By field)} lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or mir_edr 108 mirror error disables ulong value As longword endunion mir_edr 108 mirror error disables union mir_pcix_atr 10c mirror pcix attributes {field (By field)} lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or mir_pcix_atr 10c mirror pcix attributes ulong value As longword endunion mir_pcix_atr 10c mirror pcix attributes union mir_dls 110 mirror data has left sprite counter {field (By field)} lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or mir_dls 110 mirror data has left sprite counter ulong value As longword endunion mir_dls 110 mirror data has left sprite counter union mir_csr2 114 mirror control and status continued {field (By field previous Split-Response)} lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr) {} or mir_csr2 114 mirror control and status continued ulong value As longword endunion mir_csr2 114 mirror control and status continued {rsvd6[0] (118 - 11c unused)} ulong value {} {rsvd6[1] (118 - 11c unused)} ulong value {} union x_cb 120 xor-dma command block base address {field (By field)} lbits:19 base_addr R/W Base Address of XOR-DMA SCDBs lbits:13 rsvd R Reserved {} or x_cb 120 xor-dma command block base address ulong value As longword endunion x_cb 120 xor-dma command block base address union x_pi 124 xor-dma producer index {field (By field)} lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_pi 124 xor-dma producer index ulong value As longword endunion x_pi 124 xor-dma producer index union x_ci 128 xor-dma consumer index {field (By field)} lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_ci 128 xor-dma consumer index ulong value As longword endunion x_ci 128 xor-dma consumer index union x_cc 12c xor-dma current command {field (By field)} lbits:4 rsvd R Reserved lbits:20 qword_cnt R Transfer Size in Qwords lbits:7 opcode R DMA Operation lbits:1 I R Interrupt on command completion {} or x_cc 12c xor-dma current command ulong value As longword endunion x_cc 12c xor-dma current command union x_usa 130 xor-dma upper source address {field (By field)} lbits:8 x_sa3 R Upper Source Address for x_sa3 lbits:8 x_sa2 R Upper Source Address for x_sa2 lbits:8 x_sa1 R Upper Source Address for x_sa1 lbits:8 x_sa0 R Upper Source Address for x_sa0 {} or x_usa 130 xor-dma upper source address ulong value As longword endunion x_usa 130 xor-dma upper source address union x_sa[0] 134 - 140 xor-dma source addresses 0-3 {field (By field)} lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[0] 134 - 140 xor-dma source addresses 0-3 ulong value As longword endunion x_sa[0] 134 - 140 xor-dma source addresses 0-3 union x_sa[1] 134 - 140 xor-dma source addresses 0-3 {field (By field)} lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[1] 134 - 140 xor-dma source addresses 0-3 ulong value As longword endunion x_sa[1] 134 - 140 xor-dma source addresses 0-3 union x_sa[2] 134 - 140 xor-dma source addresses 0-3 {field (By field)} lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[2] 134 - 140 xor-dma source addresses 0-3 ulong value As longword endunion x_sa[2] 134 - 140 xor-dma source addresses 0-3 union x_sa[3] 134 - 140 xor-dma source addresses 0-3 {field (By field)} lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[3] 134 - 140 xor-dma source addresses 0-3 ulong value As longword endunion x_sa[3] 134 - 140 xor-dma source addresses 0-3 union x_da 144 xor-dma destination address {field (By field)} lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_da 144 xor-dma destination address ulong value As longword endunion x_da 144 xor-dma destination address union x_uda 148 xor-dma upper destination address {field (By field)} lbits:24 rsvd R Reserved lbits:8 x_da R Upper Destination Addr for x_da {} or x_uda 148 xor-dma upper destination address ulong value As longword endunion x_uda 148 xor-dma upper destination address {x_spare (14c xor-dma spare)} ulong value {} {x_tmo (150 xor-dma transfer time out)} ulong value {} union x_csr 154 xor-dma control and status {field (By field ** in q_pint and W1C in q_pint))} lbits:1 cmp_err R Compare Error -- (duplicated lbits:1 err_count R/W1C Error, Count lbits:1 err_invop R/W1C Error, Invalid Opcode lbits:1 err_parity R/W1C Error, Parity lbits:1 err_efe R/W1C Error, End Frame Error lbits:1 err_sfe R/W1C Error, Start Frame Error lbits:1 err_toe R/W1C Error, TimeOut Error lbits:2 rsvd2 R Reserved lbits:1 sel_count R/W Select P_INT(0/1)_L for count lbits:1 sel_invop R/W Select P_INT(0/1)_L for invop lbits:1 sel_parity R/W Select P_INT(0/1)_L for parity lbits:1 sel_efe R/W Select P_INT(0/1)_L for efe lbits:1 sel_sfe R/W Select P_INT(0/1)_L for sfe lbits:1 sel_toe R/W Select P_INT(0/1)_L for toe lbits:2 rsvd1 R Reserved lbits:1 ena_count R/W Enable Count Errors lbits:1 ena_invop R/W Enable Invalid Opcode Errors lbits:1 ena_parity R/W Enable Parity Errors lbits:1 ena_efe R/W Enable End Frame Errors lbits:1 ena_sfe R/W Enable Start Frame Errors lbits:9 rsvd R Reserved lbits:1 ena_dma R/W Enables XOR-DMA operations {} or x_csr 154 xor-dma control and status ulong value As longword endunion x_csr 154 xor-dma control and status {rsvd7[0] (158 - 15c unused)} ulong value {} {rsvd7[1] (158 - 15c unused)} ulong value {} union m_tr 160 memory timing {field (By field)} lbits:1 Twtr R/W Timing, WR to RD cmd delay lbits:3 Trc R/W Timing, Activate to active cmd (same bnk) or Autoref to " " lbits:2 Trcd R/W Timing, Activate to RD or WR lbits:3 Tras R/W Timing, Activate to Precharge lbits:2 Trp R/W Timing, Precharge to Activate lbits:3 Trfc R/W Timing, Autoref cmd to Autoref or Activate cmd lbits:1 sdram_avail R Memory Unavailable When Cleared lbits:1 ecc_disable R/W Disable ECC Correction lbits:1 self_ref R/W Refresh Mode: 1=DIMMs,0=Sprite lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:14 rsvd R Reserved {} or m_tr 160 memory timing ulong value As longword endunion m_tr 160 memory timing union m_cfg 164 memory configuration {field (By field)} lbits:9 refrate R/W Refresh Rate Count lbits:1 refcnten R/W Enable Refresh Rate Counter lbits:1 init_rfsh R/W Issue Auto Refresh Commands lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:12 rfcntr R/W Refresh Cycles with init_rfsh lbits:1 ss_dimms R/W Single Sided DIMMs Installed lbits:1 scrub_en R/W Enable HW Scrubbing lbits:6 rsvd R Reserved {} or m_cfg 164 memory configuration ulong value As longword endunion m_cfg 164 memory configuration union m_mrs 168 mode register set {field (By field)} lbits:3 burst_length R Burst Length lbits:1 burst_type R Burst Type lbits:3 cas_latency R/W CAS Latency lbits:5 op_mode R/W Operating Mode lbits:20 rsvd R Reserved {} or m_mrs 168 mode register set ulong value As longword endunion m_mrs 168 mode register set union m_emrs 16c extended mode register set {field (By field)} lbits:1 sdram_dll_dis R/W Disable DLL in DDR SDRAMs lbits:1 ds R/W Drive Strength(1=Weak,0=Normal) lbits:1 qfc R/W QFC FET Isolation Control lbits:9 xemrs R/W Rsvd emrs JEDEC bits, set 0 lbits:20 rsvd R Reserved {} or m_emrs 16c extended mode register set ulong value As longword endunion m_emrs 16c extended mode register set union m_siz 170 DDR SRAM Size {field (By field)} lbits:3 ddr_size R/W DDR Memory Size Code lbits:2 installed_dimms R/W Number of DIMMs Installed lbits:1 scrub_test R/W Test bit for HW Scrub Circuit lbits:2 la_socket R/W Socket Number of L.A. (0->3) lbits:1 lap R/W Logic Analyzer Probe Installed lbits:23 rsvd R Reserved {} or m_siz 170 DDR SRAM Size ulong value As longword endunion m_siz 170 DDR SRAM Size union m_ese 174 ECC error status even {field (By field)} lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_ese 174 ECC error status even ulong value As longword endunion m_ese 174 ECC error status even union m_eso 178 ECC error status odd {field (By field)} lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_eso 178 ECC error status odd ulong value As longword endunion m_eso 178 ECC error status odd union m_eae 17c ECC address error even {field (By field)} lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eae 17c ECC address error even ulong value As longword endunion m_eae 17c ECC address error even union m_eao 180 ECC address error odd {field (By field)} lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eao 180 ECC address error odd ulong value As longword endunion m_eao 180 ECC address error odd union m_esc 184 ECC syndrome preset, correctable error counter {field (By field)} lbits:16 cec R/W Correctable Error Counter lbits:8 odd_egs R/W Odd Error Generating Syndrome lbits:8 even_egs R/W Even Error Generating Syndrome {} or m_esc 184 ECC syndrome preset, correctable error counter ulong value As longword endunion m_esc 184 ECC syndrome preset, correctable error counter union m_es 188 DDR error status {field (By field Halts chip - h)} lbits:1 err_ncb R/W1C New Command Bad h lbits:1 err_cdpe R/W1C Cmd/Data Parity Error h lbits:1 err_ude R/CLL Uncorrectable Data Error h lbits:1 err_bwde R/W1C Bad Write Data Error h lbits:1 err_cde R/CLL Correctable Data Error lbits:3 rsvd2 R Reserved lbits:1 sel_ncb R/W Select P_INT(0/1)_L for ncb's lbits:1 sel_cdpe R/W Select P_INT(0/1)_L for cdpe's lbits:1 sel_ude R/W Select P_INT(0/1)_L for ude's lbits:1 sel_bwde R/W Select P_INT(0/1)_L for bwde's lbits:1 sel_cde R/W Select P_INT(0/1)_L for cde's lbits:3 rsvd1 R Reserved lbits:1 dis_ncb R/W Disable New Command Bad lbits:1 dis_cdpe R/W Disable Cmd/Data Parity Error lbits:1 dis_ude R/W Disable Uncorrectable Data Err lbits:1 dis_bwde R/W Disable Bad Write Data Error lbits:1 dis_cde R/W Disable Correctable Data Error lbits:11 rsvd R Reserved {} or m_es 188 DDR error status ulong value As longword endunion m_es 188 DDR error status union m_sta 18c scrub test address {field (By field)} lbits:32 start_addr_35_5 R/W Scrub Test Address, bits 35:5 {} or m_sta 18c scrub test address ulong value As longword endunion m_sta 18c scrub test address {} do_not_display[624] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Sprite CSR Registers {} {quartcr[0] (SC28L194 Quad UART Control Registers a, b, c, d)} union bcrbrk (Offset 0x03) R/W Bid Control, Break Change {field (By field)} tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change union iopcr (Offset 0x02) R/W I/O Port Configuration Register {field (By field)} tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register union mr1 (Offset 0x01) R/W Mode Register 1 {field (By field)} tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 union mr0 (Offset 0x00) R/W Mode Register 0 {field (By field)} tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 union bcra (Offset 0x07) R/W Bid Control, Address recognition {field (By field)} tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {field (By field)} tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {rsvd1 ((Offset 0x05) NA Reserved)} utiny value {} union bcrcos (Offset 0x04) R/W Bid Control, Change of State {field (By field)} tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) {field (By field)} tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) union arcr (Offset 0x0A) R/W Address Recognition Character {field (By field)} tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character union xoffcr (Offset 0x09) R/W Xoff Character Register {field (By field)} tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition {} or xoffcr (Offset 0x09) R/W Xoff Character Register utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register union xoncr (Offset 0x08) R/W Xon Character Register {field (By field)} tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition {} or xoncr (Offset 0x08) R/W Xon Character Register utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) {field (By field)} tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {field (By field)} tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} {quartcr[1] (SC28L194 Quad UART Control Registers a, b, c, d)} union bcrbrk (Offset 0x03) R/W Bid Control, Break Change {field (By field)} tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change union iopcr (Offset 0x02) R/W I/O Port Configuration Register {field (By field)} tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register union mr1 (Offset 0x01) R/W Mode Register 1 {field (By field)} tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 union mr0 (Offset 0x00) R/W Mode Register 0 {field (By field)} tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 union bcra (Offset 0x07) R/W Bid Control, Address recognition {field (By field)} tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {field (By field)} tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {rsvd1 ((Offset 0x05) NA Reserved)} utiny value {} union bcrcos (Offset 0x04) R/W Bid Control, Change of State {field (By field)} tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) {field (By field)} tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) union arcr (Offset 0x0A) R/W Address Recognition Character {field (By field)} tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character union xoffcr (Offset 0x09) R/W Xoff Character Register {field (By field)} tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition {} or xoffcr (Offset 0x09) R/W Xoff Character Register utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register union xoncr (Offset 0x08) R/W Xon Character Register {field (By field)} tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition {} or xoncr (Offset 0x08) R/W Xon Character Register utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) {field (By field)} tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {field (By field)} tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} {quartcr[2] (SC28L194 Quad UART Control Registers a, b, c, d)} union bcrbrk (Offset 0x03) R/W Bid Control, Break Change {field (By field)} tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change union iopcr (Offset 0x02) R/W I/O Port Configuration Register {field (By field)} tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register union mr1 (Offset 0x01) R/W Mode Register 1 {field (By field)} tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 union mr0 (Offset 0x00) R/W Mode Register 0 {field (By field)} tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 union bcra (Offset 0x07) R/W Bid Control, Address recognition {field (By field)} tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {field (By field)} tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {rsvd1 ((Offset 0x05) NA Reserved)} utiny value {} union bcrcos (Offset 0x04) R/W Bid Control, Change of State {field (By field)} tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) {field (By field)} tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) union arcr (Offset 0x0A) R/W Address Recognition Character {field (By field)} tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character union xoffcr (Offset 0x09) R/W Xoff Character Register {field (By field)} tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition {} or xoffcr (Offset 0x09) R/W Xoff Character Register utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register union xoncr (Offset 0x08) R/W Xon Character Register {field (By field)} tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition {} or xoncr (Offset 0x08) R/W Xon Character Register utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) {field (By field)} tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {field (By field)} tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} {quartcr[3] (SC28L194 Quad UART Control Registers a, b, c, d)} union bcrbrk (Offset 0x03) R/W Bid Control, Break Change {field (By field)} tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change union iopcr (Offset 0x02) R/W I/O Port Configuration Register {field (By field)} tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register union mr1 (Offset 0x01) R/W Mode Register 1 {field (By field)} tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 union mr0 (Offset 0x00) R/W Mode Register 0 {field (By field)} tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 union bcra (Offset 0x07) R/W Bid Control, Address recognition {field (By field)} tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {field (By field)} tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff {rsvd1 ((Offset 0x05) NA Reserved)} utiny value {} union bcrcos (Offset 0x04) R/W Bid Control, Change of State {field (By field)} tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) {field (By field)} tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) union arcr (Offset 0x0A) R/W Address Recognition Character {field (By field)} tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character union xoffcr (Offset 0x09) R/W Xoff Character Register {field (By field)} tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition {} or xoffcr (Offset 0x09) R/W Xoff Character Register utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register union xoncr (Offset 0x08) R/W Xon Character Register {field (By field)} tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition {} or xoncr (Offset 0x08) R/W Xon Character Register utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) {field (By field)} tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) {field (By field)} tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {field (By field)} tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} {quartdr[0] (SC28L194 Quad UART Data Registers a, b, c, d)} union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union rxfifo (Offset 0x83) R Receiver FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union txfifo (Offset 0x83) W Transmitter FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union isr (Offset 0x82) R Interrupt Status Register {field (By field)} tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union imr (Offset 0x82) W Interrupt Mask Register {field (By field)} tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable {} or imr (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union sr (Offset 0x81) R Channel Status Register {field (By field)} tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union cr (Offset 0x81) W Command Register {field (By field)} tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union mr2 (Offset 0x80) R/W Mode Register 2 {field (By field)} tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) {field (By field)} tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) {field (By field)} tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register {field (By field)} tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register union iopior (Offset 0x85) R/W I/O Port Interrupt and Output {field (By field)} tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union ipr (Offset 0x84) R Input Port Register {field (By field)} tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) {field (By field)} tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {field (By field)} tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {rsvd3 ((Offset 0x8A) NA Reserved)} utiny value {} {rsvd2 ((Offset 0x89) NA Reserved)} utiny value {} {rsvd1 ((Offset 0x88) NA Reserved)} utiny value {} union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) {field (By field)} tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) {field (By field)} tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) {field (By field)} tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) {field (By field)} tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {field (By field)} tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {} {quartdr[1] (SC28L194 Quad UART Data Registers a, b, c, d)} union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union rxfifo (Offset 0x83) R Receiver FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union txfifo (Offset 0x83) W Transmitter FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union isr (Offset 0x82) R Interrupt Status Register {field (By field)} tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union imr (Offset 0x82) W Interrupt Mask Register {field (By field)} tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable {} or imr (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union sr (Offset 0x81) R Channel Status Register {field (By field)} tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union cr (Offset 0x81) W Command Register {field (By field)} tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union mr2 (Offset 0x80) R/W Mode Register 2 {field (By field)} tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) {field (By field)} tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) {field (By field)} tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register {field (By field)} tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register union iopior (Offset 0x85) R/W I/O Port Interrupt and Output {field (By field)} tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union ipr (Offset 0x84) R Input Port Register {field (By field)} tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) {field (By field)} tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {field (By field)} tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {rsvd3 ((Offset 0x8A) NA Reserved)} utiny value {} {rsvd2 ((Offset 0x89) NA Reserved)} utiny value {} {rsvd1 ((Offset 0x88) NA Reserved)} utiny value {} union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) {field (By field)} tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) {field (By field)} tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) {field (By field)} tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) {field (By field)} tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {field (By field)} tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {} {quartdr[2] (SC28L194 Quad UART Data Registers a, b, c, d)} union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union rxfifo (Offset 0x83) R Receiver FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union txfifo (Offset 0x83) W Transmitter FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union isr (Offset 0x82) R Interrupt Status Register {field (By field)} tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union imr (Offset 0x82) W Interrupt Mask Register {field (By field)} tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable {} or imr (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union sr (Offset 0x81) R Channel Status Register {field (By field)} tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union cr (Offset 0x81) W Command Register {field (By field)} tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union mr2 (Offset 0x80) R/W Mode Register 2 {field (By field)} tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) {field (By field)} tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) {field (By field)} tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register {field (By field)} tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register union iopior (Offset 0x85) R/W I/O Port Interrupt and Output {field (By field)} tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union ipr (Offset 0x84) R Input Port Register {field (By field)} tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) {field (By field)} tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {field (By field)} tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {rsvd3 ((Offset 0x8A) NA Reserved)} utiny value {} {rsvd2 ((Offset 0x89) NA Reserved)} utiny value {} {rsvd1 ((Offset 0x88) NA Reserved)} utiny value {} union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) {field (By field)} tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) {field (By field)} tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) {field (By field)} tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) {field (By field)} tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {field (By field)} tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {} {quartdr[3] (SC28L194 Quad UART Data Registers a, b, c, d)} union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union rxfifo (Offset 0x83) R Receiver FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union txfifo (Offset 0x83) W Transmitter FIFO Register {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union isr (Offset 0x82) R Interrupt Status Register {field (By field)} tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union imr (Offset 0x82) W Interrupt Mask Register {field (By field)} tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable {} or imr (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union sr (Offset 0x81) R Channel Status Register {field (By field)} tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union cr (Offset 0x81) W Command Register {field (By field)} tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register union mr2 (Offset 0x80) R/W Mode Register 2 {field (By field)} tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) {field (By field)} tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) {field (By field)} tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register {field (By field)} tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register union iopior (Offset 0x85) R/W I/O Port Interrupt and Output {field (By field)} tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union ipr (Offset 0x84) R Input Port Register {field (By field)} tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) {field (By field)} tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {field (By field)} tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) {rsvd3 ((Offset 0x8A) NA Reserved)} utiny value {} {rsvd2 ((Offset 0x89) NA Reserved)} utiny value {} {rsvd1 ((Offset 0x88) NA Reserved)} utiny value {} union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) {field (By field)} tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) {field (By field)} tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) {field (By field)} tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) {field (By field)} tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) {field (By field)} tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) {field (By field)} tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) {field (By field)} tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) {field (By field)} tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {field (By field)} tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) {} {tachyon (Tachyon DX2+ register save area)} union portcorr[0] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[0] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[0] Port Correlation union portcorr[1] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[1] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[1] Port Correlation union portcorr[2] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[2] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[2] Port Correlation union portcorr[3] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[3] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[3] Port Correlation union portcorr[4] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[4] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[4] Port Correlation union portcorr[5] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[5] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[5] Port Correlation union portcorr[6] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[6] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[6] Port Correlation union portcorr[7] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[7] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[7] Port Correlation union portcorr[8] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[8] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[8] Port Correlation union portcorr[9] Port Correlation ulong portcorra Port Correlation As Longword or portcorr[9] Port Correlation {portcorr (Port Correlation By Field)} utiny real_port Real hardware port number utiny port_type Port type ushort reserved Reserved {} endunion portcorr[9] Port Correlation union csr[0] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[0] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[0] Tachyon DX2+ CSR Registers union csr[1] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[1] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[1] Tachyon DX2+ CSR Registers union csr[2] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[2] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[2] Tachyon DX2+ CSR Registers union csr[3] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[3] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[3] Tachyon DX2+ CSR Registers union csr[4] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[4] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[4] Tachyon DX2+ CSR Registers union csr[5] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[5] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[5] Tachyon DX2+ CSR Registers union csr[6] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[6] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[6] Tachyon DX2+ CSR Registers union csr[7] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[7] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[7] Tachyon DX2+ CSR Registers union csr[8] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[8] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[8] Tachyon DX2+ CSR Registers union csr[9] Tachyon DX2+ CSR Registers ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[9] Tachyon DX2+ CSR Registers {csr (Tachyon DX2+ CSR Registers By Field)} union erq_base (Offset 000) ERQ Base (write only) {field (By field)} lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) union erq_len (Offset 004) ERQ Length (write only) {field (By field)} lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) union erq_prod (Offset 008) ERQ Producer Index {field (By field)} lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) {field (By field)} lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) union erq_cons (Offset 010) ERQ Consumer Index {field (By field)} lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index {rsvd1[0] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[1] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[2] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[3] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[4] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[5] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[6] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[7] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[8] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[9] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[10] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[11] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[12] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[13] ((Offset 014-04F) Reserved)} ulong value {} {rsvd1[14] ((Offset 014-04F) Reserved)} ulong value {} union sfq_base (Offset 050) SFQ Base (write only) {field (By field)} lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) union sfq_len (Offset 054) SFQ Length (write only) {field (By field)} lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) union sfq_cons (Offset 058) SFQ Consumer Index {field (By field)} lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index {rsvd2[0] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[1] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[2] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[3] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[4] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[5] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[6] ((Offset 05C-07B) Reserved)} ulong value {} {rsvd2[7] ((Offset 05C-07B) Reserved)} ulong value {} union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) {field (By field)} lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) union imq_base (Offset 080) IMQ Base (write only) {field (By field)} lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) union imq_len (Offset 084) IMQ Length (write only) {field (By field)} lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) union imq_cons (Offset 088) IMQ Consumer Index {field (By field)} lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {field (By field)} lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) {rsvd3[0] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[1] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[2] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[3] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[4] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[5] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[6] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[7] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[8] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[9] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[10] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[11] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[12] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[13] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[14] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[15] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[16] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[17] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[18] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[19] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[20] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[21] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[22] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[23] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[24] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[25] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[26] ((Offset 090-0FC) Reserved)} ulong value {} {rsvd3[27] ((Offset 090-0FC) Reserved)} ulong value {} union fm_config3 (Offset 100) Frame Manager Configuration 3 {field (By field)} lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) {rsvd3a[0] ((Offset 108-10f) Reserved)} ulong value {} {rsvd3a[1] ((Offset 108-10f) Reserved)} ulong value {} union sfp_cmd_status (Offset 110) SFP command and status {field (No description available)} lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status ulong value endunion sfp_cmd_status (Offset 110) SFP command and status union sfp_data (Offset 114) SFP data {field (By field)} lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data ulong value As longword endunion sfp_data (Offset 114) SFP data union fm_config4 (Offset 118) Frame Manager Configuration 4 {field (By field)} lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 union fm_config5 (Offset 11C) Frame Manager Configuration 5 {field (By field)} lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 {rsvd3b[0] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[1] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[2] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[3] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[4] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[5] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[6] ((Offset 120-13F) Reserved)} ulong value {} {rsvd3b[7] ((Offset 120-13F) Reserved)} ulong value {} union sest_base (Offset 140) SEST Base (write only) {field (By field)} lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) union sest_len (Offset 144) SEST Length (write only) {field (By field)} lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) {rsvd4 ((Offset 148) Reserved)} ulong value {} union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail {field (By field)} lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail union prog_addr (Offset 150) Programmable Address register {field (By field)} lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register ulong value As longword endunion prog_addr (Offset 150) Programmable Address register union prog_data (Offset 154) programmable data register {field (By field)} lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register ulong value As longword endunion prog_data (Offset 154) programmable data register {rsvd5[0] ((Offset 158-15F) Reserved)} ulong value {} {rsvd5[1] ((Offset 158-15F) Reserved)} ulong value {} union int_mess_adr (Offset 160) Interrupt Message Address (write only) {field (By field)} lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) union int_mess_value (Offset 164) Interrupt Message Value (write only) {field (By field)} lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) {field (By field)} lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) union my_id (Offset 16C) My ID {field (By field)} lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID ulong value As longword endunion my_id (Offset 16C) My ID union gpio (Offset 170) General Purpose I/O {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O ulong value As longword endunion gpio (Offset 170) General Purpose I/O {rsvd6a ((Offset 174-177) Reserved)} ulong value {} union edc_config (Offset 178) EDC Configuration Register {field (By field)} lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register union dx4_config3 (Offset 17C) DX4 Configuration Register 3 {field (By field)} lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 {field (By field)} lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 union tach_config (Offset 184) Tachyon DX2+ Configuration 1 {field (By field)} lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 union tach_control (Offset 188) Tachyon DX2+ Control {field (By field)} lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control union tach_status (Offset 18C) Tachyon DX2+ Status {field (By field)} lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status {rsvd7 ((Offset 190) Reserved)} ulong value {} union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) {field (By field)} lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 {field (By field)} lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 {field (By field)} lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) {field (By field)} lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) union up_data_addr (Offset 1A8) Upper Data Address (write only) {field (By field)} lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) {field (By field)} lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 {field (By field)} lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 {field (By field)} lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 {field (By field)} lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 {field (By field)} lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 union fm_config1 (Offset 1C0) Frame Manager Configuration 1 {field (By field)} lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 union fm_control (Offset 1C4) Frame Manager Control {field (By field)} lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control union fm_status (Offset 1C8) Frame Manager Status {field (By field)} lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 {field (By field)} lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 {field (By field)} lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 {field (By field)} lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 {field (By field)} lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer {field (By field)} lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low {field (By field)} lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA {field (By field)} lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA union fm_primitive (Offset 1EC) Frame Manager Primitive {field (By field)} lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 {field (By field)} lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 union fm_config2 (Offset 1F4) Frame Manager Configuration 2 {field (By field)} lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED {field (By field)} {pci_rsvd1F8 ((Offset 1F8) Reserved)} utiny value {} {pci_rsvd1F9 ((Offset 1F9) Reserved)} utiny value {} union romctr (Offset 1FA) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control union mctr (Offset 1FB) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {field (By field)} union softrst (Offset 1FC) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control union intpend (Offset 1FD) PCI Interrupt Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending union inten (Offset 1FE) PCI Interrupt Enable {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable union intstat (Offset 1FF) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[9] Tachyon DX2+ CSR Registers union ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low union ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords or ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} union ncfglo_fcr (Offset 0x200) Function Control Register {field (By field)} lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register union ncfglo_fsr (Offset 0x204) Function Status Register {field (By field)} lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register union ncfglo_escr (Offset 0x208) Error Split Completion Register {field (By field)} lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low union pcicfg[0] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[0] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[0] Tachyon DX2+ PCI Configuration Registers union pcicfg[1] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[1] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[1] Tachyon DX2+ PCI Configuration Registers union pcicfg[2] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[2] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[2] Tachyon DX2+ PCI Configuration Registers union pcicfg[3] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[3] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[3] Tachyon DX2+ PCI Configuration Registers union pcicfg[4] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[4] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[4] Tachyon DX2+ PCI Configuration Registers union pcicfg[5] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[5] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[5] Tachyon DX2+ PCI Configuration Registers union pcicfg[6] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[6] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[6] Tachyon DX2+ PCI Configuration Registers union pcicfg[7] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[7] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[7] Tachyon DX2+ PCI Configuration Registers union pcicfg[8] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[8] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[8] Tachyon DX2+ PCI Configuration Registers union pcicfg[9] Tachyon DX2+ PCI Configuration Registers ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[9] Tachyon DX2+ PCI Configuration Registers {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID {field (By field)} union pci_vendor_id (Offset 00) PCI Vendor ID {field (By field)} bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID union pci_device_id (Offset 02) PCI Device ID {field (By field)} bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS {field (By field)} union pci_cmd (Offset 04) PCI Command {field (By field)} bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command ushort value As word endunion pci_cmd (Offset 04) PCI Command union pci_status (Offset 06) PCI Status {field (By field)} bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS {field (By field)} union pci_revid (Offset 08) PCI Revision {field (By field)} tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision utiny value As byte endunion pci_revid (Offset 08) PCI Revision union pci_class (Offset 09) PCI Class {field (By field)} tbits:8 baseclcode Base Class Code tbits:8 subclcode Subclass Code tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {field (By field)} union pci_clsize (Offset 0C) PCI Cache Line Size {field (By field)} tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size union pci_lattmr (Offset 0D) PCI Latency Timer {field (By field)} tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer union pci_hdrtype (Offset 0E) PCI Header Type {field (By field)} tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type {pci_rsvd0f ((Offset 0F) Reserved (BIST))} utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} ulong value {} {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} ulong value {} union pci_iobasel (Offset 18) PCI Lower I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address {field (By field)} lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address union pci_membasel (Offset 20) PCI Lower Memory Address Base {field (By field)} lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base union pci_membaseu (Offset 24) PCI Upper Memory Address Base {field (By field)} lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base {pci_rsrvd28_2b ((Offset 28) Reserved)} ulong value {} union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID {field (By field)} union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID {field (By field)} bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID union pci_subsys_id (Offset 2E) PCI Subsystem ID {field (By field)} bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID union pci_rombase (Offset 30) PCI ROM Base Address {field (By field)} lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {field (By field)} union pci_cap_ptr (Offset 34) PCI Capabilities Pointer {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer {pci_rsvd35 ((Offset 35) Reserved)} utiny value {} {pci_rsvd36_37 ((Offset 36) Reserved)} ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED {pci_rsvd38_3b ((Offset 38) Reserved)} ulong value {} union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED {field (By field)} union pci_int_line (Offset 3C) PCI Interrupt Line {field (By field)} tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line union pci_int_pin (Offset 3D) PCI Interrupt Pin {field (By field)} tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin union pci_min_gnt (Offset 3E) PCI Minimum Grant {field (By field)} tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant {reserved ((Offset 3F) Reserved)} utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR {field (By field)} {pci_rsvd40 ((Offset 40) Reserved)} utiny value {} {pci_rsvd41 ((Offset 41) Reserved)} utiny value {} union pci_romctr (Offset 42) PCI ROM Control {field (By field)} tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control union pci_mctr (Offset 43) PCI Master Control {field (By field)} tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {field (By field)} union pci_softrst (Offset 44) PCI Interface Reset Control {field (By field)} tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control union pci_intpend (Offset 45) PCI Interrupt {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt union pci_inten (Offset 46) PCI Interrupt Enable Pending {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending union pci_instat (Offset 47) PCI Interrupt Status {field (By field)} tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT {pci_rsvd48_4b ((Offset 48) Reserved)} ulong value {} {pci_rsvd4c_4f ((Offset 4C) Reserved)} ulong value {} union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC {field (By field)} union pci_cap_id (Offset 50) PCI Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities union pci_pmc (Offset 52) PCI Power Management Capabilities {field (By field)} bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC union pci_pmcs (Offset 54) PCI Power Management Control and Status {field (By field)} lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status union pci_par (Offset 58) PCI Programmable Address Register {field (By field)} lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register union pci_dar (Offset 5C) PCI Programmable Data Register {field (By field)} lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register {pci_rsvd60_6f ((Offset 60) Reserved)} ulong value {} union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC {field (By field)} union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability union pci_mc (Offset 66) PCI Message Control Register {field (By field)} bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC union pci_ma (Offset 68) PCI Message Address {field (By field)} lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address ulong value As longword endunion pci_ma (Offset 68) PCI Message Address union pci_mua (Offset 6C) PCI Message Upper Address {field (By field)} lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address union pci_md (Offset 70) PCI Message Data {field (By field)} lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data ulong value As longword endunion pci_md (Offset 70) PCI Message Data union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD {field (By field)} union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier {field (By field)} tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier union pci_x_next_cap (Offset 75) PCI Next Capability Register {field (By field)} tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register union pci_x_cmd (Offset 76) PCI-X Command Register {field (By field)} bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD union pci_x_s (Offset 78) PCI-X Status Register {field (By field)} lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[9] Tachyon DX2+ PCI Configuration Registers union ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High union ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords or ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register {field (By field)} lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register {field (By field)} lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register union ncfghi_gcr (Offset 0x40C) Global Control Register {field (By field)} lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register union ncfghi_gsr (Offset 0x410) Global Status Register {field (By field)} lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {field (By field)} union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {field (By field)} bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} ulong value {} {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} ulong value {} union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low {field (By field)} lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {field (By field)} lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High union gbic_sid[0] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[0] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[0] GBIC Small Form Factor Serial ID data union gbic_sid[1] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[1] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[1] GBIC Small Form Factor Serial ID data union gbic_sid[2] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[2] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[2] GBIC Small Form Factor Serial ID data union gbic_sid[3] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[3] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[3] GBIC Small Form Factor Serial ID data union gbic_sid[4] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[4] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[4] GBIC Small Form Factor Serial ID data union gbic_sid[5] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[5] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[5] GBIC Small Form Factor Serial ID data union gbic_sid[6] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[6] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[6] GBIC Small Form Factor Serial ID data union gbic_sid[7] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[7] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[7] GBIC Small Form Factor Serial ID data union gbic_sid[8] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[8] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[8] GBIC Small Form Factor Serial ID data union gbic_sid[9] GBIC Small Form Factor Serial ID data ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[9] GBIC Small Form Factor Serial ID data {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} {base_id (Base ID Fields (Addresses 0-63))} utiny transceiver0 Transceiver code 0 utiny connector Connector type utiny ext_identifier Extended identifier utiny identifier Identifier, transceiver type utiny transceiver4 Transceiver code 4 utiny transceiver3 Transceiver code 3 utiny transceiver2 Transceiver code 2 utiny transceiver1 Transceiver code 1 utiny encoding Encoding utiny transceiver7 Transceiver code 7 utiny transceiver6 Transceiver code 6 utiny transceiver5 Transceiver code 5 utiny distance_9u_100m 9u, Distance (100m units) utiny distance_9u_km 9u, Distance (1000m units) utiny reserved Reserved utiny br_nom Baud rate, nominal utiny reserved1 Reserved utiny distance_cu CU, Distance (1m units) utiny distance_60u_10m 60u, Distance (10m units) utiny distance_50u_10m 50u, Distance (10m units) utiny[16] vendor_name Vendor name utiny[3] vendor_oui Vendor OUI utiny reserved2 Reserved utiny[16] vendor_pn Vendor part number utiny[4] vendor_rev Vendor revision utiny ccid CCID check code (Addresses 0-62) utiny[3] reserved3 Reserved {} {extn_id (Extended ID Fields (Addresses 64-95))} utiny br_min Baud rate, mmin (% lower margin) utiny br_max Baud rate, max (% upper margin) utiny[2] options Options utiny[16] vendor_sn Vendor serial number utiny[8] date_code Date code utiny ccex CCEX check code (Addresses 64-94) utiny[3] reserved Reserved {} {vend_id (Vendor Specific ID Fields (Addresses 96-127))} utiny[32] vendor_specific_data {} {saved (Saved information (not part of SFF Serial Data EEPROM information)} utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127. utiny spare available to use utiny calc_ccex Saved software calculated CCEX utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[9] GBIC Small Form Factor Serial ID data {} {} {recursive_event[0] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[1] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[2] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[3] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[4] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[5] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[6] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[7] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[8] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[9] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[10] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[11] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[12] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[13] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[14] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[15] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[16] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[17] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[18] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[19] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[20] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[21] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[22] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[23] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[24] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[25] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[26] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[27] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[28] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[29] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[30] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[31] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {recursive_event[32] (Recursive entry array)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} {unexpected_event[0] (Unexpected event array)} ulong type Unexpected event type ulong pto Post-Termination Operation Indicator ulong[10] param Unexpected event parameters {} {unexpected_event[1] (Unexpected event array)} ulong type Unexpected event type ulong pto Post-Termination Operation Indicator ulong[10] param Unexpected event parameters {} {unexpected_event[2] (Unexpected event array)} ulong type Unexpected event type ulong pto Post-Termination Operation Indicator ulong[10] param Unexpected event parameters {} {unexpected_event[3] (Unexpected event array)} ulong type Unexpected event type ulong pto Post-Termination Operation Indicator ulong[10] param Unexpected event parameters {} {first_event (First event information)} ulong tt Trap type ulong tc Termination code ulong srr0 SRR0 register ulong srr1 SRR1 register ulong cr CR register ulong xer XER register ulong ctr CTR register ulong lr LR register ulong exception Exception code ulong count Exception count {} ulonglong brcookie Back revision cookie {} {ltecb (Last Termination Event Control Block)} utiny recursive_notlogged Recursive entry not yet logged count utiny info_notlogged Last Termination Event Information not yet logged utiny reserved Reserved utiny ltecb_revision Last Termination Event Control Block Revision number utiny unexpected_logged Unexpected event already logged count utiny unexpected_notlogged Unexpected event not yet logged count utiny unexpected_event_index Unexpected event array index utiny recursive_logged Recursive entry already logged count ulong info_edc Last Termination Event Information EDC {} {} do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or u Last Termination Event Block Union utiny[16384] union_pad Union Element Padding (DO NOT DISPLAY!) endunion u Last Termination Event Block Union {} FSWGAS EVENT CODE TRANSLATION BLOCKS: EC BLOCK: 0102000d SCID_EXEC_TOD_CHANGE TRANSLATIONBLOCK TRANSLATE("Action: %[exec_tod]", eip0D.action); TRANSLATE("Current date/time: %[scmitim]", eip0D.ctime); TRANSLATE("Previous date/time: %[scmitim]", eip0D.ptime); ENDTRANSLATIONBLOCK EC BLOCK: 0300200a SCID_SCS_CBIC_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip0A.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", eip0A.dimm_size ); TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0301400b SCID_SCS_DDRIVE_INOP TRANSLATIONBLOCK TRANSLATE("Device: %[uuid]", eip0B.device); TRANSLATE("Port ID: %s", eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Rack: %d.", eip0B.rack_num), TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Enclosure: %d.", eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Bay: %d.", eip0B.bay) ); TRANSLATE( "Reason code: 0x%04X (%[drv_inop])", eip0B.reason_code, eip0B.reason_code ); CONDITIONAL(eip0B.flags.quorum_disk != 0, TRANSLATE( "Quorum space write sequence: %d.", eip0B.quorum_sequence ) ); CONDITIONAL(eip0B.flags.inq_state != 0, TRANSLATE( "Inquiry data is valid (get more details)" ); TRANSLATE( "Device capacity (blocks): %d.", eip0B.capacity ) ); CONDITIONAL(eip0B.rss_flags.member_migrating != 0, TRANSLATE( "Redundant Storage Set member is migrating" ) ); CONDITIONAL(eip0B.rss_flags.member_missing != 0, TRANSLATE( "Redundant Storage Set member is missing" ) ); CONDITIONAL(eip0B.rss_flags.member_abnormal != 0, TRANSLATE( "Redundant Storage Set member state: %d.", eip0B.member_state ) ); ENDTRANSLATIONBLOCK EC BLOCK: 03024f0b SCID_SCS_TOO_MANY_DISKS TRANSLATIONBLOCK TRANSLATE("Device: %[uuid]", eip0B.device); TRANSLATE("Port ID: %s", eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Rack: %d.", eip0B.rack_num), TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Enclosure: %d.", eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Bay: %d.", eip0B.bay) ); ENDTRANSLATIONBLOCK EC BLOCK: 0303000a SCID_SCS_START_OF_BOOT TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0304000a SCID_SCS_REALIZE_CELL_TRANSITION TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("Storage System: %[tag]", eip0A.scell_tag); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0305000a SCID_SCS_FINISHED_JOINING_SLAVE TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("Storage System: %[tag]", eip0A.scell_tag); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0306000a SCID_SCS_FINISHED_SLAVE_LEAVE TRANSLATIONBLOCK CONDITIONAL(eip0A.node_name.lo != 0, TRANSLATE("Controller: %[wwn]", eip0A.node_name), TRANSLATE("Controller node name not known") ); TRANSLATE("Storage System: %[tag]", eip0A.scell_tag); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0307000a SCID_SCS_MASTER_FAILOVER TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("Storage System: %[tag]", eip0A.scell_tag); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0308000a SCID_SCS_NSC_BROUGHT_IN TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip0A.node_name); TRANSLATE("Storage System: %[tag]", eip0A.scell_tag); TRANSLATE("DebugFlags: %08X PrintFlags: %08X", eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 03090018 SCID_SCS_MIGRATION_START TRANSLATIONBLOCK CONDITIONAL(eip18.source_migr == 0x06, TRANSLATE("Merge started") ); CONDITIONAL(eip18.source_migr == 0x0A, TRANSLATE("Split started") ); TRANSLATE("Disk Group tag: %[tag]", eip18.ldad_tag); TRANSLATE("Source Redundant Storage Set: %04X", eip18.source_rss); TRANSLATE("Target Redundant Storage Set: %04X", eip18.target_rss); TRANSLATE("Source migration flags: %04x", eip18.source_migr); TRANSLATE("Target migration flags: %04x", eip18.target_migr); TRANSLATE("Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X", eip18.smembers[0], eip18.smembers[1], eip18.smembers[2], eip18.smembers[3], eip18.smembers[4], eip18.smembers[5], eip18.smembers[6], eip18.smembers[7]); TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X", eip18.smembers[8], eip18.smembers[9], eip18.smembers[10], eip18.smembers[11], eip18.smembers[12], eip18.smembers[13], eip18.smembers[14], eip18.smembers[15]); TRANSLATE("Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X", eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2], eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5], eip18.tmembers[6], eip18.tmembers[7]); TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X", eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10], eip18.tmembers[11], eip18.tmembers[12], eip18.tmembers[13], eip18.tmembers[14], eip18.tmembers[15]); ENDTRANSLATIONBLOCK EC BLOCK: 030a0018 SCID_SCS_MIGRATION_END TRANSLATIONBLOCK CONDITIONAL(eip18.source_migr == 0x06, TRANSLATE("Merge finished") ); CONDITIONAL(eip18.source_migr == 0x0A, TRANSLATE("Split finished") ); TRANSLATE("Disk Group tag: %[tag]", eip18.ldad_tag); TRANSLATE("Source Redundant Storage Set: %04X", eip18.source_rss); TRANSLATE("Target Redundant Storage Set: %04X", eip18.target_rss); TRANSLATE("Source migration flags: %04x", eip18.source_migr); TRANSLATE("Target migration flags: %04x", eip18.target_migr); TRANSLATE("Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X", eip18.smembers[0], eip18.smembers[1], eip18.smembers[2], eip18.smembers[3], eip18.smembers[4], eip18.smembers[5], eip18.smembers[6], eip18.smembers[7]); TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X", eip18.smembers[8], eip18.smembers[9], eip18.smembers[10], eip18.smembers[11], eip18.smembers[12], eip18.smembers[13], eip18.smembers[14], eip18.smembers[15]); TRANSLATE("Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X", eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2], eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5], eip18.tmembers[6], eip18.tmembers[7]); TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X", eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10], eip18.tmembers[11], eip18.tmembers[12], eip18.tmembers[13], eip18.tmembers[14], eip18.tmembers[15]); ENDTRANSLATIONBLOCK EC BLOCK: 030b4f0b SCID_SCS_DRIVE_FAIL_DURING_REALIZE TRANSLATIONBLOCK TRANSLATE("Device: %[uuid]", eip0B.device); TRANSLATE("Port ID: %s", eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Rack: %d.", eip0B.rack_num), TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Enclosure: %d.", eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Bay: %d.", eip0B.bay) ); ENDTRANSLATIONBLOCK EC BLOCK: 030c001e SCID_SCS_FLAGS_CHANGED TRANSLATIONBLOCK TRANSLATE("DebugFlags: %08X PrintFlags: %08X Caller PC : %08X", eip1E.data[0], eip1E.data[1], eip1E.data[2]); ENDTRANSLATIONBLOCK EC BLOCK: 030d001e SCID_SCS_CSM_HANG_PROCESS TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE("Process: %s %02d", eip1E.info, eip1E.data[0]) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE("Process: %s", eip1E.info) ); CONDITIONAL(eip1E.data[1] != 0, TRANSLATE("Stack[0]: %08x (%s)", eip1E.data[1], XLATE_PC_CURRENT(eip1E.data[1])) ); CONDITIONAL(eip1E.data[2] != 0, TRANSLATE("Stack[1]: %08x (%s)", eip1E.data[2], XLATE_PC_CURRENT(eip1E.data[2])) ); CONDITIONAL(eip1E.data[3] != 0, TRANSLATE("Stack[2]: %08x (%s)", eip1E.data[3], XLATE_PC_CURRENT(eip1E.data[3])) ); CONDITIONAL(eip1E.data[4] != 0, TRANSLATE("Stack[3]: %08x (%s)", eip1E.data[4], XLATE_PC_CURRENT(eip1E.data[4])) ); CONDITIONAL(eip1E.data[5] != 0, TRANSLATE("Stack[4]: %08x (%s)", eip1E.data[5], XLATE_PC_CURRENT(eip1E.data[5])) ); CONDITIONAL(eip1E.data[6] != 0, TRANSLATE("Stack[5]: %08x (%s)", eip1E.data[6], XLATE_PC_CURRENT(eip1E.data[6])) ); CONDITIONAL(eip1E.data[7] != 0, TRANSLATE("Stack[6]: %08x (%s)", eip1E.data[7], XLATE_PC_CURRENT(eip1E.data[7])) ); CONDITIONAL(eip1E.data[8] != 0, TRANSLATE("Stack[7]: %08x (%s)", eip1E.data[8], XLATE_PC_CURRENT(eip1E.data[8])) ); CONDITIONAL(eip1E.data[9] != 0, TRANSLATE("Stack[8]: %08x (%s)", eip1E.data[9], XLATE_PC_CURRENT(eip1E.data[9])) ); CONDITIONAL(eip1E.data[10] != 0, TRANSLATE("Stack[9]: %08x (%s)", eip1E.data[10], XLATE_PC_CURRENT(eip1E.data[10])) ); CONDITIONAL(eip1E.data[11] != 0, TRANSLATE("Stack[10]: %08x (%s)", eip1E.data[11], XLATE_PC_CURRENT(eip1E.data[11])) ); CONDITIONAL(eip1E.data[12] != 0, TRANSLATE("Stack[11]: %08x (%s)", eip1E.data[12], XLATE_PC_CURRENT(eip1E.data[12])) ); CONDITIONAL(eip1E.data[13] != 0, TRANSLATE("Stack[12]: %08x (%s)", eip1E.data[13], XLATE_PC_CURRENT(eip1E.data[13])) ); CONDITIONAL(eip1E.data[14] != 0, TRANSLATE("Stack[13]: %08x (%s)", eip1E.data[14], XLATE_PC_CURRENT(eip1E.data[14])) ); CONDITIONAL(eip1E.data[15] != 0, TRANSLATE("Stack[14]: %08x (%s)", eip1E.data[15], XLATE_PC_CURRENT(eip1E.data[15])) ); CONDITIONAL(eip1E.data[16] != 0, TRANSLATE("Stack[15]: %08x (%s)", eip1E.data[16], XLATE_PC_CURRENT(eip1E.data[16])) ); CONDITIONAL(eip1E.data[17] != 0, TRANSLATE("Stack[16]: %08x (%s)", eip1E.data[17], XLATE_PC_CURRENT(eip1E.data[17])) ); CONDITIONAL(eip1E.data[18] != 0, TRANSLATE("Stack[17]: %08x (%s)", eip1E.data[18], XLATE_PC_CURRENT(eip1E.data[18])) ); CONDITIONAL(eip1E.data[19] != 0, TRANSLATE("Stack[18]: %08x (%s)", eip1E.data[19], XLATE_PC_CURRENT(eip1E.data[19])) ); CONDITIONAL(eip1E.data[20] != 0, TRANSLATE("Stack[19]: %08x (%s)", eip1E.data[20], XLATE_PC_CURRENT(eip1E.data[20])) ); CONDITIONAL(eip1E.data[21] != 0, TRANSLATE("Stack[20]: %08x (%s)", eip1E.data[21], XLATE_PC_CURRENT(eip1E.data[21])) ); CONDITIONAL(eip1E.data[22] != 0, TRANSLATE("Stack[21]: %08x (%s)", eip1E.data[22], XLATE_PC_CURRENT(eip1E.data[22])) ); CONDITIONAL(eip1E.data[23] != 0, TRANSLATE("Stack[22]: %08x (%s)", eip1E.data[23], XLATE_PC_CURRENT(eip1E.data[23])) ); ENDTRANSLATIONBLOCK EC BLOCK: 030e070b SCID_SCS_ID_WRITE_DRIVE_CHANGED TRANSLATIONBLOCK TRANSLATE("Device about to write: %[uuid]", eip0B.device); TRANSLATE("Port ID: %s", eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Rack: %d.", eip0B.rack_num), TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Enclosure: %d.", eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE("Bay: %d.", eip0B.bay) ); TRANSLATE( "Reason code: 0x%04X (%[drv_inop])", eip0B.reason_code, eip0B.reason_code ); CONDITIONAL(eip0B.flags.quorum_disk != 0, TRANSLATE( "Quorum space write sequence: %d.", eip0B.quorum_sequence ) ); CONDITIONAL(eip0B.flags.inq_state != 0, TRANSLATE( "Inquiry data is valid (get more details)" ); TRANSLATE( "Device capacity (blocks): %d.", eip0B.capacity ) ); CONDITIONAL(eip0B.rss_flags.member_migrating != 0, TRANSLATE( "Redundant Storage Set member is migrating" ) ); CONDITIONAL(eip0B.rss_flags.member_missing != 0, TRANSLATE( "Redundant Storage Set member is missing" ) ); CONDITIONAL(eip0B.rss_flags.member_abnormal != 0, TRANSLATE( "Redundant Storage Set member state: %d.", eip0B.member_state ) ); TRANSLATE("Device we should have written: %[uuid]", eip0B.second_device); TRANSLATE("Device fnb: 0x%08X", eip0B.second_fnb_ptr); TRANSLATE("Device poid, vol: 0x%04X, 0x%04X", eip0B.poid, eip0B.volnoid); ENDTRANSLATIONBLOCK EC BLOCK: 030f001e SCID_SCS_ROHS_COMPLIANCE TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE( "The HSV200 controller is RoHS compliant." ) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE( "The HSV200 controller is not RoHS compliant." ) ); CONDITIONAL(eip1E.data[1] == 1, TRANSLATE( "The HSV200 controller is a CR2 hardware build." ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0310001f SCID_SCS_UNIT_FAILOVER TRANSLATIONBLOCK TRANSLATE("Logical Disk: %[tag]", eip1F.ld_tag); TRANSLATE("Derived Unit: %[tag]", eip1F.du_tag); TRANSLATE("Storage System Virtual Disk: %[tag]", eip1F.scvd_tag); TRANSLATE("Prev Controller: %[wwn]", eip1F.prev_wwn); TRANSLATE("Current Controller: %[wwn]", eip1F.current_wwn); ENDTRANSLATIONBLOCK EC BLOCK: 03114420 SCID_SCS_FABRIC_ON_LOOP TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip20.node_name); TRANSLATE("FC port: %d", eip20.port); TRANSLATE("Port state: %d", eip20.data); ENDTRANSLATIONBLOCK EC BLOCK: 03120021 SCID_SCS_LDISK_ATTACH_DONE TRANSLATIONBLOCK TRANSLATE("Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag); TRANSLATE("Type: %[scmi_logical_disk_snap_attach_type]", eip21.operation); TRANSLATE("Status: %d", eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE("Success")); CONDITIONAL(eip21.status != 0, TRANSLATE("Error")); ENDTRANSLATIONBLOCK EC BLOCK: 03130021 SCID_SCS_LDISK_SNAPCLONE_UNSHARE_DONE TRANSLATIONBLOCK TRANSLATE("Snapclone Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag); ENDTRANSLATIONBLOCK EC BLOCK: 03140021 SCID_SCS_MIRROR_CLONE_DETACH_DONE TRANSLATIONBLOCK TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip21.prev_state, eip21.new_state); TRANSLATE("Status: %d", eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE("Success")); CONDITIONAL(eip21.status != 0, TRANSLATE("Error")); ENDTRANSLATIONBLOCK EC BLOCK: 03150021 SCID_SCS_MIRROR_CLONE_FRACTURE_DONE TRANSLATIONBLOCK TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag); TRANSLATE("Status: %d", eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE("Success")); CONDITIONAL(eip21.status != 0, TRANSLATE("Error")); ENDTRANSLATIONBLOCK EC BLOCK: 03160021 SCID_SCS_MIRROR_CLONE_RESYNC_DONE TRANSLATIONBLOCK TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag); ENDTRANSLATIONBLOCK EC BLOCK: 03170021 SCID_SCS_LDISK_INSTANT_RESTORE_DONE TRANSLATIONBLOCK TRANSLATE("Original Logical Disk: %[tag]", eip21.target_tag); TRANSLATE("Source Logical Disk: %[tag]", eip21.parent_tag); TRANSLATE("Status: %d", eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE("Success")); CONDITIONAL(eip21.status != 0, TRANSLATE("Error")); CONDITIONAL( eip21.operation == 1, TRANSLATE("This was a high performance instant restore operation") ); CONDITIONAL( eip21.operation != 1, TRANSLATE("This was a normal performance instant restore operation") ); ENDTRANSLATIONBLOCK EC BLOCK: 0400031c SCID_FM_TE TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( "Termination parameter[0]: 0x%08x", eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( "Termination parameter[1]: 0x%08x", eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( "Termination parameter[2]: 0x%08x", eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( "Termination parameter[3]: 0x%08x", eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( "Termination parameter[4]: 0x%08x", eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( "Termination parameter[5]: 0x%08x", eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( "Termination parameter[6]: 0x%08x", eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( "Termination parameter[7]: 0x%08x", eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( "Termination parameter[8]: 0x%08x", eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( "Termination parameter[9]: 0x%08x", eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( "Termination parameter[10]: 0x%08x", eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( "Termination parameter[11]: 0x%08x", eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( "Termination parameter[12]: 0x%08x", eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( "Termination parameter[13]: 0x%08x", eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( "Termination parameter[14]: 0x%08x", eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( "Termination parameter[15]: 0x%08x", eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( "Termination parameter[16]: 0x%08x", eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( "Termination parameter[17]: 0x%08x", eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( "Termination parameter[18]: 0x%08x", eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( "Termination parameter[19]: 0x%08x", eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( "Termination parameter[20]: 0x%08x", eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( "Termination parameter[21]: 0x%08x", eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( "Termination parameter[22]: 0x%08x", eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( "Termination parameter[23]: 0x%08x", eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( "Termination parameter[24]: 0x%08x", eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( "Termination parameter[25]: 0x%08x", eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( "Termination parameter[26]: 0x%08x", eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( "Termination parameter[27]: 0x%08x", eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( "Termination parameter[28]: 0x%08x", eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( "Termination parameter[29]: 0x%08x", eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( "Termination parameter[30]: 0x%08x", eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1C.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1C.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1C.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1C.lter.terminating_ctrlr ); TRANSLATE( "Termination event sequence number: %d.", eip1C.lter.seq ); TRANSLATE( "Terminating controller's software version: %s", eip1C.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1C.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0401031c SCID_FM_LAST_GASP TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( "Termination parameter[0]: 0x%08x", eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( "Termination parameter[1]: 0x%08x", eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( "Termination parameter[2]: 0x%08x", eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( "Termination parameter[3]: 0x%08x", eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( "Termination parameter[4]: 0x%08x", eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( "Termination parameter[5]: 0x%08x", eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( "Termination parameter[6]: 0x%08x", eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( "Termination parameter[7]: 0x%08x", eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( "Termination parameter[8]: 0x%08x", eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( "Termination parameter[9]: 0x%08x", eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( "Termination parameter[10]: 0x%08x", eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( "Termination parameter[11]: 0x%08x", eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( "Termination parameter[12]: 0x%08x", eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( "Termination parameter[13]: 0x%08x", eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( "Termination parameter[14]: 0x%08x", eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( "Termination parameter[15]: 0x%08x", eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( "Termination parameter[16]: 0x%08x", eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( "Termination parameter[17]: 0x%08x", eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( "Termination parameter[18]: 0x%08x", eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( "Termination parameter[19]: 0x%08x", eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( "Termination parameter[20]: 0x%08x", eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( "Termination parameter[21]: 0x%08x", eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( "Termination parameter[22]: 0x%08x", eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( "Termination parameter[23]: 0x%08x", eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( "Termination parameter[24]: 0x%08x", eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( "Termination parameter[25]: 0x%08x", eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( "Termination parameter[26]: 0x%08x", eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( "Termination parameter[27]: 0x%08x", eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( "Termination parameter[28]: 0x%08x", eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( "Termination parameter[29]: 0x%08x", eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( "Termination parameter[30]: 0x%08x", eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1C.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: %08x", eip1C.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1C.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1C.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip1C.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1C.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 04020101 SCID_FM_TPRE TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip01.ru.lter.termination_event.u.value, XLATE_TC_FLO( eip01.ru.lter.termination_event.u.value, eip01.ru.lter.ctrlr_model_id, eip01.ru.lter.baselevel_id, eip01.ru.lter.sw_version ) ); TRANSLATE( "Termination location: 0x%08x", eip01.ru.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip01.ru.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip01.ru.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip01.ru.lter.sw_version ); TRANSLATE( "Controller uptime: %y. seconds", eip01.ru.lter.uptime ); TRANSLATE( "Post termination operation: %d. (%[fm_terminate_routines])", eip01.ru.lter.reuea_index, eip01.ru.lter.reuea_index ); TRANSLATE( "Trap type: 0x%08x", eip01.rei.tt ); TRANSLATE( "Termination code: 0x%08x", eip01.rei.tc ); TRANSLATE( "SRR0 register: 0x%08x", eip01.rei.srr0 ); TRANSLATE( "LR register: 0x%08x", eip01.rei.lr ); TRANSLATE( "Exception code: 0x%08x", eip01.rei.exception ); ENDTRANSLATIONBLOCK EC BLOCK: 04030102 SCID_FM_TPUE TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip02.ru.lter.termination_event.u.value, XLATE_TC_FLO( eip02.ru.lter.termination_event.u.value, eip02.ru.lter.ctrlr_model_id, eip02.ru.lter.baselevel_id, eip02.ru.lter.sw_version ) ); TRANSLATE( "Termination location: 0x%08x", eip02.ru.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip02.ru.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip02.ru.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip02.ru.lter.sw_version ); TRANSLATE( "Controller uptime: %y. seconds", eip02.ru.lter.uptime ); TRANSLATE( "Unexpected event type: %d. (%[fm_ue])", eip02.uei.type, eip02.uei.type ); TRANSLATE( "Post termination operation: %d. (%[fm_terminate_routines])", eip02.uei.pto, eip02.uei.pto ); TRANSLATE( "Parameter[0]: 0x%08x", eip02.uei.param[0] ); TRANSLATE( "Parameter[1]: 0x%08x", eip02.uei.param[1] ); TRANSLATE( "Parameter[2]: 0x%08x", eip02.uei.param[2] ); TRANSLATE( "Parameter[3]: 0x%08x", eip02.uei.param[3] ); TRANSLATE( "Parameter[3]: 0x%08x", eip02.uei.param[3] ); ENDTRANSLATIONBLOCK EC BLOCK: 04040003 SCID_FM_SCEL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.scelcbi.status == 0, TRANSLATE("Status: 0. (No problems found)"), TRANSLATE( "Unexpected status: %d.", eip03.cinfo.scelcbi.status ) ); TRANSLATE( "Current offset: %d.", eip03.cinfo.scelcbi.current_offset ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.seq_reset != 0, TRANSLATE("Sequence number reset"), TRANSLATE("Sequence number not reset") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.wrapped != 0, TRANSLATE("Events wrapped"), TRANSLATE("Events not wrapped") ); TRANSLATE( "Current EDBN: %d.", eip03.cinfo.scelcbi.current_edbn ); TRANSLATE( "Start EDBN: %d.", eip03.cinfo.scelcbi.start_edbn ); TRANSLATE( "End EDBN: %d.", eip03.cinfo.scelcbi.end_edbn ); TRANSLATE( "Sequence reset EDBN: %d.", eip03.cinfo.scelcbi.seq_reset_edbn ); TRANSLATE( "Event count: %d.", eip03.cinfo.scelcbi.event_count ); TRANSLATE( "Sequence number: %d.", eip03.cinfo.scelcbi.sequence_number ); TRANSLATE( "Loop index: %d.", eip03.minfo.scelmi.index ); TRANSLATE( "Zero test buffer pointer: 0x%08x", eip03.minfo.scelmi.utp ); TRANSLATE( "Current event pointer: 0x%08x", eip03.minfo.scelmi.current_eventp ); TRANSLATE( "Current EDBN: %d.", eip03.minfo.scelmi.current_edbn ); TRANSLATE( "Current sequence number: %d.", eip03.minfo.scelmi.current_seqn ); TRANSLATE( "Previous offset: %d., 0x%04x", eip03.minfo.scelmi.previous_offset, eip03.minfo.scelmi.previous_offset ); TRANSLATE( "Current offset: %d., 0x%04x", eip03.minfo.scelmi.current_offset, eip03.minfo.scelmi.current_offset ); TRANSLATE( "Previous EDBN: %d.", eip03.minfo.scelmi.previous_edbn ); TRANSLATE( "Previous sequence number: %d.", eip03.minfo.scelmi.previous_seqn ); CONDITIONAL( eip03.minfo.scelmi.end_found != 0, TRANSLATE("End found"), TRANSLATE("End not found") ); CONDITIONAL( eip03.minfo.scelmi.accept_new_to_old != 0, TRANSLATE("New to old acceptable"), TRANSLATE("New to old not acceptable") ); CONDITIONAL( eip03.minfo.scelmi.unequal_found != 0, TRANSLATE("Sequence number not as expected"), TRANSLATE("Sequence number as expected") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.scelmi.iostatus, eip03.minfo.scelmi.iostatus ); ENDTRANSLATIONBLOCK EC BLOCK: 04050003 SCID_FM_SCEL_INITED TRANSLATIONBLOCK TRANSLATE( "Status: 0x%02x (%[fm_mpvfc])", eip03.cinfo.scelcbi.status, eip03.cinfo.scelcbi.status ); TRANSLATE( "Current offset: %d.", eip03.cinfo.scelcbi.current_offset ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.seq_reset != 0, TRANSLATE("Sequence number reset"), TRANSLATE("Sequence number not reset") ); CONDITIONAL( eip03.cinfo.scelcbi.flags.wrapped != 0, TRANSLATE("Events wrapped"), TRANSLATE("Events not wrapped") ); TRANSLATE( "Current EDBN: %d.", eip03.cinfo.scelcbi.current_edbn ); TRANSLATE( "Start EDBN: %d.", eip03.cinfo.scelcbi.start_edbn ); TRANSLATE( "End EDBN: %d.", eip03.cinfo.scelcbi.end_edbn ); TRANSLATE( "Sequence reset EDBN: %d.", eip03.cinfo.scelcbi.seq_reset_edbn ); TRANSLATE( "Event count: %d.", eip03.cinfo.scelcbi.event_count ); TRANSLATE( "Sequence number: %d.", eip03.cinfo.scelcbi.sequence_number ); TRANSLATE( "Loop index: %d.", eip03.minfo.scelmi.index ); TRANSLATE( "Zero test buffer pointer: 0x%08x", eip03.minfo.scelmi.utp ); TRANSLATE( "Current event pointer: 0x%08x", eip03.minfo.scelmi.current_eventp ); TRANSLATE( "Current EDBN: %d.", eip03.minfo.scelmi.current_edbn ); TRANSLATE( "Current sequence number: %d.", eip03.minfo.scelmi.current_seqn ); TRANSLATE( "Previous offset: %d., 0x%04X", eip03.minfo.scelmi.previous_offset, eip03.minfo.scelmi.previous_offset ); TRANSLATE( "Current offset: %d., 0x%04X", eip03.minfo.scelmi.current_offset, eip03.minfo.scelmi.current_offset ); TRANSLATE( "Previous EDBN: %d.", eip03.minfo.scelmi.previous_edbn ); TRANSLATE( "Previous sequence number: %d.", eip03.minfo.scelmi.previous_seqn ); CONDITIONAL( eip03.minfo.scelmi.end_found != 0, TRANSLATE("End found"), TRANSLATE("End not found") ); CONDITIONAL( eip03.minfo.scelmi.accept_new_to_old != 0, TRANSLATE("New to old acceptable"), TRANSLATE("New to old not acceptable") ); CONDITIONAL( eip03.minfo.scelmi.unequal_found != 0, TRANSLATE("Sequence number not as expected"), TRANSLATE("Sequence number as expected") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.scelmi.iostatus, eip03.minfo.scelmi.iostatus ); ENDTRANSLATIONBLOCK EC BLOCK: 04060803 SCID_FM_LOCAL_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( "Local events not reported: %d.", eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04070803 SCID_FM_REMOTE_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( "Remote events not reported: %d.", eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04080003 SCID_FM_SCTEL_INACC TRANSLATIONBLOCK TRANSLATE( "Status: 0x%02x (%[fm_mpvfc])", eip03.cinfo.sctelcbi.status, eip03.cinfo.sctelcbi.status ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE("B events wrapped"), TRANSLATE("B events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE("B events valid"), TRANSLATE("B events not valid") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE("A events wrapped"), TRANSLATE("A events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE("A events valid"), TRANSLATE("A events not valid") ); TRANSLATE( "A Controller: %[uuid]", eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( "A MRU TEDBN: %d.", eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( "B Controller: %[uuid]", eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( "B MRU TEDBN: %d.", eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( "Loop index: %d.", eip03.minfo.sctelmi.index ); TRANSLATE( "Current TEDBN: %d.", eip03.minfo.sctelmi.current_edbn ); TRANSLATE( "End TEDBN: %d.", eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE("Is A controller"), TRANSLATE("Is not A controller") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( "Hold buffer offset: %d., 0x%08x", eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 04090003 SCID_FM_SCTEL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE("Status: 0. (No problems found)"), TRANSLATE( "Unexpected status: %d.", eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE("B events wrapped"), TRANSLATE("B events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE("B events valid"), TRANSLATE("B events not valid") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE("A events wrapped"), TRANSLATE("A events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE("A events valid"), TRANSLATE("A events not valid") ); TRANSLATE( "A Controller: %[uuid]", eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( "A MRU TEDBN: %d.", eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( "B Controller: %[uuid]", eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( "B MRU TEDBN: %d.", eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( "Loop index: %d.", eip03.minfo.sctelmi.index ); TRANSLATE( "Current TEDBN: %d.", eip03.minfo.sctelmi.current_edbn ); TRANSLATE( "End TEDBN: %d.", eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE("Is A controller"), TRANSLATE("Is not A controller") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( "Hold buffer offset: %d., 0x%08x", eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040a0003 SCID_FM_SCTEL_INITED TRANSLATIONBLOCK TRANSLATE( "Status: 0x%02x (%[fm_mpvfc])", eip03.cinfo.sctelcbi.status, eip03.cinfo.sctelcbi.status ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE("B events wrapped"), TRANSLATE("B events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE("B events valid"), TRANSLATE("B events not valid") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE("A events wrapped"), TRANSLATE("A events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE("A events valid"), TRANSLATE("A events not valid") ); TRANSLATE( "A Controller: %[uuid]", eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( "A MRU TEDBN: %d.", eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( "B Controller: %[uuid]", eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( "B MRU TEDBN: %d.", eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( "Loop index: %d.", eip03.minfo.sctelmi.index ); TRANSLATE( "Current TEDBN: %d.", eip03.minfo.sctelmi.current_edbn ); TRANSLATE( "End TEDBN: %d.", eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE("Is A controller"), TRANSLATE("Is not A controller") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( "Hold buffer offset: %d., 0x%08x", eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040b0003 SCID_FM_SCTEL_UPDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE("Status: 0. (No problems found)"), TRANSLATE( "Unexpected status: %d.", eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE("B events wrapped"), TRANSLATE("B events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE("B events valid"), TRANSLATE("B events not valid") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE("A events wrapped"), TRANSLATE("A events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE("A events valid"), TRANSLATE("A events not valid") ); TRANSLATE( "A Controller: %[uuid]", eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( "A MRU TEDBN: %d.", eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( "B Controller: %[uuid]", eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( "B MRU TEDBN: %d.", eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( "Loop index: %d.", eip03.minfo.sctelmi.index ); TRANSLATE( "Current TEDBN: %d.", eip03.minfo.sctelmi.current_edbn ); TRANSLATE( "End TEDBN: %d.", eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE("Is A controller"), TRANSLATE("Is not A controller") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( "Hold buffer offset: %d., 0x%08x", eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040c0803 SCID_FM_BAD_REMOTE_EVENT TRANSLATIONBLOCK TRANSLATE( "EIP event code: 0x%08x", eip03.ainfo.remote_event.u.value ); TRANSLATE( "EIP type: 0x%02x", eip03.ainfo.remote_event.type ); TRANSLATE( "EIP revision number: 0x%02x", eip03.ainfo.remote_event.revision ); TRANSLATE("EIP count: %d.", eip03.ainfo.remote_event.count); ENDTRANSLATIONBLOCK EC BLOCK: 040d0003 SCID_FM_QUIESCED TRANSLATIONBLOCK TRANSLATE( "Quiescent type: %[fm_quiesce]", eip03.ainfo.quiesce_type ); ENDTRANSLATIONBLOCK EC BLOCK: 040e031c SCID_FM_TE_CPLD TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( "Termination parameter[0]: 0x%08x", eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( "Termination parameter[1]: 0x%08x", eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( "Termination parameter[2]: 0x%08x", eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( "Termination parameter[3]: 0x%08x", eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( "Termination parameter[4]: 0x%08x", eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( "Termination parameter[5]: 0x%08x", eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( "Termination parameter[6]: 0x%08x", eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( "Termination parameter[7]: 0x%08x", eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( "Termination parameter[8]: 0x%08x", eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( "Termination parameter[9]: 0x%08x", eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( "Termination parameter[10]: 0x%08x", eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( "Termination parameter[11]: 0x%08x", eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( "Termination parameter[12]: 0x%08x", eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( "Termination parameter[13]: 0x%08x", eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( "Termination parameter[14]: 0x%08x", eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( "Termination parameter[15]: 0x%08x", eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( "Termination parameter[16]: 0x%08x", eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( "Termination parameter[17]: 0x%08x", eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( "Termination parameter[18]: 0x%08x", eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( "Termination parameter[19]: 0x%08x", eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( "Termination parameter[20]: 0x%08x", eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( "Termination parameter[21]: 0x%08x", eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( "Termination parameter[22]: 0x%08x", eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( "Termination parameter[23]: 0x%08x", eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( "Termination parameter[24]: 0x%08x", eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( "Termination parameter[25]: 0x%08x", eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( "Termination parameter[26]: 0x%08x", eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( "Termination parameter[27]: 0x%08x", eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( "Termination parameter[28]: 0x%08x", eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( "Termination parameter[29]: 0x%08x", eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( "Termination parameter[30]: 0x%08x", eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1C.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1C.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1C.lter.termination_time ); TRANSLATE( "Second terminating controller: %[scmi_obj_hnd]", eip1C.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip1C.lter.sw_version ); TRANSLATE( "Controller uptime: %y. seconds", eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 040f0003 SCID_FM_TEISP_SENT TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE("Status: 0. (No problems found)"), TRANSLATE( "Unexpected status: %d.", eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE("B events wrapped"), TRANSLATE("B events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE("B events valid"), TRANSLATE("B events not valid") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE("A events wrapped"), TRANSLATE("A events not wrapped") ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE("A events valid"), TRANSLATE("A events not valid") ); TRANSLATE( "A Controller: %[uuid]", eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( "A MRU TEDBN: %d.", eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( "B Controller: %[uuid]", eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( "B MRU TEDBN: %d.", eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( "Loop index: %d.", eip03.minfo.sctelmi.index ); TRANSLATE( "Current TEDBN: %d.", eip03.minfo.sctelmi.current_edbn ); TRANSLATE( "End TEDBN: %d.", eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE("Is A controller"), TRANSLATE("Is not A controller") ); TRANSLATE( "I/O status: %d., 0x%08x", eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( "Hold buffer offset: %d., 0x%08x", eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 04100803 SCID_FM_LOCAL_ISR_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( "ISR events not reported: %d.", eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04110803 SCID_FM_REMOTE_ISR_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( "ISR events not reported: %d.", eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04120003 SCID_FM_LER_INTERVAL_CHANGED TRANSLATIONBLOCK CONDITIONAL( eip03.minfo.lerinfo.reporting_interval != 0, TRANSLATE( "Last event reporting enabled, interval: %d. minutes", eip03.minfo.lerinfo.reporting_interval * 15 ), TRANSLATE("Last event reporting disabled") ); ENDTRANSLATIONBLOCK EC BLOCK: 04130003 SCID_FM_LAST_EVENT_REPORTED TRANSLATIONBLOCK TRANSLATE("Last event information - "); TRANSLATE( " Reporting interval: %d. minutes", eip03.minfo.lerinfo.reporting_interval * 15 ); TRANSLATE( " Sequence number: %d.", eip03.minfo.lerinfo.sequence_number ); TRANSLATE( " Report time: %[scmitim]", eip03.minfo.lerinfo.report_time ); TRANSLATE( " Event code: %08X", eip03.minfo.lerinfo.header.u.value ); TRANSLATE("Primary controller last 30 seconds activity summary - "); TRANSLATE( " Total requests per second: %d.", eip03.cinfo.stats30.total.rps ); TRANSLATE( " Total KB per second: %d.", eip03.cinfo.stats30.total.kbs ); TRANSLATE( " Host requests per second: %d.", eip03.cinfo.stats30.host.rps ); TRANSLATE( " Host KB per second: %d.", eip03.cinfo.stats30.host.kbs ); ENDTRANSLATIONBLOCK EC BLOCK: 0414031d SCID_FM_TE_OLD TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1D.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1D.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1D.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1D.lter.terminating_ctrlr ); TRANSLATE( "Termination event sequence number: %d.", eip1D.lter.seq ); TRANSLATE( "Terminating controller's software version: %s", eip1D.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1D.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0415031d SCID_FM_LAST_GASP_OLD TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1D.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: %08x", eip1D.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1D.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1D.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip1D.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1D.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0416031d SCID_FM_TE_CPLD_OLD TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1D.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1D.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1D.lter.termination_time ); TRANSLATE( "Second terminating controller: %[scmi_obj_hnd]", eip1D.lter.terminating_ctrlr ); TRANSLATE( "Terminating controller's software version: %s", eip1D.lter.sw_version ); TRANSLATE( "Controller uptime: %y. seconds", eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 04180003 SCID_FM_MEAL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.mealcbi.status == 0, TRANSLATE("Status: 0. (No problems found)"), TRANSLATE( "Unexpected status: %d.", eip03.cinfo.mealcbi.status ) ); TRANSLATE( "Current offset: %d.", eip03.cinfo.mealcbi.current_offset ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.seq_reset != 0, TRANSLATE("Sequence number reset"), TRANSLATE("Sequence number not reset") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.wrapped != 0, TRANSLATE("Events wrapped"), TRANSLATE("Events not wrapped") ); TRANSLATE( "Current EDBN: %d.", eip03.cinfo.mealcbi.current_edbn ); TRANSLATE( "Start EDBN: %d.", eip03.cinfo.mealcbi.start_edbn ); TRANSLATE( "End EDBN: %d.", eip03.cinfo.mealcbi.end_edbn ); TRANSLATE( "Sequence reset EDBN: %d.", eip03.cinfo.mealcbi.seq_reset_edbn ); TRANSLATE( "Event count: %d.", eip03.cinfo.mealcbi.event_count ); TRANSLATE( "Sequence number: %d.", eip03.cinfo.mealcbi.sequence_number ); TRANSLATE( "Loop index: %d.", eip03.minfo.mealmi.index ); TRANSLATE( "Zero test buffer pointer: 0x%08x", eip03.minfo.mealmi.utp ); TRANSLATE( "Current event pointer: 0x%08x", eip03.minfo.mealmi.current_eventp ); TRANSLATE( "Current EDBN: %d.", eip03.minfo.mealmi.current_edbn ); TRANSLATE( "Current sequence number: %d.", eip03.minfo.mealmi.current_seqn ); TRANSLATE( "Previous offset: %d., 0x%04x", eip03.minfo.mealmi.previous_offset, eip03.minfo.mealmi.previous_offset ); TRANSLATE( "Current offset: %d., 0x%04x", eip03.minfo.mealmi.current_offset, eip03.minfo.mealmi.current_offset ); TRANSLATE( "Previous EDBN: %d.", eip03.minfo.mealmi.previous_edbn ); TRANSLATE( "Previous sequence number: %d.", eip03.minfo.mealmi.previous_seqn ); TRANSLATE( "First sequence number: %d.", eip03.minfo.mealmi.first_seqn ); CONDITIONAL( eip03.minfo.mealmi.end_found != 0, TRANSLATE("End found"), TRANSLATE("End not found") ); CONDITIONAL( eip03.minfo.mealmi.accept_new_to_old != 0, TRANSLATE("New to old acceptable"), TRANSLATE("New to old not acceptable") ); CONDITIONAL( eip03.minfo.mealmi.unequal_found != 0, TRANSLATE("Sequence number not as expected"), TRANSLATE("Sequence number as expected") ); ENDTRANSLATIONBLOCK EC BLOCK: 04190003 SCID_FM_MEAL_INITED TRANSLATIONBLOCK TRANSLATE( "Status: 0x%02x (%[fm_mpvfc])", eip03.cinfo.mealcbi.status, eip03.cinfo.mealcbi.status ); TRANSLATE( "Current offset: %d.", eip03.cinfo.mealcbi.current_offset ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_set != 0, TRANSLATE("Time set"), TRANSLATE("Time not set") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_synched != 0, TRANSLATE("Time synchronized"), TRANSLATE("Time not synchronized") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.seq_reset != 0, TRANSLATE("Sequence number reset"), TRANSLATE("Sequence number not reset") ); CONDITIONAL( eip03.cinfo.mealcbi.flags.wrapped != 0, TRANSLATE("Events wrapped"), TRANSLATE("Events not wrapped") ); TRANSLATE( "Current EDBN: %d.", eip03.cinfo.mealcbi.current_edbn ); TRANSLATE( "Start EDBN: %d.", eip03.cinfo.mealcbi.start_edbn ); TRANSLATE( "End EDBN: %d.", eip03.cinfo.mealcbi.end_edbn ); TRANSLATE( "Sequence reset EDBN: %d.", eip03.cinfo.mealcbi.seq_reset_edbn ); TRANSLATE( "Event count: %d.", eip03.cinfo.mealcbi.event_count ); TRANSLATE( "Sequence number: %d.", eip03.cinfo.mealcbi.sequence_number ); TRANSLATE( "Loop index: %d.", eip03.minfo.mealmi.index ); TRANSLATE( "Zero test buffer pointer: 0x%08x", eip03.minfo.mealmi.utp ); TRANSLATE( "Current event pointer: 0x%08x", eip03.minfo.mealmi.current_eventp ); TRANSLATE( "Current EDBN: %d.", eip03.minfo.mealmi.current_edbn ); TRANSLATE( "Current sequence number: %d.", eip03.minfo.mealmi.current_seqn ); TRANSLATE( "Previous offset: %d., 0x%04X", eip03.minfo.mealmi.previous_offset, eip03.minfo.mealmi.previous_offset ); TRANSLATE( "Current offset: %d., 0x%04X", eip03.minfo.mealmi.current_offset, eip03.minfo.mealmi.current_offset ); TRANSLATE( "Previous EDBN: %d.", eip03.minfo.mealmi.previous_edbn ); TRANSLATE( "Previous sequence number: %d.", eip03.minfo.mealmi.previous_seqn ); TRANSLATE( "First sequence number: %d.", eip03.minfo.mealmi.first_seqn ); CONDITIONAL( eip03.minfo.mealmi.end_found != 0, TRANSLATE("End found"), TRANSLATE("End not found") ); CONDITIONAL( eip03.minfo.mealmi.accept_new_to_old != 0, TRANSLATE("New to old acceptable"), TRANSLATE("New to old not acceptable") ); CONDITIONAL( eip03.minfo.mealmi.unequal_found != 0, TRANSLATE("Sequence number not as expected"), TRANSLATE("Sequence number as expected") ); ENDTRANSLATIONBLOCK EC BLOCK: 041a031c SCID_FM_TE_PRETEND TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( "Termination parameter[0]: 0x%08x", eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( "Termination parameter[1]: 0x%08x", eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( "Termination parameter[2]: 0x%08x", eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( "Termination parameter[3]: 0x%08x", eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( "Termination parameter[4]: 0x%08x", eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( "Termination parameter[5]: 0x%08x", eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( "Termination parameter[6]: 0x%08x", eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( "Termination parameter[7]: 0x%08x", eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( "Termination parameter[8]: 0x%08x", eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( "Termination parameter[9]: 0x%08x", eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( "Termination parameter[10]: 0x%08x", eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( "Termination parameter[11]: 0x%08x", eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( "Termination parameter[12]: 0x%08x", eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( "Termination parameter[13]: 0x%08x", eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( "Termination parameter[14]: 0x%08x", eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( "Termination parameter[15]: 0x%08x", eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( "Termination parameter[16]: 0x%08x", eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( "Termination parameter[17]: 0x%08x", eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( "Termination parameter[18]: 0x%08x", eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( "Termination parameter[19]: 0x%08x", eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( "Termination parameter[20]: 0x%08x", eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( "Termination parameter[21]: 0x%08x", eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( "Termination parameter[22]: 0x%08x", eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( "Termination parameter[23]: 0x%08x", eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( "Termination parameter[24]: 0x%08x", eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( "Termination parameter[25]: 0x%08x", eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( "Termination parameter[26]: 0x%08x", eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( "Termination parameter[27]: 0x%08x", eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( "Termination parameter[28]: 0x%08x", eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( "Termination parameter[29]: 0x%08x", eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( "Termination parameter[30]: 0x%08x", eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1C.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1C.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1C.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1C.lter.terminating_ctrlr ); TRANSLATE( "Termination event sequence number: %d.", eip1C.lter.seq ); TRANSLATE( "Terminating controller's software version: %s", eip1C.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1C.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 041b031d SCID_FM_TE_OLD_PRETEND TRANSLATIONBLOCK TRANSLATE( "Termination code: 0x%08x (%s)", eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( "Termination corrective action code: 0x%02x", eip1D.lter.termination_event.u.code.cac ); TRANSLATE( "Termination location: 0x%08x", eip1D.lter.termination_event.termination_location ); TRANSLATE( "Termination date/time: %[scmitim]", eip1D.lter.termination_time ); TRANSLATE( "Terminating controller: %[scmi_obj_hnd]", eip1D.lter.terminating_ctrlr ); TRANSLATE( "Termination event sequence number: %d.", eip1D.lter.seq ); TRANSLATE( "Terminating controller's software version: %s", eip1D.lter.sw_version ); TRANSLATE( "Terminating controller's baselevel ID: %s", eip1D.lter.baselevel_id ); TRANSLATE( "Controller uptime: %y. seconds", eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 06000009 SCID_FCS_SMART_FAILURE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( "Sense Key: %1X (%[scsi_sensekey])", eip09.error.sense_data.sense_key, eip09.error.sense_data.sense_key ); TRANSLATE( "ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])", eip09.error.sense_data.asc_ascq.asc_ascqb.asc, eip09.error.sense_data.asc_ascq.asc_ascqb.asq, eip09.error.sense_data.asc_ascq.asc_ascqw ); TRANSLATE( "FRU Code: 0x%02x", eip09.error.sense_data.fru_code ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06014a08 SCID_FCS_LINK_FAILURE TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); TRANSLATE("Failure cause: %[fcs_fail]", eip08.failure_cause); TRANSLATE("Producer index: 0x%04x", eip08.peq_prod_index); TRANSLATE("Consumer index: 0x%04x", eip08.peq_cons_index); TRANSLATE("Frozen index: 0x%04x", eip08.peq_frz_prod_index); TRANSLATE("Port event block(s):"); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( " [0] Type: %08X Context: %08X", eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( " [1] Type: %08X Context: %08X", eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( " [2] Type: %08X Context: %08X", eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( " [3] Type: %08X Context: %08X", eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( " [4] Type: %08X Context: %08X", eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( " [5] Type: %08X Context: %08X", eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE( " [6] Type: %08X Context: %08X", eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( " [7] Type: %08X Context: %08X", eip08.peb[7].type, eip08.peb[7].context ) ); TRANSLATE("Retry Timer: %d seconds", eip08.time ); ENDTRANSLATIONBLOCK EC BLOCK: 06020009 SCID_FCS_CHECK_CONDITION TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( "Sense Key: %1X (%[scsi_sensekey])", eip09.error.sense_data.sense_key, eip09.error.sense_data.sense_key ); TRANSLATE( "ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])", eip09.error.sense_data.asc_ascq.asc_ascqb.asc, eip09.error.sense_data.asc_ascq.asc_ascqb.asq, eip09.error.sense_data.asc_ascq.asc_ascqw ); TRANSLATE( "FRU Code: 0x%02x", eip09.error.sense_data.fru_code ); TRANSLATE( "%s", XLATE_EIP09_LBA( eip09.cmd ) ); TRANSLATE( "Info: 0x%02x%02x%02x%02x", eip09.error.sense_data.info_0, eip09.error.sense_data.info_1, eip09.error.sense_data.info_2, eip09.error.sense_data.info_3 ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06034713 SCID_FCS_DATA_EXCHANGE_TIMEOUT TRANSLATIONBLOCK TRANSLATE("Intended recipient: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Number of timeouts detected: %d.", eip13.num_times); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06044812 SCID_FCS_UNEXPECTED_WORK TRANSLATIONBLOCK TRANSLATE("Sender: %[tag]", eip12.device); TRANSLATE("Port ID: %s", eip12.cerp_id); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip12.dencl_num - 100 ) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip12.bay - 100) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip12.dencl_num) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Bay: %d.", eip12.bay) ); TRANSLATE("AL_PA: 0x%04x", eip12.al_pa); TRANSLATE( "Command descriptor block and Fibre Channel header information:" ); TRANSLATE("hdr_cdb[0]: %08X", eip12.hdr_cdb[0]); TRANSLATE("hdr_cdb[1]: %08X", eip12.hdr_cdb[1]); TRANSLATE("hdr_cdb[2]: %08X", eip12.hdr_cdb[2]); TRANSLATE("hdr_cdb[3]: %08X", eip12.hdr_cdb[3]); TRANSLATE("hdr_cdb[4]: %08X", eip12.hdr_cdb[4]); TRANSLATE("hdr_cdb[5]: %08X", eip12.hdr_cdb[5]); TRANSLATE("hdr_cdb[6]: %08X", eip12.hdr_cdb[6]); TRANSLATE("hdr_cdb[7]: %08X", eip12.hdr_cdb[7]); TRANSLATE("hdr_cdb[8]: %08X", eip12.hdr_cdb[8]); TRANSLATE("hdr_cdb[9]: %08X", eip12.hdr_cdb[9]); TRANSLATE("hdr_cdb[10]: %08X", eip12.hdr_cdb[10]); TRANSLATE("hdr_cdb[11]: %08X", eip12.hdr_cdb[11]); TRANSLATE("hdr_cdb[12]: %08X", eip12.hdr_cdb[12]); TRANSLATE("hdr_cdb[13]: %08X", eip12.hdr_cdb[13]); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip12.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip12.bypassb); ENDTRANSLATIONBLOCK EC BLOCK: 06054909 SCID_FCS_BAD_ALPA TRANSLATIONBLOCK TRANSLATE("Intended target: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06074709 SCID_FCS_TDS_TIMEOUT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06080007 SCID_FCS_LINK_ERRORS TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip07.cerp_id); TRANSLATE("Non-zero error counts:"); CONDITIONAL( eip07.loss_of_signal != 0, TRANSLATE("Loss of signal: %d.", eip07.loss_of_signal) ); CONDITIONAL( eip07.bad_rx_char != 0, TRANSLATE("Bad RX character: %d.", eip07.bad_rx_char) ); CONDITIONAL( eip07.loss_of_sync != 0, TRANSLATE("Loss of synch: %d.", eip07.loss_of_sync) ); CONDITIONAL( eip07.link_fail != 0, TRANSLATE("Link failure: %d.", eip07.link_fail) ); CONDITIONAL( eip07.rx_eofa != 0, TRANSLATE("RX EOFa delimiter: %d.", eip07.rx_eofa) ); CONDITIONAL( eip07.dis_frm != 0, TRANSLATE("Discarded frame: %d.", eip07.dis_frm) ); CONDITIONAL( eip07.bad_crc != 0, TRANSLATE("Frames with bad CRC and valid EOF: %d.", eip07.bad_crc) ); CONDITIONAL( eip07.proto_err != 0, TRANSLATE("N_Port protocol error: %d.", eip07.proto_err) ); CONDITIONAL( eip07.exp_frm != 0, TRANSLATE("Expired outbound frame: %d.", eip07.exp_frm) ); ENDTRANSLATIONBLOCK EC BLOCK: 06090013 SCID_FCS_SMART_FAILURE_COUNT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Number of failure prediction threshold exceeded errors: %d.", eip13.num_times ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060a0013 SCID_FCS_CHECK_CONDITION_COUNT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Number of check condition errors in last minute: %d.", eip13.num_times ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); ENDTRANSLATIONBLOCK EC BLOCK: 060b4709 SCID_FCS_NONDATA_EXCH_TIMEOUT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060c0013 SCID_FCS_LOOP_SWITCH TRANSLATIONBLOCK CONDITIONAL( eip13.switch_type == 1 , TRANSLATE("Switch Type: 3XX Family") ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE("Switch Type: 8XX Family") ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE("Node Name: %[tag]", eip13.device) ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE("AL_PA: 0x%04x", eip13.al_pa) ); TRANSLATE("Port ID: %s", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060d0013 SCID_FCS_DRIVE_PHYSICAL_LOCATION TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060e9613 SCID_FCS_NO_EMU_CODE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060f4013 SCID_FCS_DRIVE_SEEN_ON_ESI TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06109b13 SCID_FCS_EMU_NOT_COMMUNICATE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06120008 SCID_FCS_EMU_RETRIES_EXHAUSTED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); TRANSLATE("Enclosure: %d.", eip08.peq_prod_index); TRANSLATE("Bay: %d.", eip08.failure_cause); CONDITIONAL(eip08.peq_cons_index == 0, TRANSLATE("Loop: A")); CONDITIONAL(eip08.peq_cons_index == 1, TRANSLATE("Loop: B")); TRANSLATE("Retried task: 0x%04x", eip08.peq_frz_prod_index); TRANSLATE("Task list to be sent to Drive Enclosure Environmental Monitoring Unit:"); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( " [0] Type: %08X Context: %08X", eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( " [1] Type: %08X Context: %08X", eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( " [2] Type: %08X Context: %08X", eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( " [3] Type: %08X Context: %08X", eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( " [4] Type: %08X Context: %08X", eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( " [5] Type: %08X Context: %08X", eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE( " [6] Type: %08X Context: %08X", eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( " [7] Type: %08X Context: %08X", eip08.peb[7].type, eip08.peb[7].context ) ); ENDTRANSLATIONBLOCK EC BLOCK: 06130013 SCID_FCS_EMU_COMMUNICATE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06149813 SCID_FCS_TOO_MANY_SHELVES TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06159913 SCID_FCS_PORT_CONNECTION_SWAPPED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06169713 SCID_FCS_CABINET_NOT_CONNECTED TRANSLATIONBLOCK TRANSLATE("Controller ID not available"); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06180013 SCID_FCS_EMU_CODE_LOAD_START TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06190013 SCID_FCS_EMU_CODE_LOAD_DONE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061a0009 SCID_FCS_DRIVE_SOFT_ERRORS TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061b0013 SCID_FCS_CABINET_CONNECTED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061c4709 SCID_FCS_FRAME_TIMEOUT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061d4709 SCID_FCS_DROPPED_FRAME TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061e4c13 SCID_FCS_DRIVE_SPOF TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Good port ID: %s", eip13.cerp_id); TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061f0013 SCID_FCS_DRIVE_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06204013 SCID_FCS_UNSUPPORTED_DRIVE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06210013 SCID_FCS_WRONG_BLOCK_SIZE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06230013 SCID_FCS_LINK_IS_RESTARTED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06240013 SCID_FCS_POST_LINK_FAIL_DD TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06254313 SCID_FCS_WRONG_HARD_ALPA TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Expected AL_PA: %04x", eip13.al_pa); TRANSLATE("Actual AL_PA: %04x", eip13.num_times); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06268913 SCID_FCS_HARD_ALPA_THIEF TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Stolen AL_PA: %04x", eip13.al_pa); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06270113 SCID_FCS_SOFT_ALPA TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06280008 SCID_FCS_EMU_OB_RETRIES_EXHAUSTED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); TRANSLATE("Enclosure: %d.", eip08.peq_prod_index); TRANSLATE("Bay: %d.", eip08.failure_cause); CONDITIONAL(eip08.peq_cons_index == 0, TRANSLATE("Loop: A")); CONDITIONAL(eip08.peq_cons_index == 1, TRANSLATE("Loop: B")); TRANSLATE("Retried task: 0x%04x", eip08.peq_frz_prod_index); TRANSLATE("Task list:"); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( " [0] Type: %08X Context: %08X", eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( " [1] Type: %08X Context: %08X", eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( " [2] Type: %08X Context: %08X", eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( " [3] Type: %08X Context: %08X", eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( " [4] Type: %08X Context: %08X", eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( " [5] Type: %08X Context: %08X", eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE( " [6] Type: %08X Context: %08X", eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( " [7] Type: %08X Context: %08X", eip08.peb[7].type, eip08.peb[7].context ) ); ENDTRANSLATIONBLOCK EC BLOCK: 06290009 SCID_FCS_ABORT TRANSLATIONBLOCK TRANSLATE("Intended target: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 062a0009 SCID_FCS_RRQ TRANSLATIONBLOCK TRANSLATE("Intended target: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 062b4004 SCID_FCS_DRIVE_BRICK TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("Bypass method: %[fcs_mtl]", eip04.bypass_reason); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 062c0012 SCID_FCS_BBR TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip12.device); TRANSLATE("Port ID: %s", eip12.cerp_id); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip12.dencl_num - 100 ) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip12.bay - 100) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip12.dencl_num) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE("Bay: %d.", eip12.bay) ); TRANSLATE("AL_PA: 0x%04x", eip12.al_pa); TRANSLATE("Media defects:"); CONDITIONAL( eip12.hdr_cdb[0] != 0, TRANSLATE( " [0] LBA: %08X", eip12.hdr_cdb[0] ) ); CONDITIONAL( eip12.hdr_cdb[1] != 0, TRANSLATE( " [1] LBA: %08X", eip12.hdr_cdb[1] ) ); CONDITIONAL( eip12.hdr_cdb[2] != 0, TRANSLATE( " [2] LBA: %08X", eip12.hdr_cdb[2] ) ); CONDITIONAL( eip12.hdr_cdb[3] != 0, TRANSLATE( " [3] LBA: %08X", eip12.hdr_cdb[3] ) ); CONDITIONAL( eip12.hdr_cdb[4] != 0, TRANSLATE( " [4] LBA: %08X", eip12.hdr_cdb[4] ) ); CONDITIONAL( eip12.hdr_cdb[5] != 0, TRANSLATE( " [5] LBA: %08X", eip12.hdr_cdb[5] ) ); CONDITIONAL( eip12.hdr_cdb[6] != 0, TRANSLATE( " [6] LBA: %08X", eip12.hdr_cdb[6] ) ); CONDITIONAL( eip12.hdr_cdb[7] != 0, TRANSLATE( " [7] LBA: %08X", eip12.hdr_cdb[7] ) ); CONDITIONAL( eip12.hdr_cdb[8] != 0, TRANSLATE( " [8] LBA: %08X", eip12.hdr_cdb[8] ) ); CONDITIONAL( eip12.hdr_cdb[9] != 0, TRANSLATE( " [9] LBA: %08X", eip12.hdr_cdb[9] ) ); CONDITIONAL( eip12.hdr_cdb[10] != 0, TRANSLATE( " [10] LBA: %08X", eip12.hdr_cdb[10] ) ); CONDITIONAL( eip12.hdr_cdb[11] != 0, TRANSLATE( " [11] LBA: %08X", eip12.hdr_cdb[11] ) ); CONDITIONAL( eip12.hdr_cdb[12] != 0, TRANSLATE( " [12] LBA: %08X", eip12.hdr_cdb[12] ) ); CONDITIONAL( eip12.hdr_cdb[13] != 0, TRANSLATE( " [13] LBA: %08X", eip12.hdr_cdb[13] ) ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip12.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip12.bypassb); ENDTRANSLATIONBLOCK EC BLOCK: 062d0012 SCID_FCS_DIRECTED_LIP TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip12.cerp_id); TRANSLATE("AL_PA: 0x%04x", eip12.al_pa); TRANSLATE("LIP Type:"); CONDITIONAL( eip12.hdr_cdb[0] == 0, TRANSLATE( " LIP(F7,F7)" ) ); CONDITIONAL( eip12.hdr_cdb[0] == 1, TRANSLATE( " DIRECTED RESET" ) ); TRANSLATE("Caller PC: 0x%08X", eip12.hdr_cdb[1]); ENDTRANSLATIONBLOCK EC BLOCK: 062e0012 SCID_FCS_LIP_F8 TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip12.cerp_id); TRANSLATE("Controller affected: %[tag]", eip12.device); CONDITIONAL( eip12.hdr_cdb[0] != 0, TRANSLATE( " [0] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[0] ) ); CONDITIONAL( eip12.hdr_cdb[1] != 0, TRANSLATE( " [1] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[1] ) ); CONDITIONAL( eip12.hdr_cdb[2] != 0, TRANSLATE( " [2] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[2] ) ); CONDITIONAL( eip12.hdr_cdb[3] != 0, TRANSLATE( " [3] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[3] ) ); CONDITIONAL( eip12.hdr_cdb[4] != 0, TRANSLATE( " [4] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[4] ) ); CONDITIONAL( eip12.hdr_cdb[5] != 0, TRANSLATE( " [5] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[5] ) ); CONDITIONAL( eip12.hdr_cdb[6] != 0, TRANSLATE( " [6] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[6] ) ); CONDITIONAL( eip12.hdr_cdb[7] != 0, TRANSLATE( " [7] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[7] ) ); CONDITIONAL( eip12.hdr_cdb[8] != 0, TRANSLATE( " [8] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[8] ) ); CONDITIONAL( eip12.hdr_cdb[9] != 0, TRANSLATE( " [9] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[9] ) ); CONDITIONAL( eip12.hdr_cdb[10] != 0, TRANSLATE( " [10] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[10] ) ); CONDITIONAL( eip12.hdr_cdb[11] != 0, TRANSLATE( " [11] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[11] ) ); CONDITIONAL( eip12.hdr_cdb[12] != 0, TRANSLATE( " [12] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[12] ) ); CONDITIONAL( eip12.hdr_cdb[13] != 0, TRANSLATE( " [13] Count/AL_PA (ccccaaaa): %08X", eip12.hdr_cdb[13] ) ); ENDTRANSLATIONBLOCK EC BLOCK: 06304e13 SCID_FCS_SHELF_SPOF TRANSLATIONBLOCK TRANSLATE("Enclosure: %[tag]", eip13.device); TRANSLATE("Good port ID: %s", eip13.cerp_id); TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("AL_PA: 0x%04x", eip13.al_pa); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06310013 SCID_FCS_SHELF_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE("Enclosure: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06324e13 SCID_FCS_PORT_SPOF TRANSLATIONBLOCK TRANSLATE("Good port ID: %s", eip13.cerp_id); TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06330013 SCID_FCS_PORT_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06340013 SCID_FCS_ENABLE_DP TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06354d04 SCID_FCS_UNKNOWN_FIRMWARE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Latest known revision: %s", eip04.new_rev); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06364d04 SCID_FCS_UNSUPPORTED_FIRMWARE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Latest known revision: %s", eip04.new_rev); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0637c404 SCID_FCS_LATER_FIRMWARE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Latest known revision: %s", eip04.new_rev); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0638c404 SCID_FCS_NEWER_FIRMWARE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Latest known revision: %s", eip04.new_rev); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06394008 SCID_FCS_LOOP_RECOVERY_SLOT_BYPASSED TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Cabinet ID: %d", eip08.recovery.cab); TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf); TRANSLATE("Bay: %d", eip08.recovery.slot); ENDTRANSLATIONBLOCK EC BLOCK: 063a0008 SCID_FCS_LOOP_RECOVERY_ENTERED TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Reason Code: %d", eip08.failure_cause); CONDITIONAL(eip08.failure_cause == 0x03, TRANSLATE("LID Recovery")); CONDITIONAL(eip08.failure_cause == 0x05, TRANSLATE("DDD Recovery")); ENDTRANSLATIONBLOCK EC BLOCK: 063b0008 SCID_FCS_LOOP_RECOVERY_EXIT TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Recovery Status: 0x%x", eip08.failure_cause); CONDITIONAL(eip08.failure_cause == 0, TRANSLATE("Recovery Status Text: Success")); CONDITIONAL(eip08.failure_cause == 1, TRANSLATE("Recovery Status Text: Exhausted retry count for FNB")); CONDITIONAL(eip08.failure_cause == 2, TRANSLATE("Recovery Status Text: No valid FNBs")); CONDITIONAL(eip08.failure_cause == 3, TRANSLATE("Recovery Status Text: No open DUB gates")); CONDITIONAL(eip08.failure_cause == 4, TRANSLATE("Recovery Status Text: Fibre channel error")); CONDITIONAL(eip08.failure_cause == 5, TRANSLATE("Recovery Status Text: CBIC codeload in progress")); CONDITIONAL(eip08.failure_cause == 6, TRANSLATE("Recovery Status Text: CBIC communications over IIC")); CONDITIONAL(eip08.failure_cause == 7, TRANSLATE("Recovery Status Text: Failed to enter FCS Maint Mode")); CONDITIONAL(eip08.failure_cause == 8, TRANSLATE("Recovery Status Text: Partial success")); CONDITIONAL(eip08.failure_cause == 9, TRANSLATE("Recovery Status Text: Task aborted")); CONDITIONAL(eip08.failure_cause == 10, TRANSLATE("Recovery Status Text: No progress made")); CONDITIONAL(eip08.failure_cause == 11, TRANSLATE("Recovery Status Text: Semaphore wait timed out")); CONDITIONAL(eip08.failure_cause == 12, TRANSLATE("Recovery Status Text: Exceeded max failure threshold for loop recovery")); CONDITIONAL(eip08.failure_cause == 13, TRANSLATE("Recovery Status Text: User disabled loop recoveries")); ENDTRANSLATIONBLOCK EC BLOCK: 063c0008 SCID_FCS_LOOP_RECOVERY_ABORT TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Progress: %x", eip08.recovery.progress); TRANSLATE("Abort Status: %x", eip08.failure_cause); ENDTRANSLATIONBLOCK EC BLOCK: 063d9b09 SCID_FCS_SHELF_ONLY_OB TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); ENDTRANSLATIONBLOCK EC BLOCK: 063ec513 SCID_FCS_SHELF_ONLY_IB TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[tag]", eip13.device); TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack and enclosure not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 063f9c13 SCID_FCS_DRIVE_EMU_NOT_COMMUNICATE TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num != 99, TRANSLATE("Rack: %d.", eip13.rack_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num != 99, TRANSLATE("Enclosure: %d.", eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num != 99, TRANSLATE("Bay: %d.", eip13.bay) ); TRANSLATE("physical disk drive: %[tag]", eip13.device); ENDTRANSLATIONBLOCK EC BLOCK: 06404d04 SCID_FCS_PROVISIONAL_DRIVE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Latest known revision: %s", eip04.new_rev); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06410017 SCID_FCS_LOOP_CONFIG TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip17.cerp_id); TRANSLATE("Map ID: %u", eip17.map_id); TRANSLATE("Loop map page: %d of %d", eip17.page, eip17.total_pages); TRANSLATE("Entries in this page: %d", eip17.entries); CONDITIONAL(eip17.loop_map[0] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[00] ALPA: 0x%X", eip17.loop_map[0]) ); CONDITIONAL(eip17.loop_map[0] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[92] ALPA: 0x%X", eip17.loop_map[0]) ); CONDITIONAL(eip17.loop_map[1] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[01] ALPA: 0x%X", eip17.loop_map[1]) ); CONDITIONAL(eip17.loop_map[1] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[93] ALPA: 0x%X", eip17.loop_map[1]) ); CONDITIONAL(eip17.loop_map[2] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[02] ALPA: 0x%X", eip17.loop_map[2]) ); CONDITIONAL(eip17.loop_map[2] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[94] ALPA: 0x%X", eip17.loop_map[2]) ); CONDITIONAL(eip17.loop_map[3] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[03] ALPA: 0x%X", eip17.loop_map[3]) ); CONDITIONAL(eip17.loop_map[3] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[95] ALPA: 0x%X", eip17.loop_map[3]) ); CONDITIONAL(eip17.loop_map[4] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[04] ALPA: 0x%X", eip17.loop_map[4]) ); CONDITIONAL(eip17.loop_map[4] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[96] ALPA: 0x%X", eip17.loop_map[4]) ); CONDITIONAL(eip17.loop_map[5] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[05] ALPA: 0x%X", eip17.loop_map[5]) ); CONDITIONAL(eip17.loop_map[5] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[97] ALPA: 0x%X", eip17.loop_map[5]) ); CONDITIONAL(eip17.loop_map[6] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[06] ALPA: 0x%X", eip17.loop_map[6]) ); CONDITIONAL(eip17.loop_map[6] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[98] ALPA: 0x%X", eip17.loop_map[6]) ); CONDITIONAL(eip17.loop_map[7] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[07] ALPA: 0x%X", eip17.loop_map[7]) ); CONDITIONAL(eip17.loop_map[7] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[99] ALPA: 0x%X", eip17.loop_map[7]) ); CONDITIONAL(eip17.loop_map[8] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[08] ALPA: 0x%X", eip17.loop_map[8]) ); CONDITIONAL(eip17.loop_map[8] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[100] ALPA: 0x%X", eip17.loop_map[8]) ); CONDITIONAL(eip17.loop_map[9] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[09] ALPA: 0x%X", eip17.loop_map[9]) ); CONDITIONAL(eip17.loop_map[9] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[101] ALPA: 0x%X", eip17.loop_map[9]) ); CONDITIONAL(eip17.loop_map[10] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[10] ALPA: 0x%X", eip17.loop_map[10]) ); CONDITIONAL(eip17.loop_map[10] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[102] ALPA: 0x%X", eip17.loop_map[10]) ); CONDITIONAL(eip17.loop_map[11] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[11] ALPA: 0x%X", eip17.loop_map[11]) ); CONDITIONAL(eip17.loop_map[11] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[103] ALPA: 0x%X", eip17.loop_map[11]) ); CONDITIONAL(eip17.loop_map[12] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[12] ALPA: 0x%X", eip17.loop_map[12]) ); CONDITIONAL(eip17.loop_map[12] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[104] ALPA: 0x%X", eip17.loop_map[12]) ); CONDITIONAL(eip17.loop_map[13] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[13] ALPA: 0x%X", eip17.loop_map[13]) ); CONDITIONAL(eip17.loop_map[13] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[105] ALPA: 0x%X", eip17.loop_map[13]) ); CONDITIONAL(eip17.loop_map[14] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[14] ALPA: 0x%X", eip17.loop_map[14]) ); CONDITIONAL(eip17.loop_map[14] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[106] ALPA: 0x%X", eip17.loop_map[14]) ); CONDITIONAL(eip17.loop_map[15] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[15] ALPA: 0x%X", eip17.loop_map[15]) ); CONDITIONAL(eip17.loop_map[15] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[107] ALPA: 0x%X", eip17.loop_map[15]) ); CONDITIONAL(eip17.loop_map[16] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[16] ALPA: 0x%X", eip17.loop_map[16]) ); CONDITIONAL(eip17.loop_map[16] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[108] ALPA: 0x%X", eip17.loop_map[16]) ); CONDITIONAL(eip17.loop_map[17] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[17] ALPA: 0x%X", eip17.loop_map[17]) ); CONDITIONAL(eip17.loop_map[17] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[109] ALPA: 0x%X", eip17.loop_map[17]) ); CONDITIONAL(eip17.loop_map[18] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[18] ALPA: 0x%X", eip17.loop_map[18]) ); CONDITIONAL(eip17.loop_map[18] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[110] ALPA: 0x%X", eip17.loop_map[18]) ); CONDITIONAL(eip17.loop_map[19] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[19] ALPA: 0x%X", eip17.loop_map[19]) ); CONDITIONAL(eip17.loop_map[19] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[111] ALPA: 0x%X", eip17.loop_map[19]) ); CONDITIONAL(eip17.loop_map[20] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[20] ALPA: 0x%X", eip17.loop_map[20]) ); CONDITIONAL(eip17.loop_map[20] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[112] ALPA: 0x%X", eip17.loop_map[20]) ); CONDITIONAL(eip17.loop_map[21] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[21] ALPA: 0x%X", eip17.loop_map[21]) ); CONDITIONAL(eip17.loop_map[21] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[113] ALPA: 0x%X", eip17.loop_map[21]) ); CONDITIONAL(eip17.loop_map[22] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[22] ALPA: 0x%X", eip17.loop_map[22]) ); CONDITIONAL(eip17.loop_map[22] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[114] ALPA: 0x%X", eip17.loop_map[22]) ); CONDITIONAL(eip17.loop_map[23] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[23] ALPA: 0x%X", eip17.loop_map[23]) ); CONDITIONAL(eip17.loop_map[23] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[115] ALPA: 0x%X", eip17.loop_map[23]) ); CONDITIONAL(eip17.loop_map[24] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[24] ALPA: 0x%X", eip17.loop_map[24]) ); CONDITIONAL(eip17.loop_map[24] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[116] ALPA: 0x%X", eip17.loop_map[24]) ); CONDITIONAL(eip17.loop_map[25] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[25] ALPA: 0x%X", eip17.loop_map[25]) ); CONDITIONAL(eip17.loop_map[25] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[117] ALPA: 0x%X", eip17.loop_map[25]) ); CONDITIONAL(eip17.loop_map[26] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[26] ALPA: 0x%X", eip17.loop_map[26]) ); CONDITIONAL(eip17.loop_map[26] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[118] ALPA: 0x%X", eip17.loop_map[26]) ); CONDITIONAL(eip17.loop_map[27] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[27] ALPA: 0x%X", eip17.loop_map[27]) ); CONDITIONAL(eip17.loop_map[27] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[119] ALPA: 0x%X", eip17.loop_map[27]) ); CONDITIONAL(eip17.loop_map[28] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[28] ALPA: 0x%X", eip17.loop_map[28]) ); CONDITIONAL(eip17.loop_map[28] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[120] ALPA: 0x%X", eip17.loop_map[28]) ); CONDITIONAL(eip17.loop_map[29] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[29] ALPA: 0x%X", eip17.loop_map[29]) ); CONDITIONAL(eip17.loop_map[29] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[121] ALPA: 0x%X", eip17.loop_map[29]) ); CONDITIONAL(eip17.loop_map[30] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[30] ALPA: 0x%X", eip17.loop_map[30]) ); CONDITIONAL(eip17.loop_map[30] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[122] ALPA: 0x%X", eip17.loop_map[30]) ); CONDITIONAL(eip17.loop_map[31] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[31] ALPA: 0x%X", eip17.loop_map[31]) ); CONDITIONAL(eip17.loop_map[31] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[123] ALPA: 0x%X", eip17.loop_map[31]) ); CONDITIONAL(eip17.loop_map[32] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[32] ALPA: 0x%X", eip17.loop_map[32]) ); CONDITIONAL(eip17.loop_map[32] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[124] ALPA: 0x%X", eip17.loop_map[32]) ); CONDITIONAL(eip17.loop_map[33] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[33] ALPA: 0x%X", eip17.loop_map[33]) ); CONDITIONAL(eip17.loop_map[33] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[125] ALPA: 0x%X", eip17.loop_map[33]) ); CONDITIONAL(eip17.loop_map[34] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[34] ALPA: 0x%X", eip17.loop_map[34]) ); CONDITIONAL(eip17.loop_map[34] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[126] ALPA: 0x%X", eip17.loop_map[34]) ); CONDITIONAL(eip17.loop_map[35] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[35] ALPA: 0x%X", eip17.loop_map[35]) ); CONDITIONAL(eip17.loop_map[35] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[127] ALPA: 0x%X", eip17.loop_map[35]) ); CONDITIONAL(eip17.loop_map[36] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[36] ALPA: 0x%X", eip17.loop_map[36]) ); CONDITIONAL(eip17.loop_map[36] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[128] ALPA: 0x%X", eip17.loop_map[36]) ); CONDITIONAL(eip17.loop_map[37] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[37] ALPA: 0x%X", eip17.loop_map[37]) ); CONDITIONAL(eip17.loop_map[37] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[129] ALPA: 0x%X", eip17.loop_map[37]) ); CONDITIONAL(eip17.loop_map[38] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[38] ALPA: 0x%X", eip17.loop_map[38]) ); CONDITIONAL(eip17.loop_map[38] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[130] ALPA: 0x%X", eip17.loop_map[38]) ); CONDITIONAL(eip17.loop_map[39] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[39] ALPA: 0x%X", eip17.loop_map[39]) ); CONDITIONAL(eip17.loop_map[39] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[131] ALPA: 0x%X", eip17.loop_map[39]) ); CONDITIONAL(eip17.loop_map[40] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[40] ALPA: 0x%X", eip17.loop_map[40]) ); CONDITIONAL(eip17.loop_map[40] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[132] ALPA: 0x%X", eip17.loop_map[40]) ); CONDITIONAL(eip17.loop_map[41] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[41] ALPA: 0x%X", eip17.loop_map[41]) ); CONDITIONAL(eip17.loop_map[41] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[133] ALPA: 0x%X", eip17.loop_map[41]) ); CONDITIONAL(eip17.loop_map[42] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[42] ALPA: 0x%X", eip17.loop_map[42]) ); CONDITIONAL(eip17.loop_map[42] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[134] ALPA: 0x%X", eip17.loop_map[42]) ); CONDITIONAL(eip17.loop_map[43] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[43] ALPA: 0x%X", eip17.loop_map[43]) ); CONDITIONAL(eip17.loop_map[43] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[135] ALPA: 0x%X", eip17.loop_map[43]) ); CONDITIONAL(eip17.loop_map[44] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[44] ALPA: 0x%X", eip17.loop_map[44]) ); CONDITIONAL(eip17.loop_map[44] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[136] ALPA: 0x%X", eip17.loop_map[44]) ); CONDITIONAL(eip17.loop_map[45] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[45] ALPA: 0x%X", eip17.loop_map[45]) ); CONDITIONAL(eip17.loop_map[45] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[137] ALPA: 0x%X", eip17.loop_map[45]) ); CONDITIONAL(eip17.loop_map[46] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[46] ALPA: 0x%X", eip17.loop_map[46]) ); CONDITIONAL(eip17.loop_map[46] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[138] ALPA: 0x%X", eip17.loop_map[46]) ); CONDITIONAL(eip17.loop_map[47] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[47] ALPA: 0x%X", eip17.loop_map[47]) ); CONDITIONAL(eip17.loop_map[47] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[139] ALPA: 0x%X", eip17.loop_map[47]) ); CONDITIONAL(eip17.loop_map[48] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[48] ALPA: 0x%X", eip17.loop_map[48]) ); CONDITIONAL(eip17.loop_map[48] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[140] ALPA: 0x%X", eip17.loop_map[48]) ); CONDITIONAL(eip17.loop_map[49] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[49] ALPA: 0x%X", eip17.loop_map[49]) ); CONDITIONAL(eip17.loop_map[49] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[141] ALPA: 0x%X", eip17.loop_map[49]) ); CONDITIONAL(eip17.loop_map[50] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[50] ALPA: 0x%X", eip17.loop_map[50]) ); CONDITIONAL(eip17.loop_map[50] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[142] ALPA: 0x%X", eip17.loop_map[50]) ); CONDITIONAL(eip17.loop_map[51] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[51] ALPA: 0x%X", eip17.loop_map[51]) ); CONDITIONAL(eip17.loop_map[51] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[143] ALPA: 0x%X", eip17.loop_map[51]) ); CONDITIONAL(eip17.loop_map[52] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[52] ALPA: 0x%X", eip17.loop_map[52]) ); CONDITIONAL(eip17.loop_map[52] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[144] ALPA: 0x%X", eip17.loop_map[52]) ); CONDITIONAL(eip17.loop_map[53] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[53] ALPA: 0x%X", eip17.loop_map[53]) ); CONDITIONAL(eip17.loop_map[53] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[145] ALPA: 0x%X", eip17.loop_map[53]) ); CONDITIONAL(eip17.loop_map[54] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[54] ALPA: 0x%X", eip17.loop_map[54]) ); CONDITIONAL(eip17.loop_map[54] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[146] ALPA: 0x%X", eip17.loop_map[54]) ); CONDITIONAL(eip17.loop_map[55] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[55] ALPA: 0x%X", eip17.loop_map[55]) ); CONDITIONAL(eip17.loop_map[55] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[147] ALPA: 0x%X", eip17.loop_map[55]) ); CONDITIONAL(eip17.loop_map[56] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[56] ALPA: 0x%X", eip17.loop_map[56]) ); CONDITIONAL(eip17.loop_map[56] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[148] ALPA: 0x%X", eip17.loop_map[56]) ); CONDITIONAL(eip17.loop_map[57] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[57] ALPA: 0x%X", eip17.loop_map[57]) ); CONDITIONAL(eip17.loop_map[57] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[149] ALPA: 0x%X", eip17.loop_map[57]) ); CONDITIONAL(eip17.loop_map[58] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[58] ALPA: 0x%X", eip17.loop_map[58]) ); CONDITIONAL(eip17.loop_map[58] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[150] ALPA: 0x%X", eip17.loop_map[58]) ); CONDITIONAL(eip17.loop_map[59] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[59] ALPA: 0x%X", eip17.loop_map[59]) ); CONDITIONAL(eip17.loop_map[59] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[151] ALPA: 0x%X", eip17.loop_map[59]) ); CONDITIONAL(eip17.loop_map[60] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[60] ALPA: 0x%X", eip17.loop_map[60]) ); CONDITIONAL(eip17.loop_map[60] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[152] ALPA: 0x%X", eip17.loop_map[60]) ); CONDITIONAL(eip17.loop_map[61] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[61] ALPA: 0x%X", eip17.loop_map[61]) ); CONDITIONAL(eip17.loop_map[61] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[153] ALPA: 0x%X", eip17.loop_map[61]) ); CONDITIONAL(eip17.loop_map[62] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[62] ALPA: 0x%X", eip17.loop_map[62]) ); CONDITIONAL(eip17.loop_map[62] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[154] ALPA: 0x%X", eip17.loop_map[62]) ); CONDITIONAL(eip17.loop_map[63] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[63] ALPA: 0x%X", eip17.loop_map[63]) ); CONDITIONAL(eip17.loop_map[63] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[155] ALPA: 0x%X", eip17.loop_map[63]) ); CONDITIONAL(eip17.loop_map[64] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[64] ALPA: 0x%X", eip17.loop_map[64]) ); CONDITIONAL(eip17.loop_map[64] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[156] ALPA: 0x%X", eip17.loop_map[64]) ); CONDITIONAL(eip17.loop_map[65] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[65] ALPA: 0x%X", eip17.loop_map[65]) ); CONDITIONAL(eip17.loop_map[65] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[157] ALPA: 0x%X", eip17.loop_map[65]) ); CONDITIONAL(eip17.loop_map[66] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[66] ALPA: 0x%X", eip17.loop_map[66]) ); CONDITIONAL(eip17.loop_map[66] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[158] ALPA: 0x%X", eip17.loop_map[66]) ); CONDITIONAL(eip17.loop_map[67] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[67] ALPA: 0x%X", eip17.loop_map[67]) ); CONDITIONAL(eip17.loop_map[67] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[159] ALPA: 0x%X", eip17.loop_map[67]) ); CONDITIONAL(eip17.loop_map[68] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[68] ALPA: 0x%X", eip17.loop_map[68]) ); CONDITIONAL(eip17.loop_map[68] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[160] ALPA: 0x%X", eip17.loop_map[68]) ); CONDITIONAL(eip17.loop_map[69] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[69] ALPA: 0x%X", eip17.loop_map[69]) ); CONDITIONAL(eip17.loop_map[69] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[161] ALPA: 0x%X", eip17.loop_map[69]) ); CONDITIONAL(eip17.loop_map[70] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[70] ALPA: 0x%X", eip17.loop_map[70]) ); CONDITIONAL(eip17.loop_map[70] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[162] ALPA: 0x%X", eip17.loop_map[70]) ); CONDITIONAL(eip17.loop_map[71] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[71] ALPA: 0x%X", eip17.loop_map[71]) ); CONDITIONAL(eip17.loop_map[71] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[163] ALPA: 0x%X", eip17.loop_map[71]) ); CONDITIONAL(eip17.loop_map[72] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[72] ALPA: 0x%X", eip17.loop_map[72]) ); CONDITIONAL(eip17.loop_map[72] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[164] ALPA: 0x%X", eip17.loop_map[72]) ); CONDITIONAL(eip17.loop_map[73] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[73] ALPA: 0x%X", eip17.loop_map[73]) ); CONDITIONAL(eip17.loop_map[73] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[165] ALPA: 0x%X", eip17.loop_map[73]) ); CONDITIONAL(eip17.loop_map[74] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[74] ALPA: 0x%X", eip17.loop_map[74]) ); CONDITIONAL(eip17.loop_map[74] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[166] ALPA: 0x%X", eip17.loop_map[74]) ); CONDITIONAL(eip17.loop_map[75] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[75] ALPA: 0x%X", eip17.loop_map[75]) ); CONDITIONAL(eip17.loop_map[75] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[167] ALPA: 0x%X", eip17.loop_map[75]) ); CONDITIONAL(eip17.loop_map[76] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[76] ALPA: 0x%X", eip17.loop_map[76]) ); CONDITIONAL(eip17.loop_map[76] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[168] ALPA: 0x%X", eip17.loop_map[76]) ); CONDITIONAL(eip17.loop_map[77] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[77] ALPA: 0x%X", eip17.loop_map[77]) ); CONDITIONAL(eip17.loop_map[77] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[169] ALPA: 0x%X", eip17.loop_map[77]) ); CONDITIONAL(eip17.loop_map[78] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[78] ALPA: 0x%X", eip17.loop_map[78]) ); CONDITIONAL(eip17.loop_map[78] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[170] ALPA: 0x%X", eip17.loop_map[78]) ); CONDITIONAL(eip17.loop_map[79] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[79] ALPA: 0x%X", eip17.loop_map[79]) ); CONDITIONAL(eip17.loop_map[79] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[171] ALPA: 0x%X", eip17.loop_map[79]) ); CONDITIONAL(eip17.loop_map[80] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[80] ALPA: 0x%X", eip17.loop_map[80]) ); CONDITIONAL(eip17.loop_map[80] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[172] ALPA: 0x%X", eip17.loop_map[80]) ); CONDITIONAL(eip17.loop_map[81] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[81] ALPA: 0x%X", eip17.loop_map[81]) ); CONDITIONAL(eip17.loop_map[81] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[173] ALPA: 0x%X", eip17.loop_map[81]) ); CONDITIONAL(eip17.loop_map[82] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[82] ALPA: 0x%X", eip17.loop_map[82]) ); CONDITIONAL(eip17.loop_map[82] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[174] ALPA: 0x%X", eip17.loop_map[82]) ); CONDITIONAL(eip17.loop_map[83] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[83] ALPA: 0x%X", eip17.loop_map[83]) ); CONDITIONAL(eip17.loop_map[83] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[175] ALPA: 0x%X", eip17.loop_map[83]) ); CONDITIONAL(eip17.loop_map[84] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[84] ALPA: 0x%X", eip17.loop_map[84]) ); CONDITIONAL(eip17.loop_map[84] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[176] ALPA: 0x%X", eip17.loop_map[84]) ); CONDITIONAL(eip17.loop_map[85] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[85] ALPA: 0x%X", eip17.loop_map[85]) ); CONDITIONAL(eip17.loop_map[85] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[177] ALPA: 0x%X", eip17.loop_map[85]) ); CONDITIONAL(eip17.loop_map[86] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[86] ALPA: 0x%X", eip17.loop_map[86]) ); CONDITIONAL(eip17.loop_map[86] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[178] ALPA: 0x%X", eip17.loop_map[86]) ); CONDITIONAL(eip17.loop_map[87] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[87] ALPA: 0x%X", eip17.loop_map[87]) ); CONDITIONAL(eip17.loop_map[87] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[179] ALPA: 0x%X", eip17.loop_map[87]) ); CONDITIONAL(eip17.loop_map[88] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[88] ALPA: 0x%X", eip17.loop_map[88]) ); CONDITIONAL(eip17.loop_map[88] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[180] ALPA: 0x%X", eip17.loop_map[88]) ); CONDITIONAL(eip17.loop_map[89] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[89] ALPA: 0x%X", eip17.loop_map[89]) ); CONDITIONAL(eip17.loop_map[89] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[181] ALPA: 0x%X", eip17.loop_map[89]) ); CONDITIONAL(eip17.loop_map[90] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[90] ALPA: 0x%X", eip17.loop_map[90]) ); CONDITIONAL(eip17.loop_map[90] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[182] ALPA: 0x%X", eip17.loop_map[90]) ); CONDITIONAL(eip17.loop_map[91] != 0xFF && eip17.page == 1, TRANSLATE("Loop Map[91] ALPA: 0x%X", eip17.loop_map[91]) ); CONDITIONAL(eip17.loop_map[91] != 0xFF && eip17.page == 2, TRANSLATE("Loop Map[183] ALPA: 0x%X", eip17.loop_map[91]) ); ENDTRANSLATIONBLOCK EC BLOCK: 06420009 SCID_FCS_PASSTHRU_CMD TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06440008 SCID_FCS_LOOP_RECOVERY_SHELF TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf); ENDTRANSLATIONBLOCK EC BLOCK: 06450008 SCID_FCS_LOOP_RECOVERY_SUSPECT TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Cabinet ID: %d", eip08.recovery.cab); TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf); TRANSLATE("Bay: %d", eip08.recovery.slot); ENDTRANSLATIONBLOCK EC BLOCK: 06460008 SCID_FCS_LOOP_RECOVERY_CAB_ERROR TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06480008 SCID_FCS_LOOP_RECOVERY_BYPASS_FAILURE TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Unbypass Failure Enclosure Mask: %x", eip08.failure_cause); ENDTRANSLATIONBLOCK EC BLOCK: 06490008 SCID_FCS_ENCLOSURE_RECOVERY_ENTERED TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Cab: %d, Enclosure %d", eip08.recovery.cab, eip08.recovery.shelf); ENDTRANSLATIONBLOCK EC BLOCK: 064a0008 SCID_FCS_ENCLOSURE_RECOVERY_EXIT TRANSLATIONBLOCK TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id); TRANSLATE("Cab: %d, Enclosure %d", eip08.recovery.cab, eip08.recovery.shelf); TRANSLATE("Recovery Status: %x", eip08.failure_cause); ENDTRANSLATIONBLOCK EC BLOCK: 064b0008 SCID_FCS_LOOP_RECOVERY TRANSLATIONBLOCK TRANSLATE("Loop Recoveries Flag: %d", eip08.recovery.progress); CONDITIONAL(eip08.recovery.progress == 0x01, TRANSLATE("ENABLE Loop Recovery Operations")); CONDITIONAL(eip08.recovery.progress == 0x00, TRANSLATE("DISABLE Loop Recovery Operations")); ENDTRANSLATIONBLOCK EC BLOCK: 064c0004 SCID_FCS_DSL_DRIVE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("Failure Reason Code: %d", eip04.bypass_reason); ENDTRANSLATIONBLOCK EC BLOCK: 064d0008 SCID_FCS_CODELOAD_COMPLETE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 064e0009 SCID_FCS_NON_ZERO_RSP_CODE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip09.device); TRANSLATE("Port ID: %s", eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE("Bay: %d.", eip09.bay) ); TRANSLATE("AL_PA: 0x%04x", eip09.al_pa); TRANSLATE("%s", XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( "RSP Code: 0x%02x", eip09.error.sense_data.fru_code ); TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa); TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0700b515 SCID_CS_ALLOCATION_STALL TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip15.tag1); TRANSLATE("Disk Group: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 0, TRANSLATE("State: Attempting to retry allocation") ); CONDITIONAL(eip15.state == 1, TRANSLATE("State: Awaiting a leveling event") ); ENDTRANSLATIONBLOCK EC BLOCK: 0701b515 SCID_CS_EXPANSION_STALL TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip15.tag1); TRANSLATE("Disk Group: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 0, TRANSLATE("State: Attempting to retry allocation") ); CONDITIONAL(eip15.state == 1, TRANSLATE("State: Awaiting a leveling event") ); ENDTRANSLATIONBLOCK EC BLOCK: 07020015 SCID_CS_LEVELING_START TRANSLATIONBLOCK TRANSLATE("Disk Group: %[tag]", eip15.tag1); ENDTRANSLATIONBLOCK EC BLOCK: 07030015 SCID_CS_LEVELING_END TRANSLATIONBLOCK TRANSLATE("Disk Group: %[tag]", eip15.tag1); CONDITIONAL(eip15.state == 0, TRANSLATE("Not Level"), TRANSLATE("Level") ); CONDITIONAL(eip15.status == 0, TRANSLATE("No Data Moved"), TRANSLATE("Data Moved") ); ENDTRANSLATIONBLOCK EC BLOCK: 07040015 SCID_CS_MEMBER_MANAGER_OP_START TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE("State: Reconstructing") ); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.state == 6, TRANSLATE("State: Reverting") ); ENDTRANSLATIONBLOCK EC BLOCK: 07050015 SCID_CS_MEMBER_MANAGER_OP_END TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE("State: Reconstructing") ); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.state == 6, TRANSLATE("State: Reverting") ); CONDITIONAL(eip15.status == 1, TRANSLATE("Status: success") ); CONDITIONAL(eip15.status == 2, TRANSLATE("Status: RAID0 reconstruct failed") ); CONDITIONAL(eip15.status == 4, TRANSLATE("Status: RAID5 reconstruct failed") ); CONDITIONAL(eip15.status == 8, TRANSLATE("Status: RAID1 reconstruct failed") ); ENDTRANSLATIONBLOCK EC BLOCK: 07060015 SCID_CS_MIGRATION_START TRANSLATIONBLOCK TRANSLATE("Disk Group: %[tag]", eip15.tag1); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Merge began") ); CONDITIONAL(eip15.state == 8, TRANSLATE("State: Split began") ); ENDTRANSLATIONBLOCK EC BLOCK: 07070015 SCID_CS_MIGRATION_END TRANSLATIONBLOCK TRANSLATE("Disk Group: %[tag]", eip15.tag1); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Merge complete") ); CONDITIONAL(eip15.state == 8, TRANSLATE("State: Split complete") ); ENDTRANSLATIONBLOCK EC BLOCK: 07080015 SCID_CS_DELETION_FAILED TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip15.tag1); TRANSLATE("Disk group: %[tag]", eip15.tag2); TRANSLATE("Status: %d", eip15.status); ENDTRANSLATIONBLOCK EC BLOCK: 0709b515 SCID_CS_MEMBER_MANAGER_OP_STALL TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.status == 1, TRANSLATE("Status: Awaiting additional storage") ); ENDTRANSLATIONBLOCK EC BLOCK: 070a0015 SCID_CS_MEMBER_MANAGER_OP_RESTART TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.status == 0, TRANSLATE("Status: Retrying the operation") ); ENDTRANSLATIONBLOCK EC BLOCK: 070b0015 SCID_CS_METADATA_INCONSISTENCY TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); CONDITIONAL(eip15.tag2 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Logical Disk identity unavailable"), TRANSLATE("Logical Disk: %[tag]", eip15.tag2) ); CONDITIONAL(eip15.state == 0, TRANSLATE("State: Physical Segment Deallocated") ); CONDITIONAL(eip15.state == 1, TRANSLATE("State: Unreferenced Physical Segment") ); CONDITIONAL(eip15.state == 2, TRANSLATE("State: Multi-referenced Physical Segment") ); CONDITIONAL(eip15.state == 3, TRANSLATE("State: NULL rsdm_ptr in update_lmap_shared") ); CONDITIONAL(eip15.status == 0, TRANSLATE("Status: OK") ); CONDITIONAL(eip15.status == 1, TRANSLATE("Status: FAILURE") ); CONDITIONAL(eip15.status == 3 && eip15.state == 3, TRANSLATE("LD is overcommitted") ); ENDTRANSLATIONBLOCK EC BLOCK: 070d0015 SCID_CS_MEMBER_MANAGER_OP_ERROR TRANSLATIONBLOCK TRANSLATE("Logical Disk: %[tag]", eip15.tag1); TRANSLATE("Volume: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE("State: Reconstructing") ); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.state == 6, TRANSLATE("State: Reverting") ); TRANSLATE("Error: 0x%x", eip15.status); TRANSLATE("Error: 0x01 = Missing Drive"); TRANSLATE("Error: 0x02 = Invalid RAID type"); TRANSLATE("Error: 0x04 = Invalid member management opeartion"); TRANSLATE("Error: 0x08 = Invalid RStore"); TRANSLATE("Error: 0x10 = LD Realization Failed"); ENDTRANSLATIONBLOCK EC BLOCK: 09010005 SCID_SCMI_PS_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09020005 SCID_SCMI_VOL_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]", eip05.add_handle ); TRANSLATE( "State: %[scmi_volume_condition] --> %[scmi_volume_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 09030005 SCID_SCMI_LDISK_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09040005 SCID_SCMI_NSC_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09050005 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE("Controller containing battery: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0906bf05 SCID_SCMI_VOL_CONDITION_CHANGE_MISSING TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]", eip05.add_handle ); TRANSLATE( "State: %[scmi_volume_condition] --> %[scmi_volume_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 09070005 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE("Fibre Channel port: %s (%d.)", eip05.attribute.value.str, eip05.secondary_id ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0908b405 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE("State: Normal --> Threshold reached"); ENDTRANSLATIONBLOCK EC BLOCK: 09090005 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_SUFFICIENT TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]", eip05.add_handle ); TRANSLATE( "State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resource_availability_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 090a0005 SCID_SCMI_LDISK_DATA_LOST_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_data_availability_condition] --> %[scmi_logical_disk_data_availability_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 090c0005 SCID_SCMI_LDISK_SNAPCLONE_UNSHARE_DONE TRANSLATIONBLOCK TRANSLATE("Snapclone Logical Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Noid of parent internal Logical Disk: 0x%04x", eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 090d0005 SCID_SCMI_VOL_QUORUM_DISK_CHANGE TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_volume_quorum_disk_condition] --> %[scmi_volume_quorum_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 090e3605 SCID_SCMI_NSC_TEMP_TRIP_REACHED TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Sensor 1 current temperature: %d. degrees Celsius", eip05.value.ul1 ); TRANSLATE( "Sensor 2 adjusted temperature: %d. degrees Celsius", eip05.value.ul2 ); TRANSLATE( "Trip point temperature: %d. degrees Celsius", eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 090f2e05 SCID_SCMI_NSC_CLOSE_TO_TEMP_TRIP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Sensor 1 current temperature: %d. degrees Celsius", eip05.value.ul1 ); TRANSLATE( "Sensor 2 adjusted temperature: %d. degrees Celsius", eip05.value.ul2 ); TRANSLATE( "Trip point temperature: %d. degrees Celsius", eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 09110005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09122405 SCID_SCMI_NSC_FANA_SPEED_SLOW TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09132005 SCID_SCMI_NSC_VOLTAGE_OUT_OF_RANGE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Out of range voltage: %d. millivolts", eip05.value.ul1); TRANSLATE("Voltage threshold: %d. millivolts", eip05.secondary_id); TRANSLATE("DIMM size: %d MB", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0914bf05 SCID_SCMI_VOL_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_volume_condition] --> %[scmi_volume_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 0915b905 SCID_SCMI_NSC_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09160005 SCID_SCMI_NSC_TEMP_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Sensor 1 current temperature: %d. degrees Celsius", eip05.value.ul1 ); TRANSLATE( "Sensor 2 adjusted temperature: %d. degrees Celsius", eip05.value.ul2 ); ENDTRANSLATIONBLOCK EC BLOCK: 09172805 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09180005 SCID_SCMI_NSC_BATTERYA_IN_USE_CHANGE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09190005 SCID_SCMI_NSC_VOLTAGE_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Normal range voltage: %d. millivolts", eip05.value.ul1); TRANSLATE("Voltage threshold: %d. millivolts", eip05.secondary_id); ENDTRANSLATIONBLOCK EC BLOCK: 091a2005 SCID_SCMI_NSC_VOLTAGE_REGULATOR_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("DIMM size: %d MB", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 091b0005 SCID_SCMI_LDAD_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091c0005 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER_NORMAL TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE("State: Threshold reached --> Normal"); ENDTRANSLATIONBLOCK EC BLOCK: 091d2205 SCID_SCMI_NSC_BATTERYA_BAD TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091e0005 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091f2905 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09200005 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09210005 SCID_SCMI_NSC_BATTERYB_IN_USE_CHANGE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09222305 SCID_SCMI_NSC_BATTERYB_BAD TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Battery assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09232b05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09240005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09252505 SCID_SCMI_NSC_FANB_SPEED_SLOW TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09262c05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09270005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09282d05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09290005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 092a2605 SCID_SCMI_NSC_FANA_SPEED_SLOW__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 092b2705 SCID_SCMI_NSC_FANB_SPEED_SLOW__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 092c2f05 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_BAD TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 092dbf05 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_INSUFFICIENT TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]", eip05.add_handle ); TRANSLATE( "State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resource_availability_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 092e0005 SCID_SCMI_NSC_LOGIN_FAILURE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Storage System Management Interface command: %[scmi_object_function_code]", eip05.value.ul1 ); TRANSLATE("Host Adapter: %[scmi_obj_hnd]", eip05.attribute.value.obj.handle); TRANSLATE( "Reject reason: %[scmi_response_status_value]", eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 092f0005 SCID_SCMI_NSC_COMMAND_ERROR_RETURN TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Storage System Management Interface command: %[scmi_object_function_code]", eip05.value.ul1 ); TRANSLATE( "Return code: %[scmi_response_status_value]", eip05.value.ul2 ); TRANSLATE( "Internal command version: 0x%08x", eip05.secondary_id ); TRANSLATE( "Internal target: %[scmi_obj_hnd]", eip05.add_handle ); TRANSLATE( "scmicp.parms.u32[0]: %d", eip05.attribute.value.u32[0] ); TRANSLATE( "scmicp.parms.u32[1]: %d", eip05.attribute.value.u32[1] ); TRANSLATE( "scmicp.parms.u32[2]: %d", eip05.attribute.value.u32[2] ); TRANSLATE( "scmicp.parms.u32[3]: %d", eip05.attribute.value.u32[3] ); TRANSLATE( "scmicp.parms.u32[4]: %d", eip05.attribute.value.u32[4] ); TRANSLATE( "scmicp.parms.u32[5]: %d", eip05.attribute.value.u32[5] ); TRANSLATE( "Remote Error: %d", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09300005 SCID_SCMI_NSC_LOOP_MAPGEN_CHANGE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Loop pair: %d.", eip05.secondary_id); TRANSLATE( "Map generation number change: %d. --> %d.", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09314205 SCID_SCMI_PS_CONDITION_CHANGE_DEGRADED TRANSLATIONBLOCK TRANSLATE("physical disk drive: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09324005 SCID_SCMI_PS_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE("physical disk drive: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0933000e SCID_SCMI_DU_CREATED TRANSLATIONBLOCK TRANSLATE("Derived Unit: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Associated Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.attribute.value.obj.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0934000e SCID_SCMI_LDISK_CREATED TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE( "Disk Group: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Size in blocks: %y.", eip0E.attribute.value.u64[0] ); TRANSLATE( "Redundancy type: %[scmi_logical_disk_redundancy_type]", eip0E.attribute.value.u32[2] ); TRANSLATE( "%[scmi_logical_disk_type]", eip0E.attribute.value.u32[3] ); ENDTRANSLATIONBLOCK EC BLOCK: 0935000e SCID_SCMI_LDAD_CREATED TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip0E.handle ); TRANSLATE("Number of disks in group: %d.", eip0E.attribute.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0936000e SCID_SCMI_PS_DISCOVERED TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0937000e SCID_SCMI_PU_CREATED TRANSLATIONBLOCK TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE( "Associated Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.attribute.value.obj.handle ); TRANSLATE( "Host path: %[scmi_obj_hnd]", eip0E.add_handle2 ); TRANSLATE( "Host LUN number [0]: 0x%08x", eip0E.add_data[0] ); TRANSLATE( "Host LUN number [1]: 0x%08x", eip0E.add_data[1] ); ENDTRANSLATIONBLOCK EC BLOCK: 0938000e SCID_SCMI_SCELL_CLIENT_CREATED TRANSLATIONBLOCK TRANSLATE( "Storage System Host Path: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0939000e SCID_SCMI_SCVD_CREATED TRANSLATIONBLOCK TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 093a000e SCID_SCMI_VOL_CREATED TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]", eip0E.add_handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 093b000e SCID_SCMI_DU_DELETED TRANSLATIONBLOCK TRANSLATE("Derived unit: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE( "Associated Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.attribute.value.obj.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 093c000e SCID_SCMI_LDISK_DELETED TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.handle); ENDTRANSLATIONBLOCK EC BLOCK: 093d000e SCID_SCMI_LDAD_DELETED TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 093e420e SCID_SCMI_PS_DISAPPEARED TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 093f000e SCID_SCMI_PU_DELETED TRANSLATIONBLOCK TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE( "Associated Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.attribute.value.obj.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0940000e SCID_SCMI_SCELL_CLIENT_DELETED TRANSLATIONBLOCK TRANSLATE( "Storage System Host Path: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0941000e SCID_SCMI_SCVD_DELETED TRANSLATIONBLOCK TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0E.handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0943000e SCID_SCMI_SCELL_OTHER_JOINED TRANSLATIONBLOCK CONDITIONAL( eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Controller ID not available"), TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0944ba0e SCID_SCMI_SCELL_OTHER_GONE TRANSLATIONBLOCK CONDITIONAL( eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Controller ID not available"), TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0945000e SCID_SCMI_SCELL_DELETED TRANSLATIONBLOCK CONDITIONAL( eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Storage System ID not available"), TRANSLATE("Storage System: %[scmi_obj_hnd]", eip0E.add_handle ) ); CONDITIONAL( eip0E.add_handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Controller ID not available"), TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.add_handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0946000e SCID_SCMI_GROUP_CREATED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0E.handle ); TRANSLATE( "Mode: %[scmi_group_drm_mode]",eip0E.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0947000e SCID_SCMI_GROUP_DELETED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0948000e SCID_SCMI_SNAP_LD_CREATED TRANSLATIONBLOCK TRANSLATE("Associated snapshot Virtual Disk: %[scmi_obj_hnd]", eip0E.handle ); TRANSLATE( "Disk Group: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Size in blocks: %y.", eip0E.attribute.value.u64[0] ); TRANSLATE( "Redundancy type: %[scmi_logical_disk_redundancy_type]", eip0E.attribute.value.u32[2] ); TRANSLATE("Parent Logical Disk: %[scmi_obj_hnd]", eip0E.add_handle2); ENDTRANSLATIONBLOCK EC BLOCK: 0949000e SCID_SCMI_CLONE_LD_CREATED TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk copy: %[scmi_obj_hnd]", eip0E.handle ); TRANSLATE( "Disk Group: %[scmi_obj_hnd]", eip0E.add_handle ); TRANSLATE( "Size in blocks: %y.", eip0E.attribute.value.u64[0] ); TRANSLATE( "Redundancy type: %[scmi_logical_disk_redundancy_type]", eip0E.attribute.value.u32[2] ); TRANSLATE("Parent Logical Disk: %[scmi_obj_hnd]", eip0E.add_handle2); ENDTRANSLATIONBLOCK EC BLOCK: 094a000e SCID_SCMI_GROUP_DELETE_INCOMPLETE TRANSLATIONBLOCK TRANSLATE( "Destination Data Replication Group: %[scmi_obj_hnd]", eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 094b000e SCID_SCMI_VOL_REMOVED TRANSLATIONBLOCK TRANSLATE("Volume: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Associated Disk Group: %[scmi_obj_hnd]", eip0E.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 094c000e SCID_SCMI_RMTNODE_CREATED TRANSLATIONBLOCK TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Storage System UUID: %[scmi_obj_hnd]", eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 094d000e SCID_SCMI_RMTNODE_DELETED TRANSLATIONBLOCK TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Storage System UUID: %[scmi_obj_hnd]", eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 094e000e SCID_SCMI_RMTNODE_UPDATED TRANSLATIONBLOCK TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle); TRANSLATE("Storage System UUID: %[scmi_obj_hnd]", eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 0965000f SCID_SCMI_SCELL_CLIENT_MODE_CHANGE TRANSLATIONBLOCK TRANSLATE( "Storage System Host Path: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Mode: %[scmi_client_mode] --> %[scmi_client_mode]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0966000f SCID_SCMI_STORAGECELL_TIME_SET TRANSLATIONBLOCK CONDITIONAL( eip0F.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE( "Storage System identity unavailable" ), TRANSLATE( "Storage System: %[scmi_obj_hnd]", eip0F.handle ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0967000f SCID_SCMI_PU_LUN_CHANGE TRANSLATIONBLOCK TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0F.handle); TRANSLATE( "LUN: %y. --> %y.", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE("Storage System Virtual Disk noid: 0x%04x", eip0F.secondary_id.Id); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0968000f SCID_SCMI_STORAGECELL_DEV_ADDITION_CHANGE TRANSLATIONBLOCK TRANSLATE( "Storage System: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Policy: %[scmi_storagecell_device_addition_policy] --> %[scmi_storagecell_device_addition_policy]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0969000f SCID_SCMI_SCVD_QUIESCED_CHANGE TRANSLATIONBLOCK TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); TRANSLATE( "State: %[scmi_scvd_quiescent_condition] --> %[scmi_scvd_quiescent_condition]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 096a000f SCID_SCMI_SCVD_STATE_CHANGE TRANSLATIONBLOCK TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); TRANSLATE( "State: %[scmi_state] --> %[scmi_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 096b000f SCID_SCMI_SCVD_CACHE_POLICY_CHANGE TRANSLATIONBLOCK TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); TRANSLATE( "Write cache policy: %[scmi_write_disk_cache_policy_type] --> %[scmi_write_disk_cache_policy_type]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE( "Read cache policy: %[scmi_read_disk_cache_policy_type] --> %[scmi_read_disk_cache_policy_type]", eip0F.old_attr.value.u32[1], eip0F.new_attr.value.u32[1] ); TRANSLATE( "Cache mirroring policy: %[scmi_mirror_disk_cache_policy_type] --> %[scmi_mirror_disk_cache_policy_type]", eip0F.old_attr.value.u32[2], eip0F.new_attr.value.u32[2] ); ENDTRANSLATIONBLOCK EC BLOCK: 096c000f SCID_SCMI_VOL_USAGE_CHANGE TRANSLATIONBLOCK TRANSLATE( "Volume: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_volume_usage] --> %[scmi_volume_usage]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); CONDITIONAL( eip0F.old_attr.value.u32[0] == 1 || eip0F.new_attr.value.u32[0] == 1, TRANSLATE( "Disk Group: %[scmi_obj_hnd]", eip0F.add_handle ) ); TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)", eip0F.secondary_id.rss_data.Id, eip0F.secondary_id.rss_data.Id ); TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)", eip0F.secondary_id.rss_data.Index, eip0F.secondary_id.rss_data.Index ); ENDTRANSLATIONBLOCK EC BLOCK: 096d000f SCID_SCMI_LDAD_SPARE_CHANGE TRANSLATIONBLOCK TRANSLATE( "Disk Group: %[scmi_obj_hnd]", eip0F.handle ); CONDITIONAL( eip0F.new_attr.value.u32[0] > eip0F.old_attr.value.u32[0], TRANSLATE( "Disk Failure Protection Level increased" ), TRANSLATE( "Disk Failure Protection Level decreased" ) ); TRANSLATE( "Disk Failure Protection Level: %d. --> %d.", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 096e000f SCID_SCMI_DU_WRITE_PROTECTED_CHANGE TRANSLATIONBLOCK TRANSLATE("Derived unit: %[scmi_obj_hnd]", eip0F.handle); TRANSLATE( "State: %[scmi_du_write_protect_condition] --> %[scmi_du_write_protect_condition]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE("Storage System Virtual Disk noid: 0x%04x", eip0F.secondary_id.Id); TRANSLATE( "Associated Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0970460f SCID_SCMI_PS_DRIVE_PORT_FAILURE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE("Port: %s", eip0F.new_attr.value.str); CONDITIONAL(eip0F.old_attr.value.u32[1] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE("Enclosure: %d.", eip0F.old_attr.value.u32[1]) ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE("Bay: %d.", eip0F.old_attr.value.u32[2]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0971000f SCID_SCMI_NSC_SHUTDOWN_REQUEST TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip0F.handle); TRANSLATE( "Restart type: %[scmi_nsc_restart_option]", eip0F.old_attr.value.u32[0] ); TRANSLATE( "Other controller action: %[scmi_nsc_shutdown_other_option]", eip0F.old_attr.value.u32[1] ); TRANSLATE( "Controller power state: %[scmi_nsc_shutdown_poweroff_option]", eip0F.old_attr.value.u32[2] ); TRANSLATE( "Physical disk drive enclosures power state: %[scmi_nsc_shutdown_encl_poweroff_option]", eip0F.old_attr.value.u32[3] ); TRANSLATE( "Battery assembly state: %[scmi_nsc_shutdown_battass_option]", eip0F.old_attr.value.u32[4] ); TRANSLATE( "Shutdown delay: %d. seconds", eip0F.old_attr.value.u32[5] ); ENDTRANSLATIONBLOCK EC BLOCK: 0972000f SCID_SCMI_NSC_SHUTDOWN TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip0F.handle); TRANSLATE( "Cache memory shutdown result: %[scmi_shutdown]", eip0F.old_attr.value.u32[0] ); TRANSLATE( "Cache memory shutdown internal status: %d.", eip0F.old_attr.value.u32[1] ); TRANSLATE( "Physical disk drive enclosures power off result: %[scmi_shutdown]", eip0F.old_attr.value.u32[2] ); TRANSLATE( "Physical disk drive enclosures power off internal status: %[scmi_shutdown]", eip0F.old_attr.value.u32[3] ); TRANSLATE( "Battery assemblies disable result: %[scmi_shutdown]", eip0F.old_attr.value.u32[4] ); TRANSLATE( "Battery assemblies disable failure mode: %[scmi_nsc_shutdown_battass_failure_mode]", eip0F.old_attr.value.u32[5] ); ENDTRANSLATIONBLOCK EC BLOCK: 0973000f SCID_SCMI_DRM_FAILSAFE_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_state] --> %[scmi_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0974000f SCID_SCMI_DRM_MODE_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Mode: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0975000f SCID_SCMI_DRM_OPERATION_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Actual State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE( "Requested State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]", eip0F.old_attr.value.u32[1], eip0F.new_attr.value.u32[1] ); TRANSLATE( "Async Rundown State: %[scmi_rundown_flag] --> %[scmi_rundown_flag]", eip0F.old_attr.value.u32[2], eip0F.new_attr.value.u32[2] ); ENDTRANSLATIONBLOCK EC BLOCK: 0976000f SCID_SCMI_DRM_READ_ONLY_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Attribute: %[scmi_group_readonly_type] --> %[scmi_group_readonly_type]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0977000f SCID_SCMI_DRM_SITE_FAILOVER_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Role: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0978000f SCID_SCMI_DRM_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0979000f SCID_SCMI_DRM_SCVD_ADDED_TO_GROUP TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 097a000f SCID_SCMI_DRM_SCVD_REMOVED_FROM_GROUP TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "Storage System Virtual Disk: %[scmi_obj_hnd]", eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 097b000f SCID_SCMI_DRM_AUTO_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_auto_suspend_state] --> %[scmi_group_auto_suspend_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097c000f SCID_SCMI_DRM_DEST_PRESENT_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_dest_present_state] --> %[scmi_group_dest_present_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097d000f SCID_SCMI_PS_FLAGS_CHANGED TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE("Old ps_flags value: 0x%08x.", eip0F.old_attr.value.u32[0]); TRANSLATE("New ps_flags value: 0x%08x.", eip0F.new_attr.value.u32[0]); ENDTRANSLATIONBLOCK EC BLOCK: 097e000f SCID_SCMI_DRM_DEFER_COPY_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_defer_copy_state] --> %[scmi_group_defer_copy_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097f000f SCID_SCMI_DRM_LINK_DOWN_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0980000f SCID_SCMI_DRM_SITE_FAILOVER_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0981000f SCID_SCMI_DRM_DEFER_COPY_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip0F.handle ); TRANSLATE( "State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]", eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09c85105 SCID_SCMI_LDISK_DATA_LOST_CHANGE_DATA_LOST TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_data_availability_condition] --> %[scmi_logical_disk_data_availability_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09c95105 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09ca5105 SCID_SCMI_LDISK_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cb5005 SCID_SCMI_LDISK_CONDITION_CHANGE_OVERCOMMIT TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cc5105 SCID_SCMI_LDISK_CONDITION_CHANGE_DATA_LOST TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cdc305 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Port: %s", eip05.attribute.value.str ); TRANSLATE( "State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]", eip05.value.ul2, eip05.value.ul1 ); TRANSLATE("DIMM size: %d MB", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09ce0005 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP_MARKED TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cf4105 SCID_SCMI_PS_CONDITION_CHANGE_NOT_PRESENT TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09d00005 SCID_SCMI_NSC_ICON_YELLOW_OFF_CHANGE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); ENDTRANSLATIONBLOCK EC BLOCK: 09d1b905 SCID_SCMI_NSC_ICON_YELLOW_ON_CHANGE TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); ENDTRANSLATIONBLOCK EC BLOCK: 09d22a05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE( "State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d35105 SCID_SCMI_DRM_GROUP_INOP TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d40005 SCID_SCMI_DRM_GROUP_OPERATIVE TRANSLATIONBLOCK TRANSLATE( "Data Replication Group: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d50005 SCID_SCMI_PS_CONDITION_CHANGE_SPOF TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[scmi_obj_hnd]", eip05.handle ); TRANSLATE( "State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]", eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09d63705 SCID_SCMI_NSC_TEMP_SNSR_DONT_AGREE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "Sensor 1 current reading: %d. degrees Celsius", eip05.value.ul1 ); TRANSLATE( "Sensor 2 current reading: %d. degrees Celsius", eip05.value.ul2 ); TRANSLATE("DIMM size: %d MB", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09d73705 SCID_SCMI_NSC_TEMP_SNSR_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("I2C status: %x", eip05.value.ul1); TRANSLATE("DIMM size: %d MB", eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09d8b605 SCID_SCMI_SRC_LOST TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 09d90005 SCID_SCMI_SRC_ATTAINED TRANSLATIONBLOCK TRANSLATE("Disk Group: %[scmi_obj_hnd]", eip05.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 09da0005 SCID_SCMI_NSC_FANA_SPEED_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09db0005 SCID_SCMI_NSC_FANB_SPEED_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Blower assembly: %d.", eip05.secondary_id); TRANSLATE("Current speed: %d. RPM", eip05.value.ul1); TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09dc0b05 SCID_SCMI_NSC_POWERDOWN_NEEDED TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("New version: 0x%x.", eip05.value.ul1); TRANSLATE("Old version: 0x%x.", eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09dd0005 SCID_SCMI_NSC_MAINTENANCE_INVOKE_CALL TRANSLATIONBLOCK TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle); TRANSLATE("Function Called: 0x%x.", eip05.value.ul1); TRANSLATE("Parameter 1: 0x%x.", eip05.value.ul2); TRANSLATE("Parameter 2: 0x%x.", eip05.add_data[0]); TRANSLATE("Parameter 3: 0x%x.", eip05.add_data[1]); ENDTRANSLATIONBLOCK EC BLOCK: 09de5205 SCID_SCMI_LDISK_CONDITION_CHANGE_INVALIDATED TRANSLATIONBLOCK TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle); TRANSLATE( "State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]", eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0b000010 SCID_SYS_RESYNCH TRANSLATIONBLOCK TRANSLATE("Controller: %[wwn]", eip10.node_name); TRANSLATE("Program Counter: 0x%08x", eip10.information.pc); TRANSLATE( "Code: %d., 0x%08x (%[rcse])", eip10.information.code, eip10.information.code, eip10.information.code ); TRANSLATE("Flags: 0x%08x", eip10.information.flags); TRANSLATE("Flag meanings:"); TRANSLATE( "0x00000001 = Do not turn off host port LASERs" ); TRANSLATE( "0x00000002 = Do not wait RA_TOV if source ids were not changed" ); TRANSLATE( "0x00000004 = Bypass all diagnostics" ); TRANSLATE( "0x00000008 = Bypass diagnostics and configuration" ); TRANSLATE( "0x00000010 = Do not prompt for GO" ); TRANSLATE( "0x00000020 = Bypass card boot and diagnostics" ); TRANSLATE( "0x00000040 = Use image in memory" ); TRANSLATE( "0x00000080 = Bypass device discovery" ); TRANSLATE( "0x00000100 = Realize from memory map" ); TRANSLATE( "0x00000200 = Preserve HELP cache" ); TRANSLATE( "0x00000400 = Emergency drive firmware upgrade" ); TRANSLATE( "0x00001000 = Preserve host port 0 at 2 gigabyte" ); TRANSLATE( "0x00002000 = Preserve host port 1 at 2 gigabyte" ); TRANSLATE( "0x02000000 = Use bypass to send resynchronization MFC" ); TRANSLATE( "0x04000000 = Storage System scrub by this controller" ); TRANSLATE( "0x08000000 = Storage System scrub by other controller" ); TRANSLATE( "0x10000000 = Log event after reboot" ); TRANSLATE( "0x20000000 = Storage System resynchronization" ); TRANSLATE( "0x40000000 = Fault Manager termination bypassed" ); TRANSLATE( "0x80000000 = Power on reboot occurred" ); ENDTRANSLATIONBLOCK EC BLOCK: 0b01b515 SCID_SYS_MIGRATE_DFW_STALLED TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Volume identity unavailable"), TRANSLATE("Volume: %[tag]", eip15.tag1) ); TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE("State: Migrating") ); CONDITIONAL(eip15.status == 1, TRANSLATE("Status: Awaiting additional storage") ); ENDTRANSLATIONBLOCK EC BLOCK: 0b020004 SCID_SYS_DCL_BEGIN TRANSLATIONBLOCK TRANSLATE("Model: %s",eip04.pid); TRANSLATE("Target revision: %s",eip04.rev); ENDTRANSLATIONBLOCK EC BLOCK: 0b040004 SCID_SYS_CODELOAD_DRIVE TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("Port ID: %s", eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE("Rack, enclosure, and bay not known") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE("Last known bay: %d.", eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE("Bay: %d.", eip04.bay) ); TRANSLATE("AL_PA: 0x%04x", eip04.al_pa); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Target firmware revision: %s", eip04.new_rev); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0b050004 SCID_SYS_DRIVE_LOADED TRANSLATIONBLOCK TRANSLATE("Physical disk drive: %[tag]", eip04.device); TRANSLATE("SCSI Product ID: %s", eip04.pid); TRANSLATE("Current firmware revision: %s", eip04.rev); TRANSLATE("Target firmware revision: %s", eip04.new_rev); TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0b06001a SCID_SYS_CODELOAD TRANSLATIONBLOCK TRANSLATE("State: %s", eip1A.state); TRANSLATE("AddState/Version: %s %s", eip1A.hardware, eip1A.versions); ENDTRANSLATIONBLOCK EC BLOCK: 0b070b1a SCID_SYS_GLUE_POWERDOWN_NEEDED TRANSLATIONBLOCK TRANSLATE("State: %s", eip1A.state); TRANSLATE("AddState/Version: %s %s", eip1A.hardware, eip1A.versions); ENDTRANSLATIONBLOCK EC BLOCK: 0b09001e SCID_SYS_PROCESS_WITH_WORK TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE("Process: %s %02d", eip1E.info, eip1E.data[0]) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE("Process: %s", eip1E.info) ); CONDITIONAL(eip1E.data[1] != 0, TRANSLATE("Stack[0]: %08x (%s)", eip1E.data[1], XLATE_PC_CURRENT(eip1E.data[1])) ); CONDITIONAL(eip1E.data[2] != 0, TRANSLATE("Stack[1]: %08x (%s)", eip1E.data[2], XLATE_PC_CURRENT(eip1E.data[2])) ); CONDITIONAL(eip1E.data[3] != 0, TRANSLATE("Stack[2]: %08x (%s)", eip1E.data[3], XLATE_PC_CURRENT(eip1E.data[3])) ); CONDITIONAL(eip1E.data[4] != 0, TRANSLATE("Stack[3]: %08x (%s)", eip1E.data[4], XLATE_PC_CURRENT(eip1E.data[4])) ); CONDITIONAL(eip1E.data[5] != 0, TRANSLATE("Stack[4]: %08x (%s)", eip1E.data[5], XLATE_PC_CURRENT(eip1E.data[5])) ); CONDITIONAL(eip1E.data[6] != 0, TRANSLATE("Stack[5]: %08x (%s)", eip1E.data[6], XLATE_PC_CURRENT(eip1E.data[6])) ); CONDITIONAL(eip1E.data[7] != 0, TRANSLATE("Stack[6]: %08x (%s)", eip1E.data[7], XLATE_PC_CURRENT(eip1E.data[7])) ); CONDITIONAL(eip1E.data[8] != 0, TRANSLATE("Stack[7]: %08x (%s)", eip1E.data[8], XLATE_PC_CURRENT(eip1E.data[8])) ); CONDITIONAL(eip1E.data[9] != 0, TRANSLATE("Stack[8]: %08x (%s)", eip1E.data[9], XLATE_PC_CURRENT(eip1E.data[9])) ); CONDITIONAL(eip1E.data[10] != 0, TRANSLATE("Stack[9]: %08x (%s)", eip1E.data[10], XLATE_PC_CURRENT(eip1E.data[10])) ); CONDITIONAL(eip1E.data[11] != 0, TRANSLATE("Stack[10]: %08x (%s)", eip1E.data[11], XLATE_PC_CURRENT(eip1E.data[11])) ); CONDITIONAL(eip1E.data[12] != 0, TRANSLATE("Stack[11]: %08x (%s)", eip1E.data[12], XLATE_PC_CURRENT(eip1E.data[12])) ); CONDITIONAL(eip1E.data[13] != 0, TRANSLATE("Stack[12]: %08x (%s)", eip1E.data[13], XLATE_PC_CURRENT(eip1E.data[13])) ); CONDITIONAL(eip1E.data[14] != 0, TRANSLATE("Stack[13]: %08x (%s)", eip1E.data[14], XLATE_PC_CURRENT(eip1E.data[14])) ); CONDITIONAL(eip1E.data[15] != 0, TRANSLATE("Stack[14]: %08x (%s)", eip1E.data[15], XLATE_PC_CURRENT(eip1E.data[15])) ); CONDITIONAL(eip1E.data[16] != 0, TRANSLATE("Stack[15]: %08x (%s)", eip1E.data[16], XLATE_PC_CURRENT(eip1E.data[16])) ); CONDITIONAL(eip1E.data[17] != 0, TRANSLATE("Stack[16]: %08x (%s)", eip1E.data[17], XLATE_PC_CURRENT(eip1E.data[17])) ); CONDITIONAL(eip1E.data[18] != 0, TRANSLATE("Stack[17]: %08x (%s)", eip1E.data[18], XLATE_PC_CURRENT(eip1E.data[18])) ); CONDITIONAL(eip1E.data[19] != 0, TRANSLATE("Stack[18]: %08x (%s)", eip1E.data[19], XLATE_PC_CURRENT(eip1E.data[19])) ); CONDITIONAL(eip1E.data[20] != 0, TRANSLATE("Stack[19]: %08x (%s)", eip1E.data[20], XLATE_PC_CURRENT(eip1E.data[20])) ); CONDITIONAL(eip1E.data[21] != 0, TRANSLATE("Stack[20]: %08x (%s)", eip1E.data[21], XLATE_PC_CURRENT(eip1E.data[21])) ); CONDITIONAL(eip1E.data[22] != 0, TRANSLATE("Stack[21]: %08x (%s)", eip1E.data[22], XLATE_PC_CURRENT(eip1E.data[22])) ); CONDITIONAL(eip1E.data[23] != 0, TRANSLATE("Stack[22]: %08x (%s)", eip1E.data[23], XLATE_PC_CURRENT(eip1E.data[23])) ); ENDTRANSLATIONBLOCK EC BLOCK: 0c03000c SCID_DRM_MERGING TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c045f0c SCID_DRM_FAILSAFE_LOCKED_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c05610c SCID_DRM_FAILSAFE_LOCKED_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c06600c SCID_DRM_COPY_READ_ERROR TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid); TRANSLATE("First block in error: 0x%08x", eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c075f0c SCID_DRM_COPY_WRITE_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); TRANSLATE("First block in error: 0x%08x", eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c08610c SCID_DRM_COPY_WRITE_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); TRANSLATE("First block in error: 0x%08x", eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c09620c SCID_DRM_LOG_FULL TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0a000c SCID_DRM_LOG_RESET TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0c000c SCID_DRM_MERGE_DONE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0f000c SCID_DRM_FAILSAFE_CLEARED TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c10000c SCID_DRM_FULL_COPY TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c11000c SCID_DRM_SITE_FAILOVER_DEST_TO_SRC TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Source Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c12000c SCID_DRM_SITE_FAILOVER_SRC_TO_DEST TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c160016 SCID_DRM_TIME_REPORT TRANSLATIONBLOCK TRANSLATE("Message sender: %[uuid]", eip16.sender); TRANSLATE("Message receiver: %[uuid]", eip16.receiver); TRANSLATE("Message receiver's partner: %[uuid]", eip16.receiver_partner); TRANSLATE("Time message sent: %[scmitim]", eip16.sent_time); TRANSLATE("Time message received: %[scmitim]", eip16.received_time); ENDTRANSLATIONBLOCK EC BLOCK: 0c17630c SCID_DRM_COMM_PROTOCOL_MISMATCH TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid ); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c18640c SCID_DRM_SLOW_CROSS_SITE_RESPONSE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c19020c SCID_DRM_WRITE_COLLISION TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); TRANSLATE("First overlapping block in error: 0x%08x", eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c1a000c SCID_DRM_COPY_DONE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1b5f0c SCID_DRM_LOGGING_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1c610c SCID_DRM_LOGGING_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1d000c SCID_DRM_LOG_INCONSISTENT TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1e5f0c SCID_DRM_NOT_PRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1f000c SCID_DRM_REPRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c20650c SCID_DRM_STUCK_CROSS_SITE_RESPONSE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c21660c SCID_DRM_STUCK_LOCAL_GSB_LOCK TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c22000c SCID_DRM_TUNNEL_OPENED TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid ); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c23670c SCID_DRM_SLOW_ISL_RESPONSE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c24000c SCID_DRM_LOGGING_UNIT_STALLED TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c25000c SCID_DRM_COPY_WRITE_UNIT_STALLED TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); TRANSLATE("First block in error: 0x%08x", eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c26000c SCID_DRM_EXISTING_TUNNEL_OPENED TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid ); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c27000c SCID_DRM_TUNNEL_OPENED_BY_PEER TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid ); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c285f0c SCID_DRM_REMOTE_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c29000c SCID_DRM_TUNNEL_CLOSED_PREF_PORT TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid ); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2a000c SCID_DRM_REMOTE_SITE_FOUND TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2b600c SCID_DRM_MERGE_READ_ERROR TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2c660c SCID_DRM_STUCK_DEST_GSB_LOCK TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Source Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2d000c SCID_DRM_DELETE_PORTWWN TRANSLATIONBLOCK TRANSLATE("Client Object: %[tag]", eip0C.group_uuid); TRANSLATE("Host index: 0x%04x", eip0C.blocks); TRANSLATE("Peer node: %[wwn]", eip0C.source_scvd_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2e680c SCID_DRM_TOO_MANY_NODES TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 0c2f000c SCID_DRM_AVAILABLE_NODES TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 0c30000c SCID_DRM_INVALIDATE_LOG TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c31000c SCID_DRM_COPY_RESTART TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c325f0c SCID_DRM_TUNNEL_CL_LNKDWN TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c335f0c SCID_DRM_TUNNEL_CL_STUCKTMO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c345f0c SCID_DRM_TUNNEL_CL_FLTMO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c35070c SCID_DRM_TUNNEL_CL_GSBLCK TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c365f0c SCID_DRM_TUNNEL_CL_THRASH TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c375f0c SCID_DRM_TUNNEL_CL_PNGRTRY TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c38630c SCID_DRM_TUNNEL_CL_UNSUPPROTO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c39000c SCID_DRM_TUNNEL_CL_TEARDOWN TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3a5f0c SCID_DRM_TUNNEL_CL_OPENTMO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3b000c SCID_DRM_TUNNEL_CL_RMTREOPEN TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3c000c SCID_DRM_TUNNEL_CL_RMTOPN_DP TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3d5f0c SCID_DRM_TUNNEL_CL_RSNDTMO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3e000c SCID_DRM_TUNNEL_CL_RMTREQ TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3f000c SCID_DRM_TUNNEL_CL_NEWSID TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c40690c SCID_DRM_TUNNEL_CL_INVALIDSN TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c41000c SCID_DRM_TUNNEL_CL_CHGPROTO TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c42000c SCID_DRM_TUNNEL_CL_PEERDEL TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c43000c SCID_DRM_TUNNEL_CL_MAINT13 TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c49000c SCID_DRM_TUNNEL_CL_CCBDEL TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4a000c SCID_DRM_CONN_RJT_RESYNC TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4b000c SCID_DRM_CONN_RJT_NOSCELL TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4c000c SCID_DRM_CONN_RJT_NOPATH TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4d000c SCID_DRM_CONN_RJT_POLLING TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4e000c SCID_DRM_CONN_RJT_NOTEVA TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4f000c SCID_DRM_CONN_RJT_HOSTWWID TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c50000c SCID_DRM_CONN_RJT_BADUUID TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c51000c SCID_DRM_CONN_RJT_VERSION TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c52000c SCID_DRM_CONN_RJT_PRTDISABLE TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c53000c SCID_DRM_CONN_RJT_NORESRC TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c54000c SCID_DRM_CONN_RJT_NEWVER TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c550016 SCID_DRM_TIME_SENT TRANSLATIONBLOCK TRANSLATE("Message sender: %[uuid]", eip16.sender); TRANSLATE("Message sender's partner: %[uuid]", eip16.receiver_partner); TRANSLATE("Message receiver: %[uuid]", eip16.receiver); TRANSLATE("Time message sent: %[scmitim]", eip16.sent_time); ENDTRANSLATIONBLOCK EC BLOCK: 0c56000c SCID_DRM_FL_TIMEOUT_CHANGE TRANSLATIONBLOCK TRANSLATE("The DRM forced logging timeout value has changed from %d seconds to %d seconds.", eip0C.port, eip0C.side); ENDTRANSLATIONBLOCK EC BLOCK: 0c57000c SCID_DRM_FL_TIMEOUT_RESET TRANSLATIONBLOCK TRANSLATE("The DRM forced logging timeout value has reset to %d seconds.",eip0C.side); ENDTRANSLATIONBLOCK EC BLOCK: 0c58690c SCID_DRM_HIGH_ISL_RETRY_RATE TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c59690c SCID_DRM_HIGH_OUT_OF_ORDER_RATE TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5a670c SCID_DRM_HIGH_ISL_PING_TIME TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5b670c SCID_DRM_MIN_WRITE_RESOURCES TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5c670c SCID_DRM_MIN_COPY_RESOURCES TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5d000c SCID_DRM_ISL_QOS_HAS_IMPROVED TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5e000c SCID_DRM_LOG_SHRINK_IN_PROGRESS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5f000c SCID_DRM_LOG_SHRINK_FINISHED TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid); TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid); TRANSLATE("Data Replication Destination Storage System: %[tag]", eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c60000c SCID_DRM_HIGH_VDISK_RESPONSE TRANSLATIONBLOCK TRANSLATE("Port: %s", eip0C.cerp_id); TRANSLATE("Controller: %d", eip0C.side); TRANSLATE("Peer Storage System: %[tag]", eip0C.peer_scell_uuid); TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0d000111 SCID_DEEMU_UNRECOGNIZED_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("alarm_error_code.field.reserved: 0x%02x", eip11.alarm_error_code.field.reserved ); TRANSLATE("alarm_error_code.field.ec: 0x%02x", eip11.alarm_error_code.field.ec ); TRANSLATE("alarm_error_code.field.en: 0x%02x", eip11.alarm_error_code.field.en ); TRANSLATE("alarm_error_code.field.et: 0x%02x", eip11.alarm_error_code.field.et ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d014011 SCID_DEEMU_DRIVE_CFG_LINK_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Bay which detected problem: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d024111 SCID_DEEMU_DRIVE_MISSING TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected bay: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d034111 SCID_DEEMU_DRIVE_SLACTIVE_REMOVED TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected bay: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d044211 SCID_DEEMU_DRIVE_LINK_RATE_BAD TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected bay: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.alarm_error_code.field.ec == 4, TRANSLATE("Problem detected on loop A") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 5, TRANSLATE("Problem detected on loop B") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d330911 SCID_DEEMU_DEPSACI_LOST TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected power supply: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d348011 SCID_DEEMU_DEPS_MISSING TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected power supply: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d359a11 SCID_DEEMU_LOAD_BALANCE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected power supply: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d478311 SCID_DEEMU_DEBLWR_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected blower: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Blower speed is out of range") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 2, TRANSLATE("Blower speed is vastly out of range") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 3, TRANSLATE("Blower has stopped") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 4, TRANSLATE("Blower reported internal error") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d4b8211 SCID_DEEMU_DEBLWR_MISSING TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Affected blower: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d4c8411 SCID_DEEMU_DEBLWR_BOTH_MISSING TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Second missing blower: %d.", eip11.alarm_error_code.field.en ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d5b8611 SCID_DEEMU_DETS_OOR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.en == 1, TRANSLATE("Temperature sensor tripped by power supply 1 exhaust") ); CONDITIONAL(eip11.alarm_error_code.field.en == 2, TRANSLATE("Temperature sensor tripped by power supply 2 exhaust") ); CONDITIONAL(eip11.alarm_error_code.field.en == 3, TRANSLATE("Temperature sensor tripped by Drive Enclosure Environmental Monitoring Unit") ); CONDITIONAL(eip11.alarm_error_code.field.en >= 4, TRANSLATE("Temperature sensor tripped by drive bay %d.", eip11.alarm_error_code.field.en - 3 ) ); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Temperature range is near high critical") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 2, TRANSLATE("Temperature range is above high critical") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 3, TRANSLATE("Temperature range is near low critical") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 4, TRANSLATE("Temperature range is reached low critical") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d5f8711 SCID_DEEMU_DETS_ATCRITICAL TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d6f8811 SCID_DEEMU_INTERNAL_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("An internal Drive Enclosure Environmental Monitoring Unit clock error has occurred") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 2, TRANSLATE("The I2C bus not processing data and is unable to report status") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 5, TRANSLATE("A backplane NVRAM error has occurred.") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d710011 SCID_DEEMU_INTERNAL_ERROR1 TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.ec == 3, TRANSLATE("Error is due to an enclosure power supply shutdown") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 16, TRANSLATE("Error is due to corrupt Drive Enclosure Environmental Monitoring Unit ESI data") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d728a11 SCID_DEEMU_NOSES TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d7e8c11 SCID_DEEMU_INVNVRAM TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d7f8b11 SCID_DEEMU_INTERNAL_ERROR2 TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.ec == 11, TRANSLATE("Error cause: Drive Enclosure Environmental Monitoring Unit cannot write to NVRAM)") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 12, TRANSLATE("Error cause: Drive Enclosure Environmental Monitoring Unit cannot read from NVRAM)") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 13, TRANSLATE("Error cause: the Field Programmable Gate Array failed to load required information") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d828e11 SCID_DEEMU_ENCADDRBAD TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d838911 SCID_DEEMU_HARDBAD TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL( eip11.alarm_error_code.field.ec == 15, TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure DP") ); CONDITIONAL( eip11.alarm_error_code.field.ec == 18, TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure BT") ); CONDITIONAL( eip11.alarm_error_code.field.ec == 19, TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure ESI") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d858f11 SCID_DEEMU_PSSHTDNFAILED TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0d8d9011 SCID_DEEMU_DEXCVR_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("Transceiver: %d.", eip11.alarm_error_code.field.en); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Error cause: transceivers have invalid or incompatible type") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 2, TRANSLATE("Error cause: transceiver cannot detect data signal") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 3, TRANSLATE("Error cause: FC-AL bus fault involving transceiver") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 4, TRANSLATE("Error cause: transceiver removed") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 5, TRANSLATE("Error cause: transceiver detected invalid characters") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0da18111 SCID_DEEMU_DEVS_OOR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.en == 1, TRANSLATE("Voltage sensor tripped by power supply 1: +5 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 2, TRANSLATE("Voltage sensor tripped by power supply 1: +12 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 3, TRANSLATE("Voltage sensor tripped by power supply 2: +5 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 4, TRANSLATE("Voltage sensor tripped by power supply 2: +12 VDC") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0db58111 SCID_DEEMU_DECS_OOR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.en == 1, TRANSLATE("Current sensor tripped by power supply 1: +5 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 2, TRANSLATE("Current sensor tripped by power supply 1: +12 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 3, TRANSLATE("Current sensor tripped by power supply 2: +5 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.en == 4, TRANSLATE("Current sensor tripped by power supply 2: +12 VDC") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("The element current is appoaching the high current critical threshold") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 2, TRANSLATE("The element current is above the high current critical threshold") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0dd89211 SCID_DEEMU_BACKPLANE_ERROR_AUTOREC TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0dd99111 SCID_DEEMU_BACKPLANE_ERROR_UNREC TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.alarm_error_code.field.ec == 11, TRANSLATE("Error cause: cannot write to NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 12, TRANSLATE("Error cause: cannot read from NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 13, TRANSLATE("Error cause: NVRAM not properly initialized") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0ddd9311 SCID_DEEMU_DEIOM_ERROR_UNREC TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Error cause: I/O module link speed unsupported") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 11, TRANSLATE("Error cause: cannot write to I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 12, TRANSLATE("Error cause: cannot read from I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 13, TRANSLATE("Error cause: I/O module was removed") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0dde9511 SCID_DEEMU_DEIOM_NOCOMM_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Error cause: I/O module link speed unsupported") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 11, TRANSLATE("Error cause: cannot write to I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 12, TRANSLATE("Error cause: cannot read from I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 13, TRANSLATE("Error cause: I/O module was removed") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0dec9411 SCID_DEEMU_DEIOM_ERROR_AUTOREC TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en); CONDITIONAL(eip11.alarm_error_code.field.ec == 1, TRANSLATE("Error cause: I/O module link speed unsupported") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 11, TRANSLATE("Error cause: cannot write to I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 12, TRANSLATE("Error cause: cannot read from I/O module NVRAM") ); CONDITIONAL(eip11.alarm_error_code.field.ec == 13, TRANSLATE("Error cause: I/O module was removed") ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0df00011 SCID_DEEMU_STATUS_CHANGE TRANSLATIONBLOCK CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0df68811 SCID_DEEMU_COMM_ERROR TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("alarm_error_code.field.ec: 0x%02x", eip11.alarm_error_code.field.ec ); TRANSLATE("alarm_error_code.field.en: 0x%02x", eip11.alarm_error_code.field.en ); TRANSLATE("alarm_error_code.field.et: 0x%02x", eip11.alarm_error_code.field.et ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0df70011 SCID_DEEMU_COMM_RECOVERY_COMPLETE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("alarm_error_code.field.ec: 0x%02x", eip11.alarm_error_code.field.ec ); TRANSLATE("alarm_error_code.field.en: 0x%02x", eip11.alarm_error_code.field.en ); TRANSLATE("alarm_error_code.field.et: 0x%02x", eip11.alarm_error_code.field.et ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0df80011 SCID_DEEMU_COMM_INIT_COMPLETE TRANSLATIONBLOCK TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle); CONDITIONAL(eip11.dencl_num == 99, TRANSLATE("Location unknown") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num < 99, TRANSLATE("Enclosure: %d.", eip11.dencl_num) ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Rack number not valid in this release") ); CONDITIONAL(eip11.dencl_num > 99, TRANSLATE("Last known enclosure: %d.", eip11.dencl_num - 100 ) ); TRANSLATE("alarm_error_code.field.ec: 0x%02x", eip11.alarm_error_code.field.ec ); TRANSLATE("alarm_error_code.field.en: 0x%02x", eip11.alarm_error_code.field.en ); TRANSLATE("alarm_error_code.field.et: 0x%02x", eip11.alarm_error_code.field.et ); CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information")); ENDTRANSLATIONBLOCK EC BLOCK: 0e000019 SCID_SDC_BATT_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("Battery System State : %[scmi_nsc_battery_system_condition]", eip19.state.cur); TRANSLATE("Battery System HUT : %d",eip19.status_data.cur); TRANSLATE("Brick 0 State : %[scmi_battery_brick_state]", eip19.comp_states[0]); TRANSLATE("Brick 0 Overall Status : %[scmi_battery_brick_status_code]", eip19.comp_status_codes[0]); TRANSLATE("Brick 0 Combined Status : 0x%08X",eip19.comp_status_data[0]); TRANSLATE("Brick 1 State : %[scmi_battery_brick_state]", eip19.comp_states[1]); TRANSLATE("Brick 1 Overall Status : %[scmi_battery_brick_status_code]", eip19.comp_status_codes[1]); TRANSLATE("Brick 1 Combined Status : 0x%08X",eip19.comp_status_data[1]); TRANSLATE("Brick 2 State : %[scmi_battery_brick_state]", eip19.comp_states[2]); TRANSLATE("Brick 2 Overall Status : %[scmi_battery_brick_status_code]", eip19.comp_status_codes[2]); TRANSLATE("Brick 2 Combined Status : 0x%08X",eip19.comp_status_data[2]); TRANSLATE("Brick 3 State : %[scmi_battery_brick_state]", eip19.comp_states[3]); TRANSLATE("Brick 3 Overall Status : %[scmi_battery_brick_status_code]", eip19.comp_status_codes[3]); TRANSLATE("Brick 3 Combined Status : 0x%08X",eip19.comp_status_data[3]); ENDTRANSLATIONBLOCK EC BLOCK: 0e010019 SCID_SDC_BATT_BRICK_0_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur); TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e02cc19 SCID_SDC_BATT_BRICK_0_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e030019 SCID_SDC_BATT_BRICK_0_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e04c819 SCID_SDC_BATT_BRICK_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e050019 SCID_SDC_BATT_BRICK_1_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur); TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e06cd19 SCID_SDC_BATT_BRICK_1_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e070019 SCID_SDC_BATT_BRICK_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e08c919 SCID_SDC_BATT_BRICK_1_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e090019 SCID_SDC_BATT_BRICK_2_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur); TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0ace19 SCID_SDC_BATT_BRICK_2_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0b0019 SCID_SDC_BATT_BRICK_2_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0cca19 SCID_SDC_BATT_BRICK_2_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0d0019 SCID_SDC_BATT_BRICK_3_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur); TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0ecf19 SCID_SDC_BATT_BRICK_3_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e0f0019 SCID_SDC_BATT_BRICK_3_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e10cb19 SCID_SDC_BATT_BRICK_3_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE("State : %[scmi_battery_brick_state]", eip19.state.cur), TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]", eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]", eip19.status_code.cur), TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]", eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e110019 SCID_SDC_BATT_SYS_COND_GOOD TRANSLATIONBLOCK TRANSLATE("Battery System Hold-up Time is greater than %d hours", eip19.status_code.cur); TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]", eip19.state.old, eip19.state.cur); TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old, eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e120019 SCID_SDC_BATT_SYS_COND_LOW TRANSLATIONBLOCK TRANSLATE("Battery System Hold-up Time is greater than %d and less than %d hours", eip19.status_code.old, eip19.status_code.cur); TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]", eip19.state.old, eip19.state.cur); TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old, eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e13d019 SCID_SDC_BATT_SYS_COND_BAD TRANSLATIONBLOCK TRANSLATE("Battery System Hold-up Time is zero hours"); TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]", eip19.state.old, eip19.state.cur); TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old, eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e140019 SCID_SDC_BLOW_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("Blower 0 State : %[scmi_fan_status]", eip19.comp_states[0]); TRANSLATE("Blower 0 Initial Status : 0x%X",eip19.comp_status_codes[0]); TRANSLATE("Blower 0 RPM : %d",eip19.comp_status_data[0]); TRANSLATE("Blower 1 State : %[scmi_fan_status]", eip19.comp_states[1]); TRANSLATE("Blower 1 Initial Status : 0x%X",eip19.comp_status_codes[1]); TRANSLATE("Blower 1 RPM : %d",eip19.comp_status_data[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0e150019 SCID_SDC_BLOWER_0_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status]",eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e16d419 SCID_SDC_BLOWER_0_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e170019 SCID_SDC_BLOWER_0_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e18d219 SCID_SDC_BLOWER_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e190019 SCID_SDC_BLOWER_1_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status]",eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1ad519 SCID_SDC_BLOWER_1_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1b0019 SCID_SDC_BLOWER_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1cd319 SCID_SDC_BLOWER_1_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]", eip19.state.old, eip19.state.cur); TRANSLATE("Status Code : 0x%X",eip19.status_code.cur); TRANSLATE("RPM : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1dda19 SCID_SDC_BATT_MEMORY_READ_FAILURE TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("Battery Brick Number : %d",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1e0019 SCID_SDC_TEMP_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_temp_system_state]",eip19.state.cur); TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]); TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]); TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]); TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]); TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e1f0019 SCID_SDC_TEMP_NORMAL TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]", eip19.state.old, eip19.state.cur); TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]); TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]); TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]); TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]); TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e202e19 SCID_SDC_TEMP_CLOSE_TO_TEMP_TRIP TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]", eip19.state.old, eip19.state.cur); TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]); TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]); TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]); TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]); TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e213619 SCID_SDC_TEMP_OVER_TEMP TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]", eip19.state.old, eip19.state.cur); TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]); TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]); TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]); TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]); TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e220019 SCID_SDC_PWR_SUPPLY_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("Power Supply 0 State : %[scmi_power_supply_state]", eip19.comp_states[0]); TRANSLATE("Power Supply 1 State : %[scmi_power_supply_state]", eip19.comp_states[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0e230019 SCID_SDC_PWR_SUPPLY_0_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state]",eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e24d819 SCID_SDC_PWR_SUPPLY_0_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e250019 SCID_SDC_PWR_SUPPLY_0_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e26d619 SCID_SDC_PWR_SUPPLY_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e270019 SCID_SDC_PWR_SUPPLY_1_INSERTED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state]",eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e28d919 SCID_SDC_PWR_SUPPLY_1_REMOVED TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e290019 SCID_SDC_PWR_SUPPLY_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e2ad719 SCID_SDC_PWR_SUPPLY_1_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle); TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]", eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 42000008 SCID_HP_FC_LINK_DOWN TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42010008 SCID_HP_FC_LINK_FAILED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42030007 SCID_HP_LINK_ERRORS TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip07.cerp_id); CONDITIONAL( eip07.loss_of_signal != 0, TRANSLATE("Loss of signal: %d.", eip07.loss_of_signal) ); CONDITIONAL( eip07.bad_rx_char != 0, TRANSLATE("Bad RX characters: %d.", eip07.bad_rx_char) ); CONDITIONAL( eip07.loss_of_sync != 0, TRANSLATE("Loss of synchs: %d.", eip07.loss_of_sync) ); CONDITIONAL( eip07.link_fail != 0, TRANSLATE("Link failures: %d.", eip07.link_fail) ); CONDITIONAL( eip07.rx_eofa != 0, TRANSLATE("RX EOFa delimiters: %d.", eip07.rx_eofa) ); CONDITIONAL( eip07.dis_frm != 0, TRANSLATE("Discarded frames: %d.", eip07.dis_frm) ); CONDITIONAL( eip07.bad_crc != 0, TRANSLATE("Frames with bad CRC and valid EOF: %d.", eip07.bad_crc) ); CONDITIONAL( eip07.proto_err != 0, TRANSLATE("N_Port protocol errors: %d.", eip07.proto_err) ); CONDITIONAL( eip07.exp_frm != 0, TRANSLATE("Expired outbound frames: %d.", eip07.exp_frm) ); ENDTRANSLATIONBLOCK EC BLOCK: 42044a08 SCID_HP_LINK_FAILURE TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); TRANSLATE("Producer index: %04X", eip08.peq_prod_index); TRANSLATE("Consumer index: %04X", eip08.peq_cons_index); TRANSLATE("Frozen index: %04X", eip08.peq_frz_prod_index); TRANSLATE("Port event block(s):"); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( " [0] Type: %08X Context: %08X", eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( " [1] Type: %08X Context: %08X", eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( " [2] Type: %08X Context: %08X", eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( " [3] Type: %08X Context: %08X", eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( " [4] Type: %08X Context: %08X", eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( " [5] Type: %08X Context: %08X", eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE( " [6] Type: %08X Context: %08X", eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( " [7] Type: %08X Context: %08X", eip08.peb[7].type, eip08.peb[7].context ) ); ENDTRANSLATIONBLOCK EC BLOCK: 42050008 SCID_HP_FC_LINK_WEDGED TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 4206001b SCID_HP_UNIT_STALLED_TOO_LONG TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag); CONDITIONAL( eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Associated Storage System Virtual Disk: %[tag]", eip1B.scvd_tag) ); ENDTRANSLATIONBLOCK EC BLOCK: 4207001b SCID_HP_LUN_TRANSITION TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag); CONDITIONAL( eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Associated Storage System Virtual Disk: %[tag]", eip1B.scvd_tag) ); ENDTRANSLATIONBLOCK EC BLOCK: 42080008 SCID_HP_FREEZE_TACH TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42090008 SCID_HP_SOFT_RESET_TACH TRANSLATIONBLOCK TRANSLATE("Port ID: %s", eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 420a001b SCID_HP_UNIT_STALLED_TOO_LONG_EXIT TRANSLATIONBLOCK TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag); CONDITIONAL( eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE("Associated Storage System Virtual Disk: %[tag]", eip1B.scvd_tag) ); ENDTRANSLATIONBLOCK EC BLOCK: 83002014 SCID_DOG_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 0, TRANSLATE("(Error reporting for pre-MIST tests)") ); CONDITIONAL(eip14.eep_error.TE_num == 2, TRANSLATE("(HW code check and Operator Control Panel setup)") ); CONDITIONAL(eip14.eep_error.TE_num == 7, TRANSLATE("(Cache Memory test)") ); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE("(Port 0 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE("(Port 1 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE("(Port 2 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE("(Port 3 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 16, TRANSLATE("(Port 4 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE("(Port 5 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE("(Port 6 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE("(Port 7 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE("(Port 8 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE("(Port 9 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 22, TRANSLATE("(All Ports test)") ); CONDITIONAL(eip14.eep_error.TE_num == 23, TRANSLATE("(Port-to-Port test)") ); CONDITIONAL(eip14.eep_error.TE_num == 24, TRANSLATE("(Config and Init Port regs)") ); CONDITIONAL(eip14.eep_error.TE_num == 28, TRANSLATE("(SDC test)") ); CONDITIONAL(eip14.eep_error.TE_num == 31, TRANSLATE("(Hardware Revision test)") ); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83013014 SCID_DOG_FAILURE_GBIC TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE("(Port 0 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE("(Port 1 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE("(Port 2 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE("(Port 3 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 16, TRANSLATE("(Port 4 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE("(Port 5 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE("(Port 6 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE("(Port 7 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE("(Port 8 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE("(Port 9 test)") ); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83073a14 SCID_DOG_FAILURE_GBIC_MISSING TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE("(Port 0 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE("(Port 1 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE("(Port 2 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE("(Port 3 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 16, TRANSLATE("(Port 4 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE("(Port 5 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE("(Port 6 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE("(Port 7 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE("(Port 8 test)") ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE("(Port 9 test)") ); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83083b14 SCID_DOG_SRAM_TEST_ERROR TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83093b14 SCID_DOG_SRAM_PARITY_ERROR TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 830a3b14 SCID_DOG_SRAM_PARITY_GEN_FAIL TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num); TRANSLATE("Test number: %d.", eip14.eep_error.test_num); TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count); TRANSLATE("Error code: %08X", eip14.eep_error.error_code); TRANSLATE("Address of error: %08X", eip14.eep_error.address); TRANSLATE("Expected data: %08X", eip14.eep_error.expected); TRANSLATE("Actual data: %08X", eip14.eep_error.actual); TRANSLATE( "Controller uptime of failure: %y.", eip14.eep_error.uptime ); TRANSLATE("DIMM size: %d MB", eip14.dimm_size ); ENDTRANSLATIONBLOCK TERMINATION CODE TRANSLATION BLOCKS: TC BLOCK: 0101011f SCID_EXEC_FLT_UNKNOWN TRANSLATIONBLOCK TRANSLATE("TC [llistefc]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0102011f SCID_EXEC_FLT_DLQ_ENTRY_CHECK TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0103011f SCID_EXEC_FLT_TIMER_NOT_EXPIRED TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0104011f SCID_EXEC_FLT_NOT_A_TIMER TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0105011f SCID_EXEC_FLT_DLQ_LINKS_NOT_ZERO TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0106011f SCID_EXEC_FLT_DLQ_HEAD_CHECK TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0107011f SCID_EXEC_FLT_SQ_LINK_NOT_ZERO TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0108011f SCID_EXEC_FLT_NOT_A_BQUE TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0109011f SCID_EXEC_FLT_NOT_A_SEM TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010a011f SCID_EXEC_FLT_NYI TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010b011f SCID_EXEC_FLT_NOT_TWI_AS_EXPECTD TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010c011f SCID_EXEC_FLT_TOO_MANY_LOG_CALLS TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010d011f SCID_EXEC_FLT_UNKNOWN_LOG_CALL TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010e011f SCID_EXEC_FLT_NOT_A_AQUE TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010f011f SCID_EXEC_FLT_WAITERS_INVALID TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0110011f SCID_EXEC_FLT_NOT_A_GATE TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0111011f SCID_EXEC_FLT_RECEIVERS_INVALID TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0112011f SCID_EXEC_FLT_BQUE_HAS_ITEMS TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0113011f SCID_EXEC_FLT_NOT_A_ASEM TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0114011f SCID_EXEC_FLT_UNKNOWNSYSTEM_TRAP TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0115011f SCID_EXEC_FLT_ACTIVE_DMA_UNDRFLW TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0116011f SCID_EXEC_FLT_UNEXPECTED_CDB TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0117011f SCID_EXEC_FLT_BUFFER_IN_USE TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0118011f SCID_EXEC_FLT_BUFFER_IS_FREE TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0119011f SCID_EXEC_FLT_INTS_DISABLED TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011a011f SCID_EXEC_FLT_ZERO_PAGE_CORRUPT TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011b011f SCID_EXEC_FLT_DCBZNOTCLALND TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011c0140 SCID_EXEC_FLT_CTRL_K_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 011d01c0 SCID_EXEC_FLT_CTRL_K_CC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 011e0120 SCID_EXEC_FLT_CTRL_R_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 011f01a0 SCID_EXEC_FLT_CTRL_R_CC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 01220105 SCID_EXEC_UNKNOWN_SMI TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("GLUE_SMI_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_SMI_39_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 01400100 SCID_EXEC_TIMER_NOT_BQUE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 015a0100 SCID_EXEC_SHEDULER_SUBP_QUE_EMPTY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02000100 SCID_CA_INSUFF_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02010100 SCID_CA_BAD_GET_DATA TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02020100 SCID_CA_DEFINE_BQ_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02030100 SCID_CA_DUPLICATE_DIRTY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02040100 SCID_CA_BAD_MOP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02050100 SCID_CA_BAD_UNIT_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02070100 SCID_CA_BROKEN_TWICE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02080100 SCID_CA_MIRROR_UUID_CHANGED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02090100 SCID_CA_INVALID_LOCK_META TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020a0100 SCID_CA_INVALID_PARITY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020b0100 SCID_CA_BAD_POP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020c0100 SCID_CA_BAD_GCOP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020d0100 SCID_CA_NCA_CORRUPTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020e0100 SCID_CA_FREE_DIAG_BUF TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020f0100 SCID_CA_IMPROPER_MWB_RECO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02100100 SCID_CA_DIFF_MNODE_MFC_NCAE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02110100 SCID_CA_IMPROPER_MWBF_RECO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02120100 SCID_CA_WRITE_HOLE_COLL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02150100 SCID_CA_CNODE_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02160100 SCID_CA_VBUFF_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02180102 SCID_CA_BAD_PROXY_WRITE_STATE TRANSLATIONBLOCK TRANSLATE("Bad Proxy Write MFC State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("State value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 02190102 SCID_CA_BAD_PROXY_READ_STATE TRANSLATIONBLOCK TRANSLATE("Bad Proxy Read MFC State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("State value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 021a0102 SCID_CA_BAD_PROXY_VERIFY_STATE TRANSLATIONBLOCK TRANSLATE("Bad Proxy Verify MFC State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("State value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 021b0100 SCID_CA_NOT_ENOUGH_XDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 021c0102 SCID_CA_INVALID_FLUSH_NODE TRANSLATIONBLOCK TRANSLATE("Flush Node Ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Block Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03010104 SCID_SCS_INTERNAL_ERROR_SINGLE TRANSLATIONBLOCK TRANSLATE("PC of termination call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("PC-specific parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("PC-specific parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("PC-specific parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 03020184 SCID_SCS_INTERNAL_ERROR_DUAL TRANSLATIONBLOCK TRANSLATE("PC of termination call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("PC-specific parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("PC-specific parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("PC-specific parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 03030102 SCID_SCS_BAD_SWITCH_VALUE TRANSLATIONBLOCK TRANSLATE("PC of termination call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Switch value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03040102 SCID_SCS_QUORUM_ACCESS_FAILURE TRANSLATIONBLOCK TRANSLATE("PC of termination call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("QW block address where access failed: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03060184 SCID_SCS_UNRECOVERABLE_ERROR TRANSLATIONBLOCK TRANSLATE("PC of termination call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("PC-specific parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("PC-specific parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("PC-specific parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 030a0102 SCID_SCS_BAD_SCSDB_INDEX TRANSLATIONBLOCK TRANSLATE("area_offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("ds_index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 030b0101 SCID_SCS_BAD_SCSDB_AREA_OFF TRANSLATIONBLOCK TRANSLATE("area_offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 030c0100 SCID_SCS_SCSDB_CACHE_FULL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 030d0101 SCID_SCS_SCSDB_CACHE_FREE TRANSLATIONBLOCK TRANSLATE("cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 030e0102 SCID_SCS_SCSDB_CACHE_FLUSH TRANSLATIONBLOCK TRANSLATE("cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("page offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 030f0101 SCID_SCS_SCSDB_CACHE_COMMIT TRANSLATIONBLOCK TRANSLATE("cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03100102 SCID_SCS_BAD_CVMDB_INDEX TRANSLATIONBLOCK TRANSLATE("area_offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("ds_index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03110101 SCID_SCS_BAD_CVMDB_AREA_OFF TRANSLATIONBLOCK TRANSLATE("area_offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03120100 SCID_SCS_CVMDB_CACHE_FULL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03130101 SCID_SCS_CVMDB_CACHE_FREE TRANSLATIONBLOCK TRANSLATE("Cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03140102 SCID_SCS_CVMDB_CACHE_FLUSH TRANSLATIONBLOCK TRANSLATE("Cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Page offset: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03150101 SCID_SCS_CVMDB_CACHE_COMMIT TRANSLATIONBLOCK TRANSLATE("Cache page index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03160100 SCID_SCS_PB_BUFFER_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 031f0100 SCID_SCS_FC_OP_DESCS_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 032a0000 SCID_SCS_MASTER_CONFLICT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 033c0106 SCID_SCS_BAD_RP_LOGIN_STATE TRANSLATIONBLOCK TRANSLATE("Invocation instance: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Port login state: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Local port: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Port id value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Port name (low): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Port name (high): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 033d0105 SCID_SCS_BAD_RP_LOGGEDIN_TMR_EXP TRANSLATIONBLOCK TRANSLATE("Port login state: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Local port: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Port id value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Port name (low): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Port name (high): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 03500020 SCID_SCS_DEBUG_CRASH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03510141 SCID_SCS_KILLED_BY_OTHER TRANSLATIONBLOCK TRANSLATE("Reason code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03520140 SCID_SCS_KILL_OTHER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03640020 SCID_SCS_SHUTDOWN_RESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03650060 SCID_SCS_SHUTDOWN_NORESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03660060 SCID_SCS_SHUTDOWN_POWEROFF TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03670000 SCID_SCS_CRASH_RESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03680040 SCID_SCS_CRASH_NORESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03690080 SCID_SCS_CRASH_RESTART_COUPLED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 036a00c0 SCID_SCS_CRASH_NORESTART_COUPLED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 036b0001 SCID_SCS_CANT_FAILOVER_FREEZING_UNIT TRANSLATIONBLOCK TRANSLATE("Unit noid: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 036c01c8 SCID_SCS_NOTIFY_DEV TRANSLATIONBLOCK TRANSLATE("Generic parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Generic parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Generic parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Generic parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Generic parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Generic parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Generic parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("Generic parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); ENDTRANSLATIONBLOCK TC BLOCK: 03780101 SCID_SCS_CANT_REALIZE_XXXDB TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03790020 SCID_SCS_CODE_LOAD_RESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0400011f SCID_FM_DEF_EXCEPTION TRANSLATIONBLOCK TRANSLATE("Ecde [llistppcec]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0401011f SCID_FM_MACHINE_CHECK TRANSLATIONBLOCK TRANSLATE("Glue chip interrupt bits [31:0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Glue chip interrupt bits [63:32]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0402011f SCID_FM_DEBUG TRANSLATIONBLOCK TRANSLATE("Pointer to DEBUG purpose string: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0403047f SCID_FM_RECURSIVE_TE TRANSLATIONBLOCK TRANSLATE("Recursive event termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Recursive event termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Recursive event termination parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Recursive event termination parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Recursive event termination parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Recursive event termination parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("Recursive event termination parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("Recursive event termination parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("Recursive event termination parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("Recursive event termination parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("Recursive event termination parameter 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("Recursive event termination parameter 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("Recursive event termination parameter 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("Recursive event termination parameter 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("Recursive event termination parameter 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("Recursive event termination parameter 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("Recursive event termination parameter 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("Recursive event termination parameter 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("Recursive event termination parameter 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("Recursive event termination parameter 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("Recursive event termination parameter 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("Recursive event termination parameter 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("Recursive event termination parameter 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("Recursive event termination parameter 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("Recursive event termination parameter 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("Recursive event termination parameter 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("Recursive event termination parameter 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("Recursive event termination parameter 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("Recursive event termination parameter 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("Recursive event termination parameter 27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("Recursive event termination parameter 28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04050101 SCID_FM_UPDSCELABAE_EDBN_BAD TRANSLATIONBLOCK TRANSLATE("Event data block index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 0406017f SCID_FM_LTE_RESET TRANSLATIONBLOCK TRANSLATE("In progress event termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("In progress event termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("In progress event termination parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("In progress event termination parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("In progress event termination parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("In progress event termination parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("In progress event termination parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("In progress event termination parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("In progress event termination parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("In progress event termination parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("In progress event termination parameter 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("In progress event termination parameter 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("In progress event termination parameter 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("In progress event termination parameter 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("In progress event termination parameter 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("In progress event termination parameter 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("In progress event termination parameter 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("In progress event termination parameter 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("In progress event termination parameter 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("In progress event termination parameter 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("In progress event termination parameter 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("In progress event termination parameter 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("In progress event termination parameter 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("In progress event termination parameter 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("In progress event termination parameter 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("In progress event termination parameter 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("In progress event termination parameter 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("In progress event termination parameter 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("In progress event termination parameter 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("In progress event termination parameter 27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("In progress event termination parameter 28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0407016a SCID_FM_PREMATURE_TERM TRANSLATIONBLOCK TRANSLATE("Trap type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("TC [llisttcc]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("CR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("XER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("CTR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("Exception code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("Exception count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); ENDTRANSLATIONBLOCK TC BLOCK: 04080582 SCID_FM_COUPLED_CRASH_DR TRANSLATIONBLOCK TRANSLATE("Other controller termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Other controller termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040905a2 SCID_FM_COUPLED_CRASH_NDR TRANSLATIONBLOCK TRANSLATE("Other controller termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Other controller termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040a05c2 SCID_FM_COUPLED_CRASH_DNR TRANSLATIONBLOCK TRANSLATE("Other controller termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Other controller termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040b05e2 SCID_FM_COUPLED_CRASH_NDNR TRANSLATIONBLOCK TRANSLATE("Other controller termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Other controller termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040c0582 SCID_FM_COUPLED_CRASH_BADDRCC TRANSLATIONBLOCK TRANSLATE("Other controller termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Other controller termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040d0101 SCID_FM_UNRECOG_UPDSCELABAE_OP TRANSLATIONBLOCK TRANSLATE("Unrecognized value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 040e0100 SCID_FM_NOT_MASTER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 040f0100 SCID_FM_IS_MASTER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04100182 SCID_FM_SCEL_NOT_ACTIVE TRANSLATIONBLOCK TRANSLATE("Local control flags: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Master control flags: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 04110181 SCID_FM_CSLD_SCXEL_INACC TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 04120123 SCID_FM_ALL_LTE_RESET TRANSLATIONBLOCK TRANSLATE("Unexpected event type: %d. (%[fm_ue])", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Index: %d.", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Good entries: %d.", teb.u.data.ltei.lter.termination_event.params.param[2]); ENDTRANSLATIONBLOCK TC BLOCK: 04130107 SCID_FM_INVALID_STRUCT_TYPE TRANSLATIONBLOCK TRANSLATE("Unexpected value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Allowed value 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Allowed value 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Allowed value 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Allowed value 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Allowed value 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("Allowed value 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04140104 SCID_FM_EIP_OUT_OF_RANGE TRANSLATIONBLOCK TRANSLATE("Event code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Out-of-range EIP type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Minimum allowed EIP type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Maximum allowed EIP type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 04150104 SCID_FM_EIP_TOO_BIG TRANSLATIONBLOCK TRANSLATE("Event code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("EIP type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("EIP size: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Maximum allowed EIP size: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 04160103 SCID_FM_EIP_NOT_MULTLW TRANSLATIONBLOCK TRANSLATE("Event code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("EIP type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("EIP size: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); ENDTRANSLATIONBLOCK TC BLOCK: 04170107 SCID_FM_CSIO_REQUEST_INVALID TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("I/O operation: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("NOID: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Block address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Number of blocks: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"), TRANSLATE("Buffer address supplied to CS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE("PC of call to Container Services: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04180107 SCID_FM_CSIO_UNRECOG_STATUS TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("I/O operation: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("NOID: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Block address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Number of blocks: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"), TRANSLATE("Buffer address supplied to CS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE("PC of call to Container Services: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04190100 SCID_FM_RESTARTDEBUG TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041a0100 SCID_FM_UNEXP_ACTIVEQ_EMPTY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041b0105 SCID_FM_CORRECT_EDBN_NOT_CACHED TRANSLATIONBLOCK TRANSLATE("Event data block number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Current event pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Event entry check status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Current event sequence number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Expected event sequence number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 041c0100 SCID_FM_NOT_SCMI_ETC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041d0100 SCID_FM_NOT_SCMI TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041e0102 SCID_FM_TEISP_BAD TRANSLATIONBLOCK TRANSLATE("Unexpected value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Expected value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 041f0a1f SCID_FM_LOW_MEM_ACC_V TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0420011f SCID_FM_WATCHDOG_TIMEOUT TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04210107 SCID_FM_CSIO_DRIVE_BROKEN_STATUS TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("I/O operation: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("NOID: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Block address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Number of blocks: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"), TRANSLATE("Buffer address supplied to CS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE("PC of call to Container Services: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04220102 SCID_FM_EC_ILLEGAL_SCID TRANSLATIONBLOCK TRANSLATE("Event code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Illegal software component: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 04240960 SCID_FM_POWER_LOSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 043f011f SCID_FM_PPC_EXCEPTION_0000 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0440011f SCID_FM_PPC_EXCEPTION_0100 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0441011f SCID_FM_PPC_EXCEPTION_0200 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0442011f SCID_FM_PPC_EXCEPTION_0300 TRANSLATIONBLOCK TRANSLATE("DSISR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DAR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("DABR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0443011f SCID_FM_PPC_EXCEPTION_0400 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0444011f SCID_FM_PPC_EXCEPTION_0500 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0445011f SCID_FM_PPC_EXCEPTION_0600 TRANSLATIONBLOCK TRANSLATE("DSISR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DAR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0446011f SCID_FM_PPC_EXCEPTION_0700 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0447011f SCID_FM_PPC_EXCEPTION_0800 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0448011f SCID_FM_PPC_EXCEPTION_0900 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0449011f SCID_FM_PPC_EXCEPTION_0A00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044a011f SCID_FM_PPC_EXCEPTION_0B00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044b011f SCID_FM_PPC_EXCEPTION_0C00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044c011f SCID_FM_PPC_EXCEPTION_0D00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044d011f SCID_FM_PPC_EXCEPTION_0E00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044e011f SCID_FM_PPC_EXCEPTION_0F00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044f011f SCID_FM_PPC_EXCEPTION_1000 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0450011f SCID_FM_PPC_EXCEPTION_1100 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0451011f SCID_FM_PPC_EXCEPTION_1200 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0452011f SCID_FM_PPC_EXCEPTION_1300 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0453011f SCID_FM_PPC_EXCEPTION_1400 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04540101 SCID_FM_BAD_EDBN_COUNT TRANSLATIONBLOCK TRANSLATE("Event data block count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 04550101 SCID_FM_BAD_REI_STATUS TRANSLATIONBLOCK TRANSLATE("Unexpected status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 04560102 SCID_FM_ACTIVEQ_EVENT_NA TRANSLATIONBLOCK TRANSLATE("Sequence number requested: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Number events reported valid for retrieval: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 04570105 SCID_FM_DIRECT_TERM_CALL TRANSLATIONBLOCK TRANSLATE("PC of direct call: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Stack pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Trap type parameter: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("TC parameter: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Save area parameter: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0458011f SCID_FM_PPC_EXCEPTION_1500 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0459011f SCID_FM_PPC_EXCEPTION_1600 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045a011f SCID_FM_PPC_EXCEPTION_1700 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045b011f SCID_FM_PPC_EXCEPTION_1800 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045c011f SCID_FM_PPC_EXCEPTION_1900 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045d011f SCID_FM_PPC_EXCEPTION_1A00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045e011f SCID_FM_PPC_EXCEPTION_1B00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045f011f SCID_FM_PPC_EXCEPTION_1C00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0460011f SCID_FM_PPC_EXCEPTION_1D00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0461011f SCID_FM_PPC_EXCEPTION_1E00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0462011f SCID_FM_PPC_EXCEPTION_1F00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0463011f SCID_FM_PPC_EXCEPTION_2000 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0464011f SCID_FM_PPC_EXCEPTION_2100 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0465011f SCID_FM_PPC_EXCEPTION_2200 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0466011f SCID_FM_PPC_EXCEPTION_2300 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0467011f SCID_FM_PPC_EXCEPTION_2400 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0468011f SCID_FM_PPC_EXCEPTION_2500 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0469011f SCID_FM_PPC_EXCEPTION_2600 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046a011f SCID_FM_PPC_EXCEPTION_2700 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046b011f SCID_FM_PPC_EXCEPTION_2800 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046c011f SCID_FM_PPC_EXCEPTION_2900 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046d011f SCID_FM_PPC_EXCEPTION_2A00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046e011f SCID_FM_PPC_EXCEPTION_2B00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046f011f SCID_FM_PPC_EXCEPTION_2C00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0470011f SCID_FM_PPC_EXCEPTION_2D00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0471011f SCID_FM_PPC_EXCEPTION_2E00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0472011f SCID_FM_PPC_EXCEPTION_2F00 TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04730167 SCID_FM_BUILD_ADDRESS_MAP_ERROR TRANSLATIONBLOCK TRANSLATE("ADDRESS_MAP index: %d.", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter 1: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter 2: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter 3: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[3], teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Parameter 4: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[4], teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Parameter 5: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[5], teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Parameter 6: %d. (0x%08x)", teb.u.data.ltei.lter.termination_event.params.param[6], teb.u.data.ltei.lter.termination_event.params.param[6] ); ENDTRANSLATIONBLOCK TC BLOCK: 04740160 SCID_FM_ELPMA_NOTALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0476013f SCID_FM_LTE_RESET_CMPLT TRANSLATIONBLOCK TRANSLATE("In progress event termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("In progress event termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("In progress event termination parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("In progress event termination parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("In progress event termination parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("In progress event termination parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("In progress event termination parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("In progress event termination parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("In progress event termination parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("In progress event termination parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("In progress event termination parameter 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("In progress event termination parameter 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("In progress event termination parameter 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("In progress event termination parameter 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("In progress event termination parameter 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("In progress event termination parameter 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("In progress event termination parameter 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("In progress event termination parameter 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("In progress event termination parameter 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("In progress event termination parameter 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("In progress event termination parameter 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("In progress event termination parameter 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("In progress event termination parameter 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("In progress event termination parameter 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("In progress event termination parameter 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("In progress event termination parameter 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("In progress event termination parameter 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("In progress event termination parameter 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("In progress event termination parameter 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("In progress event termination parameter 27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("In progress event termination parameter 28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0477013f SCID_FM_LTE_RESET_INTD TRANSLATIONBLOCK TRANSLATE("In progress event termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("In progress event termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("In progress event termination parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("In progress event termination parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("In progress event termination parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("In progress event termination parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("In progress event termination parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("In progress event termination parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("In progress event termination parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("In progress event termination parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("In progress event termination parameter 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("In progress event termination parameter 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("In progress event termination parameter 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("In progress event termination parameter 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("In progress event termination parameter 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("In progress event termination parameter 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("In progress event termination parameter 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("In progress event termination parameter 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("In progress event termination parameter 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("In progress event termination parameter 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("In progress event termination parameter 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("In progress event termination parameter 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("In progress event termination parameter 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("In progress event termination parameter 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("In progress event termination parameter 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("In progress event termination parameter 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("In progress event termination parameter 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("In progress event termination parameter 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("In progress event termination parameter 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("In progress event termination parameter 27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("In progress event termination parameter 28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0478393f SCID_FM_LTE_RESET_SPPC_RESET TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Reserved: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Reserved: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[3] != 0, TRANSLATE( "Previous termination event code[-1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[4] != 0, TRANSLATE( "Previous termination event code[-2]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] != 0, TRANSLATE( "Previous termination event code[-3]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[6] != 0, TRANSLATE( "Previous termination event code[-4]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[7] != 0, TRANSLATE( "Previous termination event code[-5]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[8] != 0, TRANSLATE( "Previous termination event code[-6]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[9] != 0, TRANSLATE( "Previous termination event code[-7]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[10] != 0, TRANSLATE( "Previous termination event code[-9]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[11] != 0, TRANSLATE( "Previous termination event code[-10]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[12] != 0, TRANSLATE( "Previous termination event code[-11]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[13] != 0, TRANSLATE( "Previous termination event code[-12]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[14] != 0, TRANSLATE( "Previous termination event code[-13]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[15] != 0, TRANSLATE( "Previous termination event code[-14]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[16] != 0, TRANSLATE( "Previous termination event code[-15]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[17] != 0, TRANSLATE( "Previous termination event code[-16]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[18] != 0, TRANSLATE( "Previous termination event code[-17]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[19] != 0, TRANSLATE( "Previous termination event code[-18]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[20] != 0, TRANSLATE( "Previous termination event code[-19]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[21] != 0, TRANSLATE( "Previous termination event code[-20]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[22] != 0, TRANSLATE( "Previous termination event code[-21]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[23] != 0, TRANSLATE( "Previous termination event code[-22]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[25] != 0, TRANSLATE( "Previous termination event code[-23]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[26] != 0, TRANSLATE( "Previous termination event code[-24]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[27] != 0, TRANSLATE( "Previous termination event code[-25]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[28] != 0, TRANSLATE( "Previous termination event code[-26]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[29] != 0, TRANSLATE( "Previous termination event code[-27]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[30] != 0, TRANSLATE( "Previous termination event code[-28]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30] ) ); ENDTRANSLATIONBLOCK TC BLOCK: 04790020 SCID_FM_LTE_RESET_MMTSTEXECD TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 047a013f SCID_FM_LTE_RESET_UNEXP TRANSLATIONBLOCK TRANSLATE("Termination processing state value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Reserved: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("In progress event termination location: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("In progress event termination code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("In progress event termination parameter 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("In progress event termination parameter 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("In progress event termination parameter 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("In progress event termination parameter 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("In progress event termination parameter 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("In progress event termination parameter 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("In progress event termination parameter 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("In progress event termination parameter 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("In progress event termination parameter 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("In progress event termination parameter 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("In progress event termination parameter 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("In progress event termination parameter 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("In progress event termination parameter 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("In progress event termination parameter 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("In progress event termination parameter 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("In progress event termination parameter 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("In progress event termination parameter 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("In progress event termination parameter 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("In progress event termination parameter 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("In progress event termination parameter 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("In progress event termination parameter 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("In progress event termination parameter 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("In progress event termination parameter 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("In progress event termination parameter 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("In progress event termination parameter 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("In progress event termination parameter 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("In progress event termination parameter 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 047b0022 SCID_FM_SCRUB_REQUESTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 15, TRANSLATE("SCRUB was requested via OCP") ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 56, TRANSLATE("SCRUB was requested via OCP") ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 99, TRANSLATE("SCRUB was requested via SCMI") ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 100, TRANSLATE("SCRUB was requested via the Console") ); TRANSLATE("Calling PC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 04810130 SCID_FM_XL_WATCHDOG_TIMEOUT TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("GLUE_RESET_DIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE_RESET_IN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE_SELF_RESET: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 0482206f SCID_FM_CACHE_VTT_FAIL TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 0483206f SCID_FM_DIMM_012_DC_NOT_OK TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 0484206f SCID_FM_DIMM_3_DC_NOT_OK TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 0485200f SCID_FM_60X_DPE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 04862010 SCID_FM_60X_APE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 0487390e SCID_FM_PPC_L1_ICACHE_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK TC BLOCK: 0488390e SCID_FM_PPC_L1_DCACHE_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK TC BLOCK: 0489390e SCID_FM_PPC_L2_CACHE_TAG_OR_DPE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK TC BLOCK: 048a2015 SCID_FM_60X_TIMEOUT_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE_TIMER_CTRL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE_PPC_SV (pre-Sprite3 only): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("GLUE_PPC_CT (pre-Sprite3 only): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_PC_REV (Sprite3 only): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_PC_WTT (Sprite3 only): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_PC_TT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 048b0030 SCID_FM_KILLED_BY_OTHER TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("GLUE_RESET_DIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE_RESET_IN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE_SELF_RESET: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 048c0030 SCID_FM_RESET_BY_SELF TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("GLUE_RESET_DIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE_RESET_IN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE_SELF_RESET: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 048d0030 SCID_FM_RESET_BY_BUTTON TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("GLUE_RESET_DIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE_RESET_IN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE_SELF_RESET: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 048e0114 SCID_FM_ATLANTIS_60X_BAD_ADDR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 048f2015 SCID_FM_ATLANTIS_60X_TT_IV_BIRV TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 04900114 SCID_FM_ATLANTIS_PROTECTION_ERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 04913915 SCID_FM_ATLANTIS_ISRAM_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_SRAM_CONFIGURATION: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_SRAM_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_SRAM_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_SRAM_ERROR_ADDRESS_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_SRAM_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_SRAM_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("ATLANTIS_SRAM_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 04922015 SCID_FM_ATLANTIS_PM_ECC_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_SDRAM_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_SDRAM_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_SDRAM_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_SDRAM_RECEIVED_ECC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_SDRAM_CALCULATED_ECC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_SDRAM_ECC_COUNTER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("ATLANTIS_SDRAM_ECC_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 04930112 SCID_FM_ATLANTIS_DEV_BURST_ERROR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04942013 SCID_FM_ATLANTIS_DEV_RDY_TIMEOUT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04952013 SCID_FM_ATLANTIS_DEV_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04960112 SCID_FM_ATLANTIS_DMA_BAD_ADDR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04970112 SCID_FM_ATLANTIS_DMA_ACCESS_PROT TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04980112 SCID_FM_ATLANTIS_DMA_WRT_PRO_ERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04990112 SCID_FM_ATLANTIS_DMA_DSCRPT_ACC TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 049a010f SCID_FM_SPRITE_60X_TIMEOUT_PCIX TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 049b2010 SCID_FM_SPRITE_LAST_ENTRY_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 049c2010 SCID_FM_SPRITE_60X_ALIGNMENT_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 049d3910 SCID_FM_SPRITE_QUEUE_RD_DPE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 049e010f SCID_FM_SPRITE_PCIX_ACCESS_ERROR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 049f2011 SCID_FM_SPRITE_QUEUE_INVAL_DEST TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Q_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04a0011b SCID_FM_SPRITE_XORDMA_TIMEOUT TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04a1011b SCID_FM_SPRITE_XORDMA_SFRAME_ERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04a2011b SCID_FM_SPRITE_XORDMA_EFRAME_ERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04a3391c SCID_FM_SPRITE_XORDMA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04a4011b SCID_FM_SPRITE_XORDMA_INVAL_OP TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04a5011b SCID_FM_SPRITE_XORDMA_CNT_ERROR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_X_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_X_TMO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_X_CB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_X_PI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_X_CI: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_X_CC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_X_USA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_X_SA0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_X_SA1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_X_SA2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_X_SA3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_X_UDA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("SPRITE_X_DA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04a62011 SCID_FM_SPRITE_BAD_WRT_DATA_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_M_ES: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04a73911 SCID_FM_SPRITE_CMD_OR_DATA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_M_ES: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04a82011 SCID_FM_SPRITE_NEW_CMD_BAD_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_M_ES: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04a92016 SCID_FM_SPRITE_CM_ECC_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PC_ERR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_M_ES: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_M_ESE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("SPRITE_M_ESO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("SPRITE_M_EAE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_M_EAO: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_M_ESC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); ENDTRANSLATIONBLOCK TC BLOCK: 04aa2012 SCID_FM_PCIX_NO_BOF_INVAL_DEST TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04ab2012 SCID_FM_PCIX_XACTN_LEN_MISMATCH TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04ac3912 SCID_FM_PCIX_XACTN_ENTRY_RPERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04ad0111 SCID_FM_PCIX_BITE_COUNT_MISMATCH TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04ae0111 SCID_FM_PCIX_TARGT_RCNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04af0111 SCID_FM_PCIX_INITR_RCNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b00111 SCID_FM_PCIX_SC_COUNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b10111 SCID_FM_PCIX_SC_ERR_MSG_RCVD TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b20111 SCID_FM_PCIX_UNEXPECTED_SC TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b30111 SCID_FM_PCIX_SC_INVAL_TERMINATN TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b40111 SCID_FM_PCIX_SC_WO_PREV_SR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04b52012 SCID_FM_PCIX_PERR_ASSERTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b60112 SCID_FM_PCIX_BAD_ADDR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b72012 SCID_FM_PCIX_RCVD_TARG_ABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b82012 SCID_FM_PCIX_SERR_ASSERTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b92012 SCID_FM_PCIX_SERR_DETECTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_Pn_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_Pn_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("SPRITE_Pn_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04ba011b SCID_FM_TACH_UNSUP_BYTE_ENA_ERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_PCI_REG_1FC: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04bb391b SCID_FM_TACH_OUTBOUND_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_TACH_STATUS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04bc391b SCID_FM_TACH_INBOUND_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_TACH_STATUS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04bd201c SCID_FM_TACH_DETECTED_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04be201c SCID_FM_TACH_SIGNALED_SERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04bf011b SCID_FM_TACH_RECEIVED_MABORT TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04c0201c SCID_FM_TACH_RECEIVED_TABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c1201c SCID_FM_TACH_SIGNALED_TABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c2201c SCID_FM_TACH_MASTER_DATA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c3011b SCID_FM_TACH_UNEXP_SC_ERROR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_PCI_X_S: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04c4011b SCID_FM_TACH_SC_DISCARDED_ERROR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_PCI_X_S: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04c5391c SCID_FM_TACH_PERR_ON_SC_XACTION TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c6391c SCID_FM_TACH_PERR_ON_IN_DATA TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c7391c SCID_FM_TACH_PERR_ON_OUT_DATA TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c8201c SCID_FM_TACH_ATTRIBUTE_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c9011b SCID_FM_TACH_SC_BYTE_CNT_EXCESS TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04ca011b SCID_FM_TACH_RD_BYTE_CNT_EXCESS TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04cb011b SCID_FM_TACH_READ_FIFO_PERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04cc011b SCID_FM_TACH_WRITE_FIFO_PERR TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_FSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TACHn_ESCR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04cd011b SCID_FM_TACH_RSVD_REGION_ACCESS TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("REAL_PORT_NUMBER: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TACHn_GSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("SPRITE_PC_ADDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TACHn_TACH_CONTROL: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TACHn_FM_STATUSS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TACHn_FM_CONFIG1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TACHn_FM_CONFIG2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TACHn_FM_CONFIG3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04ce010d SCID_FM_TACH_PERR_ON_SC TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); ENDTRANSLATIONBLOCK TC BLOCK: 04cf011a SCID_FM_XL_UNDECODED_MC TRANSLATIONBLOCK TRANSLATE("SRR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SRR1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("MSSSR0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("GLUE_MCP_31_0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("GLUE_MCP_47_32: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SPRITE_PC_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("TACH01_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("TACH23_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("TACH45_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TACH67_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TACH89_CINTPEND: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("SPRITE_P0_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("SPRITE_P0_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("SPRITE_P0_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("SPRITE_P1_CSR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("SPRITE_P1_CSR2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("SPRITE_P1_EDR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); ENDTRANSLATIONBLOCK TC BLOCK: 04d00180 SCID_FM_MEALCP_INUSE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04f6013f SCID_FM_USERAPNDR_TEST TRANSLATIONBLOCK TRANSLATE("TP[0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("TP[1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("TP[2]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("TP[3]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("TP[4]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("TP[5]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("TP[6]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("TP[7]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("TP[8]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("TP[9]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("TP[10]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TP[11]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TP[12]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TP[13]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TP[14]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TP[15]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TP[16]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TP[17]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TP[18]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TP[19]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TP[20]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TP[21]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TP[22]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TP[23]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TP[24]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TP[25]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TP[26]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TP[27]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("TP[28]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("TP[29]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("TP[30]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04f70000 SCID_FM_CTRL_Z_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04f9017f SCID_FM_POFF_TEST TRANSLATIONBLOCK TRANSLATE("TP[0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("TP[1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("TP[2]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("TP[3]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("TP[4]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("TP[5]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("TP[6]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("TP[7]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("TP[8]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("TP[9]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("TP[10]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TP[11]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TP[12]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TP[13]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TP[14]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TP[15]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TP[16]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TP[17]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TP[18]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TP[19]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TP[20]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TP[21]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TP[22]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TP[23]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TP[24]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TP[25]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TP[26]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TP[27]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("TP[28]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("TP[29]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("TP[30]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fa0100 SCID_FM_USERNP_TEST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04fb011f SCID_FM_USERAP_TEST TRANSLATIONBLOCK TRANSLATE("TP[0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("TP[1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("TP[2]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("TP[3]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("TP[4]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("TP[5]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("TP[6]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("TP[7]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("TP[8]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("TP[9]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("TP[10]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TP[11]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TP[12]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TP[13]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TP[14]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TP[15]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TP[16]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TP[17]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TP[18]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TP[19]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TP[20]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TP[21]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TP[22]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TP[23]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TP[24]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TP[25]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TP[26]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TP[27]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("TP[28]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("TP[29]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("TP[30]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fc0100 SCID_FM_ISRNP_TEST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04fd011f SCID_FM_ISRAP_TEST TRANSLATIONBLOCK TRANSLATE("TP[0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("TP[1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("TP[2]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("TP[3]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("TP[4]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("TP[5]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("TP[6]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("TP[7]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("TP[8]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("TP[9]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("TP[10]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("TP[11]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("TP[12]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("TP[13]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("TP[14]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("TP[15]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("TP[16]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("TP[17]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("TP[18]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("TP[19]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("TP[20]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("TP[21]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("TP[22]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("TP[23]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("TP[24]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("TP[25]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("TP[26]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("TP[27]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("TP[28]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("TP[29]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("TP[30]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fe0100 SCID_FM_NYI TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04ff011f SCID_FM_OLD_STYLE_BUGCHECK TRANSLATIONBLOCK TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Undefined: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SRR1 (machine state): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Link Register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Stack Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("R31: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("R30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("R29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("R28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("R27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("R26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("R25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("R24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("R23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("R22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("R21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("R20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("R19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("R18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("R17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("R16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("R12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("R11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("R10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("R9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("R8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("R7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("R6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("R5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("R4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("R3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 06040100 SCID_FCS_INIT_MEM_SFQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06150100 SCID_FCS_INIT_FCS_DUMP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 061c0100 SCID_FCS_INIT_MEM_IBQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 061d0100 SCID_FCS_INIT_MEM_MFC_COP_BUF TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06200100 SCID_FCS_INVAL_COMPL_MSG TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06230100 SCID_FCS_CLASS2_OUTB_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0624011f SCID_FCS_HOST_PROGRAMMING_ERROR TRANSLATIONBLOCK TRANSLATE("Callback: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("SEST Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("CDB10B Opcode: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Loc: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28] ); TRANSLATE("SGL ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29] ); TRANSLATE("SGL Byte Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30] ); ENDTRANSLATIONBLOCK TC BLOCK: 06280100 SCID_FCS_INVAL_PORT_EVENT_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06290100 SCID_FCS_UNKNOWN_FED_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062a0100 SCID_FCS_UNKNOWN_LDN_FED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062b0100 SCID_FCS_START_TIMER_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062c0100 SCID_FCS_UNKNOWN_TIMER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062e0100 SCID_FCS_SEST_PROGM_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062f0100 SCID_FCS_UNKNOWN_EXCH_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06320100 SCID_FCS_PORT_OFFLINE_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06330100 SCID_FCS_OUT_RESERVED_FEDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06340100 SCID_FCS_UNSUPPORTED_ELS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06360100 SCID_FCS_UNSUPPORTED_DRIVE_INIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06380100 SCID_FCS_UNSUPPORTED_TDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 063c0100 SCID_FCS_LBA_RANGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06410100 SCID_FCS_UNKNOWN_STATUS_BYTE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06420100 SCID_FCS_NO_BACKEND_PORTS_AVAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06460100 SCID_FCS_UNSUPPORTED_SES_PAGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06470100 SCID_FCS_BAD_STRING_IN_PAGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06500080 SCID_FCS_REMOTE_COUPLE_CRASH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0651011f SCID_FCS_MFC_PROC_ACK_DSI_TRAP TRANSLATIONBLOCK TRANSLATE("MFC Port Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("rcvd_pcb_ptr: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("rcvd_d_id: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("out_credits: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("next_sn: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("last_rcvd_ack: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("delivered_sn: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("last_xferred_ack: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("flags: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("acked_sn: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("process_sn: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10] ); TRANSLATE("ack_cnt: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11] ); TRANSLATE("tunnel_idx: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12] ); TRANSLATE("in-tunnel 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13] ); TRANSLATE("in-tunnel 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14] ); TRANSLATE("in-tunnel 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15] ); TRANSLATE("in-tunnel 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16] ); TRANSLATE("in-tunnel 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17] ); TRANSLATE("in-tunnel 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18] ); TRANSLATE("in-tunnel 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19] ); TRANSLATE("in-tunnel 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20] ); TRANSLATE("in-tunnel 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21] ); TRANSLATE("out-tunnel 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22] ); TRANSLATE("out-tunnel 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23] ); TRANSLATE("out-tunnel 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24] ); TRANSLATE("out-tunnel 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25] ); TRANSLATE("out-tunnel 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26] ); TRANSLATE("out-tunnel 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27] ); TRANSLATE("out-tunnel 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28] ); TRANSLATE("out-tunnel 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29] ); TRANSLATE("out-tunnel 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30] ); ENDTRANSLATIONBLOCK TC BLOCK: 07000100 SCID_CS_INSUFF_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07010100 SCID_CS_LMAP_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07020100 SCID_CS_LMAP_ALLOC_FAIL_2 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07030100 SCID_CS_INVALID_RAID_TYPE_INIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07070100 SCID_CS_QS_READ_FAIL_1 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070a0100 SCID_CS_RSD_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070b0100 SCID_CS_BAD_REF_COUNT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070c0100 SCID_CS_INVALID_OBJECT_FOR_IO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070d0100 SCID_CS_INVALID_IO_RANGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07110100 SCID_CS_RAIDTYPE_NOTSUPPORTED_1 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07130100 SCID_CS_INVALID_RS_RAID_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07140100 SCID_CS_INVALID_STRUCT_MAINZQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07150100 SCID_CS_INVALID_STRUCT_LDSBZQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07160100 SCID_CS_INVALID_STRUCT_ODWORKQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07170100 SCID_CS_PBUFF_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07180100 SCID_CS_XBUFF_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07190100 SCID_CS_NOT_IMPLEMENTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071a0100 SCID_CS_WRONG_LDSB TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071b0100 SCID_CS_WRONG_LDAD_LABORT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071c0100 SCID_CS_INVALID_RM_MAP_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071d0100 SCID_CS_RM_CACHE_HIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071e0100 SCID_CS_INVALID_PSEG_USAGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071f0100 SCID_CS_BAD_OBJ_CLASS_REG_REP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07200100 SCID_CS_NO_CMAPS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07220100 SCID_CS_INVALID_CS_REQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07240100 SCID_CS_NO_REQS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07260100 SCID_CS_BAD_VOLNOID TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07290100 SCID_CS_MULTIPLE_TRANS_DETECTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072a0100 SCID_CS_TRANS_RECOV_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072b0100 SCID_CS_RECOV_INVALID_TRANS_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072d0100 SCID_CS_NO_TRANS_DETECTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072f0100 SCID_CS_ZERO_BAD_MEM_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07300100 SCID_CS_REGENS_NOT_COMPLETE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07340100 SCID_CS_BAD_OBJ_HANDLE_REQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07350100 SCID_CS_INVALID_OP_REQ_HANDLER1 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07370100 SCID_CS_BAD_VOLNOID_SPARING TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07380100 SCID_CS_NO_XDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07390100 SCID_CS_INVALID_RTYPE_REGREASS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073b0100 SCID_CS_UNKNOWN_TRANS_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073c0100 SCID_CS_TRANS_INCONSISTENCY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073d0100 SCID_CS_INVALID_TRANS_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073e0100 SCID_CS_INVALID_STRUCT_LEVELLDQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073f0100 SCID_CS_INVALID_STRUCT_SPARERSQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07400100 SCID_CS_INVALID_STRUCT_CSREQQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07410100 SCID_CS_INVALID_STRUCT_PLDMCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07420100 SCID_CS_NO_RLBS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07430100 SCID_CS_BAD_RLB_LIST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07440100 SCID_CS_BAD_RLB_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07450100 SCID_CS_INVALID_STRUCT_CSLDQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07460100 SCID_CS_INVALID_STRUCT_CSEBITQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07480100 SCID_CS_NONMASTER_QSIO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07490100 SCID_CS_NONMASTER_CSLDIO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074a0100 SCID_CS_INVALID_STRUCT_ACBWQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074b0100 SCID_CS_INVALID_ACBW_OPCODE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074c0100 SCID_CS_INVALID_STRUCT_MAINUNSHQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074f0100 SCID_CS_INVALID_STRUCT_MIGRATE_WORKQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07500100 SCID_CS_INVALID_STRUCT_MIGRATE_RSQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07510100 SCID_CS_BAD_MEM_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07520100 SCID_CS_MELTDOWN TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07530100 SCID_CS_INVALID_STRUCT_ALB_LIST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07540100 SCID_CS_RSTORE_NOT_UTILIZED_IN_MAP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07550100 SCID_CS_INVALID_STRUCT_ALLOC_WQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07570100 SCID_CS_REALIZE_FAILED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07580100 SCID_CS_UNREALIZE_FAILED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07590100 SCID_CS_INIT_ALLOC_UNIT_REALIZED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075b0100 SCID_CS_IO_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075d0100 SCID_CS_INVALID_STRUCT_CSCBITQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075e0100 SCID_CS_INVALID_STRUCT_MAINODBGALOCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075f0100 SCID_CS_BAD_DUB_RSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07600100 SCID_CS_INVALID_LD_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07610100 SCID_CS_BAD_DIP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07620100 SCID_CS_DEALLOC_PSEG_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07630100 SCID_CS_RESERVED_CAPACITY_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07640100 SCID_CS_INVALID_STRUCT_REBUILD_PARITY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07680100 SCID_CS_MEMBER_REMOVED_FROM_RSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07690102 SCID_CS_BAD_MEMBER_MANAGER_STATE TRANSLATIONBLOCK TRANSLATE("Volume NOID: 0x%04x", teb.u.data.ltei.lter.termination_event.params.param[0] ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 0, TRANSLATE("MM Op: IDLE") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 1, TRANSLATE("MM Op: REGEN S") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 2, TRANSLATE("MM Op: REGEN D") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 3, TRANSLATE("MM Op: REPLACE S") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 4, TRANSLATE("MM Op: REPLACE D") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 5, TRANSLATE("MM Op: RESTORE S") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 6, TRANSLATE("MM Op: REVERT") ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 7, TRANSLATE("MM Op: INIT") ); ENDTRANSLATIONBLOCK TC BLOCK: 076a0100 SCID_CS_NO_QUORUM_DISKS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076b0100 SCID_CS_INVALID_PSEG_ALLOC_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076c0100 SCID_CS_XMFC_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076d0100 SCID_CS_INVALID_XMFC_OPERATION TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076e0100 SCID_CS_INVALID_TYPE_IN_RSDM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07700105 SCID_CS_CHKDSK_FAILED TRANSLATIONBLOCK TRANSLATE("Status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Op Code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Error Count: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Error Bits[0]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Error Bits[1]: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 07710100 SCID_CS_INVALID_STRUCT_MAINRESYNCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07720100 SCID_CS_RESYNC_CONTROL_NOT_FOUND TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07730100 SCID_CS_UNEXPECTED_RSD TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07740100 SCID_CS_OUT_OF_ORDER_SHADOW_DATA TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07750100 SCID_CS_UNEXPECTED_REALIZE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08010100 SCID_RS_BAD_EBIT_STATUS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08020100 SCID_RS_BAD_MEMBER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08030100 SCID_RS_BAD_RAID_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08040100 SCID_RS_REWRITE_UNSUPPORTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08050100 SCID_RS_EMPTY_DMA_CONTEXT_Q TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08060100 SCID_RS_FULL_DMA_CONTEXT_Q TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08070100 SCID_RS_CANT_ALLOCATE_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08080100 SCID_RS_UNSUPPORTED_STRUCT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08090100 SCID_RS_SCDBS_CORRUPTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 080a0100 SCID_RS_UNHANDLED_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 080f0100 SCID_RS_OUTOFSYNC_DMA_CONTEXT_Q TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09010100 SCID_SCMI_BQ_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09020100 SCID_SCMI_CP_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09040100 SCID_SCMI_INTERNAL_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09060100 SCID_SCMI_RES_BUF_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09080100 SCID_SCMI_CMDLCK_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09090100 SCID_SCMI_CMDLCK_INIT_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b000100 SCID_SYS_BAD_XMFC_RESPONSE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b010100 SCID_SYS_BAD_MFC_VECTOR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b020100 SCID_SYS_BAD_SACB_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b040100 SCID_SYS_BAD_UTIL_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b052001 SCID_SYS_EEPROM_FAILURE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b062001 SCID_SYS_UUID_RANGE_OVERFLOW TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b080100 SCID_SYS_RESYNC_NOT_ALLOWED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b092003 SCID_SYS_LCD_FAILURE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Failure status: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Message code: %d", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b0a0100 SCID_SYS_BAD_XMFC_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b100021 SCID_SYS_GLUE_CODE_RELOAD TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b110020 SCID_SYS_RESYNC_NOW TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b12db60 SCID_SYS_CODE_LOAD_DENIED TRANSLATIONBLOCK TRANSLATE( "Master controllers code is incompatible with this hardware." ); TRANSLATE( "Upgrade the master controller before restarting this controller." ); ENDTRANSLATIONBLOCK TC BLOCK: 0c010102 SCID_DRM_INVALID_DDS TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c03010c SCID_DRM_INVALID_GSB_DELETE_STATE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Group state (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("EETBs held to acknowledge (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("EETBs or MNODEs Held To Receive (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("Member List (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("Member Count (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE("Control Waiter (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE("Control Wait List empty (should be 1): %d", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("Copy In Progress (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[11]); ENDTRANSLATIONBLOCK TC BLOCK: 0c040101 SCID_DRM_RECOVERY_WRITE_DUPLICATE TRANSLATIONBLOCK TRANSLATE("Group Sequence Number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 0c050106 SCID_DRM_RECOVERY_WRITE_NOT_CACHED TRANSLATIONBLOCK TRANSLATE("LDSB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Group Sequence Number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Block Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Blocks: %d", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Cache Node: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Status: %d", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c060106 SCID_DRM_RECOVERY_WRITE_NOT_DIRTY TRANSLATIONBLOCK TRANSLATE("LDSB: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Group Sequence Number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Block Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Blocks: %d", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Cache Node: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Cache Node State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c070106 SCID_DRM_RECOVERY_WRITE_LOST_GNODE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c080106 SCID_DRM_INVALID_SCRAG_MIRROR_RIE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("RIE Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("RIE State Field: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c090106 SCID_DRM_INVALID_SCRAG_MIRROR_MEMBERS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Online count: %d", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("GCA Entry Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0a0106 SCID_DRM_INVALID_SCRAG_PRIMARY_RIE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("RIE Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("RIE State (should be 0): %d", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0b0106 SCID_DRM_INVALID_SCRAG_PRIMARY_MEMBERS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Online count: %d", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("GCA Entry Address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0c0104 SCID_DRM_INVALID_GSB_DELETE_IO TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0d0104 SCID_DRM_INVALID_GSB_INSERT TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0e0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_1 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0f0105 SCID_DRM_WRITE_LONG_E_SET_FAILED TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c100104 SCID_DRM_INVALID_ACQUIRE_DRRW TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 0c110105 SCID_DRM_LOST_GNODE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c130105 SCID_DRM_IO_FAILURE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Lock State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c140106 SCID_DRM_GSN_OUT_OF_SEQUENCE_2 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c150106 SCID_DRM_GSN_OUT_OF_SEQUENCE_3 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c160106 SCID_DRM_GSN_OUT_OF_SEQUENCE_4 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c170106 SCID_DRM_GSN_OUT_OF_SEQUENCE_5 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c180106 SCID_DRM_GSN_OUT_OF_SEQUENCE_6 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c190106 SCID_DRM_GSN_OUT_OF_SEQUENCE_7 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1a0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_8 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1b0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_9 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1c0107 SCID_DRM_GSN_OUT_OF_SEQUENCE_10 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("RIE State (should be 0): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 0c200106 SCID_DRM_GSN_OUT_OF_SEQUENCE_11 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c210106 SCID_DRM_GSN_OUT_OF_SEQUENCE_12 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Group Online GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("GSN to use + Write Resources Per Bundle: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c220108 SCID_DRM_GSN_OUT_OF_SEQUENCE_13 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Group Online GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("Group Mode: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("Log Flags: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); ENDTRANSLATIONBLOCK TC BLOCK: 0c230105 SCID_DRM_UNEXPECTED_UNIT_CACHE_STATE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Unit Cache State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c240107 SCID_DRM_INVALID_SIDE TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Requested Side: %d", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("Actual Side: %d", teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 0c270106 SCID_DRM_GSN_OUT_OF_SEQUENCE_14 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c280106 SCID_DRM_GSN_OUT_OF_SEQUENCE_15 TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Expected GSN: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c290105 SCID_DRM_INVALID_DDS_ADD_MEMBER TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2a0106 SCID_DRM_INVALID_DDS_ACK_DAS TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2b0102 SCID_DRM_INVALID_DDS_ACK_WAIT TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2c0102 SCID_DRM_INVALID_DDS_WAIT_DONE TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2d0105 SCID_DRM_INVALID_DDS_DAS_BUILD TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2e0105 SCID_DRM_INVALID_DDS_DSF_BUILD TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2f0106 SCID_DRM_INVALID_DDS_DRRW_ACK TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c300105 SCID_DRM_INVALID_DDS_DRRW_BUILD TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c310105 SCID_DRM_INVALID_DDS_GOB_BUILD TRANSLATIONBLOCK TRANSLATE("Data Replication Group: %08x %08x %08x %08x", teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c320101 SCID_DRM_INVALID_DDS_MAIN TRANSLATIONBLOCK TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c330103 SCID_DRM_INVALID_DDS_MANAGE TRANSLATIONBLOCK TRANSLATE("MFC function: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c340101 SCID_DRM_DUAL_MANAGE_EETB_IN_USE TRANSLATIONBLOCK TRANSLATE("MFC function: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c350101 SCID_DRM_DUAL_MANAGE_NULL_EETB TRANSLATIONBLOCK TRANSLATE("MFC function: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c360102 SCID_DRM_INVALID_DDS_SIMPLE TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c370102 SCID_DRM_INVALID_DDS_SIMPLE_WAIT TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c380102 SCID_DRM_INVALID_DDS_SIMPLE_BUILD TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c390102 SCID_DRM_INVALID_DDS_SOB_BUILD TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3a0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3b0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT_RESP TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3c0102 SCID_DRM_INVALID_DDS_MIRROR_BROKEN TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3d0102 SCID_DRM_INVALID_DDS_MIRROR_REQUEST_ACK TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3e0102 SCID_DRM_INVALID_DDS_MIRROR_BUILD TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3f0102 SCID_DRM_INVALID_DDS_MIRROR_RSP_ACK TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c400102 SCID_DRM_INVALID_DDS_MIRROR_RSP_BUILD TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c410102 SCID_DRM_INVALID_DDS_SITE_FAILOVER TRANSLATIONBLOCK TRANSLATE("DDS Expected State: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c420102 SCID_DRM_INVALID_DDS_SYNCH_BUFFS_ACK TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c430102 SCID_DRM_INVALID_DDS_UPDATE_MDW_ACK TRANSLATIONBLOCK TRANSLATE("MFC Status: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("DDS State: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c450100 SCID_DRM_INVALID_CODE_PATH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c460103 SCID_DRM_CORRUPT_MFC_FRAME TRANSLATIONBLOCK TRANSLATE("FRAME_SIZE: %d", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("SLOT_INDEX: %d", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("FRAME_INDEX: %d", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c470104 SCID_DRM_HOST_ACB TRANSLATIONBLOCK TRANSLATE("ACB address: %x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("ACB index: %x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Port WWN (high): %x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Port WWN (low): %x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c480100 SCID_DRM_INIT_FAIL_DDCB_ALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c490100 SCID_DRM_INIT_FAIL_RNSB_ALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c4a0104 SCID_DRM_TEMP_ACB TRANSLATIONBLOCK TRANSLATE("ACB address: %x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("ACB index: %x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Port WWN (high): %x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Port WWN (low): %x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 0e000020 SCID_SDC_INVALID_BATT_SYS_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e010020 SCID_SDC_INVALID_HOLDUP_TIME TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e020020 SCID_SDC_INVALID_BRICK_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e030020 SCID_SDC_INVALID_BRICK_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e050020 SCID_SDC_INVALID_BLOWER_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e060020 SCID_SDC_INVALID_BLOWER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e080020 SCID_SDC_INVALID_TEMPERATURE_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e090020 SCID_SDC_INVALID_PWR_SUPPLY_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e0a0020 SCID_SDC_INVALID_PWR_SUPPLY_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e0b0020 SCID_SDC_COMMAND_SEND_COLLISION TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 42000101 SCID_HP_INIT_FAIL_MEM_ALLOC TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 42050103 SCID_HP_UNEXPECTED_CACHE_LOCK TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42060105 SCID_HP_UNEXPECTED_SCSI_COMMAND TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 42070123 SCID_HP_DROP_DEAD_CNDR TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420801a3 SCID_HP_DROP_DEAD_CCNDR TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420901c3 SCID_HP_DROP_DEAD_DC TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420c0184 SCID_HP_UNKNOWN_RSCSI_BUILD_CONTEXT TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 420d0182 SCID_HP_UNKNOWN_RSCSI_RECEIVE_CONTEXT TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 420e0181 SCID_HP_ICOPS_OUT_OF_MEMORY TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 420f0182 SCID_HP_ICOPS_UNKNOWN_BUILD_CONTEXT TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42100182 SCID_HP_ICOPS_UNKNOWN_RECIEVE_CONTEXT TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42120104 SCID_HP_ILLEGAL_INPROCQ TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 42130101 SCID_HP_NO_CMD_HTBS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 42140102 SCID_HP_INVALID_RCV_DATA_CTX TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42150102 SCID_HP_CHMOD_NO_ACB TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42160102 SCID_HP_PRESENT_LUN_NO_ACB TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42190104 SCID_HP_INVALID_CCB_STATE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 421b0102 SCID_HP_INVALID_WORK_REQ_TYPE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 421c0101 SCID_HP_NO_WORK_REQUESTS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 421e0102 SCID_HP_CMD_HTB_IN_USE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42230102 SCID_HP_UNPLUN_NO_ACB TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42250104 SCID_HP_BAD_ACB_DEL TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 42260104 SCID_HP_NO_UA_TABLE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 42270108 SCID_HP_UNKNOWN_PORT_EVENT TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); ENDTRANSLATIONBLOCK TC BLOCK: 42280102 SCID_HP_UNKNOWN_CM TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42290103 SCID_HP_ILLEGAL_SEST_ID TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422a0103 SCID_HP_BAD_ALPA_ON_PTP TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422b0103 SCID_HP_UNKNOWN_IDLE_STATUS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422c0003 SCID_HP_TACHYON_ERROR TRANSLATIONBLOCK TRANSLATE("Unique identifier 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Bad port number (zero-based): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("PCI interrupt status register: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422d010a SCID_HP_UNKNOWN_IO_ERROR TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); ENDTRANSLATIONBLOCK TC BLOCK: 422e0104 SCID_HP_ILLEGAL_LUN_ACCESS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 422f0103 SCID_HP_UNKNOWN_INBOUND_STATUS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42300103 SCID_HP_ILLEGAL_SCRIPT_RSP TRANSLATIONBLOCK TRANSLATE("Unique identifier 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Function that returned bad response: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Bad response: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42310102 SCID_HP_BAD_SCRIPT_ERROR_STATUS TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42320104 SCID_HP_DUPLICATE_LUN TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 4233010a SCID_HP_INVALID_IMMEDIATE_ERROR TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); ENDTRANSLATIONBLOCK TC BLOCK: 42340104 SCID_HP_INVALID_HTBX_STATE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 42350104 SCID_HP_INVALID_UNQUIESCE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 42360102 SCID_HP_INVALID_CSEL_STATE TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42370183 SCID_HP_EVENT_NOTIFY_GAP TRANSLATIONBLOCK TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Parameter to assist in analysis 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 4238011f SCID_HP_CSM_HANG TRANSLATIONBLOCK TRANSLATE("CSM stack 0: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("CSM stack 1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("CSM stack 2: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("CSM stack 3: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("CSM stack 4: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("CSM stack 5: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("CSM stack 6: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("CSM stack 7: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("CSM stack 8: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("CSM stack 9: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("CSM stack 10: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("CSM stack 11: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("CSM stack 12: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("CSM stack 13: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("CSM stack 14: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("CSM stack 15: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("CSM stack 16: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("CSM stack 17: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("CSM stack 18: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("CSM stack 19: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("CSM stack 20: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("CSM stack 21: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("CSM stack 22: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("CSM stack 23: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("CSM stack 24: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE("CSM stack 25: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE("CSM stack 26: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE("CSM stack 27: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE("CSM stack 28: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE("CSM stack 29: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE("CSM stack 30: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 42390184 SCID_HP_PROXY_BAD_STATE TRANSLATIONBLOCK TRANSLATE("Bad Proxy IO MFC State: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("State value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Expected state: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("HTB Pointer: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 423a0102 SCID_HP_TACHERR_BOGUS_PORT TRANSLATIONBLOCK TRANSLATE("Bogus port number (zero-based): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Bogus port number (zero-based): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 423b0102 SCID_HP_TACH_NOT_RESPONDING TRANSLATIONBLOCK TRANSLATE("Bad port number (zero-based): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Bad port number (zero-based): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 423c0306 SCID_HP_ADD_CA_ACB TRANSLATIONBLOCK TRANSLATE("ACB address: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("ACB index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("Data Replication Manager flag: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("New index: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Remote port wwn (high): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Remote port wwn (low): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 83002061 SCID_DOG_CANNOT_BRANCH_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 83012079 SCID_DOG_UNEXPECTED_VECTOR_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Pointer to ASCII error message: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("TE number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Test number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Error code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Address of BUD: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Exception type: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("SRR0 at interrupt: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("SRR1/MSR at interrupt: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("LR: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("UIC status: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE("UIC mask: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE("UIC critical: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE("GLUE IS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE("GLUE MCPE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE("GLUE NPIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE("GLUE NPIE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE("GLUE ACNS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE("GLUE APNS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE("GLUE FPIS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE("GLUE FPIE: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE("GLUE ACFS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE("GLUE APFS: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE("QSR ERRDET1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE("QSR ERREN1: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[24]); ENDTRANSLATIONBLOCK TC BLOCK: 8302206b SCID_DOG_HARD_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE("Pointer to ASCII error message: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE("TE number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE("Test number: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE("Error code: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE("Address of BUD: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE("Address of error: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE("Expected data (hi): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE("Expected data (lo): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE("Actual data (hi): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE("Actual data (lo): 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[10]); ENDTRANSLATIONBLOCK TC BLOCK: 84032069 SCID_DRS_XL_EXCESSIVE_CM_CDES TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Cache memory size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Current number of detected errors: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Previous number of detected errors: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Number of seconds over which errors occurred: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE("Sprite's m_ese, even ECC status, register value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE("Sprite's m_eso, odd ECC status, register value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE("Sprite's m_eae, even ECC address, register value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE("Sprite's m_eae, odd ECC address, register value: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[8]); ENDTRANSLATIONBLOCK TC BLOCK: 84042065 SCID_DRS_XL_EXCESSIVE_PM_CDES TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( "Single Power Supply HSV200 Controller" ) ); TRANSLATE("DIMM size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE("Cache memory size: %d MB", teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE("Current number of detected errors: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE("Previous number of detected errors: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE("Number of seconds over which errors occurred: 0x%08x", teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK DEFINITIONS: %[scmi_nsc_restart_option] 0 = None -- no restart 1 = Regular -- full restart, host system connectivity is lost until the controller returns to normal operation 2 = Fast -- resynchronization, restart of the controller in a manner that has little or no impact on host system connectivity %[scmi_nsc_battery_present_condition] 0 = Not present 1 = Present %[scmi_group_auto_suspend_state] 1 = Connection between the Data Replication Source and Data Replication Destination is active. 2 = Connection between the Data Replication Source and Data Replication Destination is inactive. %[scmi_nsc_fc_port_condition] 1 = Normal 2 = Failed %[scmi_read_disk_cache_policy_type] 1 = Read cache on 2 = Read cache off %[scmi_fan_status] 1 = Normal 2 = Elevated 3 = High 4 = Bad 5 = Unknown 6 = Not Present %[scmi_rundown_flag] 0 = Flag is off, log is NOT in rundown mode, normal operation 1 = Flag is on, log is in rundown mode %[scmi_nsc_shutdown_other_option] 0 = Remain operational 1 = Coupled shutdown %[scmi_logical_disk_data_availability_condition] 0 = Data available 1 = Data lost %[scmi_object_function_code] 1001 = Derived Unit Create 1002 = Derived Unit Discard 1003 = Derived Unit Get Device Identifier 1004 = Derived Unit Get Presented Units 1005 = Derived Unit Get Presented Units Count 1006 = Derived Unit Get Storage System Virtual Disk 1007 = Derived Unit Is Write Protected 1008 = Derived Unit Set Write Protected 1009 = Derived Unit Get Settable Id 1010 = Derived Unit Set Settable Id 1011 = *** 1011 no longer used *** Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 2001 = Logical Disk Clear Data Lost 2002 = *** 2002 not used *** 2003 = *** 2003 not used *** 2004 = Logical Disk Create 2005 = Logical Disk Discard 2006 = Logical Disk Get Allocated Capacity 2007 = Logical Disk Get Allocated Storage 2008 = Logical Disk Get Condition 2009 = Logical Disk Get Default SCM EP Id 2010 = Logical Disk Get Disk Group 2011 = Logical Disk Get Master Controller 2012 = *** 2012 not used *** 2013 = Logical Disk Get Redundancy 2014 = Logical Disk Get Reserved Capacity 2015 = Logical Disk Is Data Lost 2016 = Logical Disk Offline 2017 = Logical Disk Online 2018 = *** 2018 not used *** 2019 = *** 2019 not used *** 2020 = *** 2020 not used *** 2021 = *** 2021 not used *** 2022 = Logical Disk Set Reserved Capacity 2023 = Logical Disk Verify 2024 = *** 2024 not used *** 2025 = *** 2025 no longer used *** 2026 = *** 2026 no longer used *** 2027 = Logical Disk Get Successor Logical Disk 2028 = Logical Disk Snapclone 2029 = Logical Disk Snapshot 2030 = Logical Disk Get Predecessor Logical Disk 2031 = Logical Disk Get Preferred Controller 2032 = Logical Disk Set Preferred Controller 2033 = Logical Disk Get Logical Disk Type 2034 = Logical Disk Get LUN WWID 2035 = Logical Disk Set LUN WWID 2036 = Logical Disk Attach Snaps 2037 = Logical Disk Clear Container 2038 = Logical Disk Mirror Clone 2039 = Logical Disk Restore When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 3001 = Disk Group Create 3002 = Disk Group Discard 3003 = Disk Group Get Capacity 3004 = Disk Group Get Max Logical Disk Size 3005 = Disk Group Get Occupancy 3006 = Disk Group Get Occupancy Highwater 3007 = Disk Group Get Volumes 3008 = Disk Group Get Volumes Count 3009 = Disk Group Set Occupancy Highwater 3010 = Disk Group Get Management Logical Disk Size 3011 = Disk Group Read Management Logical Disk 3012 = Disk Group Write Management Logical Disk 3013 = Disk Group Get Spares Current 3014 = Disk Group Get Spares Goal 3015 = Disk Group Set Spares Goal 3016 = Disk Group Get Condition 3017 = Disk Group Resolve Condition 3018 = Disk Group Locate 3019 = Disk Group Create New 3020 = Disk Group Add Volumes 3021 = Disk Group Write Management Logical Disk Blocks 3022 = Disk Group Get Leveling Info 3023 = Disk Group Get SRC 3024 = Disk Group Locate RSS 3025 = Disk Group Get Volumes Info 3026 = Disk Group Set Requested SRC Mode 3027 = Disk Group Get LDAD info 3028 = Disk Group Get drive type 3029 = Disk Group Set Name Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 4001 = Controller Crash 4002 = Controller Generate Id 4003 = *** 4003 no longer used *** 4004 = *** 4004 no longer used *** 4005 = Controller Get Cache Capacity 4006 = Controller Get Cache Condition 4007 = Controller Get Condition 4008 = Controller Get Default SCM EP Id 4009 = Controller Get Fibre Channel Context Id 4010 = Controller Get Firmware Version 4011 = *** 4011 no longer used *** 4012 = Controller Get Identity 4013 = *** 4013 no longer used *** 4014 = *** 4014 no longer used *** 4015 = *** 4015 no longer used *** 4016 = Controller Get Loop Port Node Id 4017 = Controller Get Loop Port Node Type 4018 = Controller Get Loop Port Position 4019 = *** 4019 no longer used *** 4020 = *** 4020 no longer used *** 4021 = *** 4021 no longer used *** 4022 = *** 4022 no longer used *** 4023 = Controller Get Controllers 4024 = Controller Get Controllers Count 4025 = Controller Get Participation 4026 = Controller Get Storage System 4027 = Controller Get Supported Class Versions 4028 = Controller Maintenance Invoke Routine 4029 = Controller Maintenance Read Memory 4030 = Controller Read Dump 4031 = Controller Read ILF Log 4032 = Controller Set Default SCM EP Id 4033 = Controller Set ILF Log Mask 4034 = Controller Set Participation 4035 = Controller Shutdown 4036 = Controller Get Physical Stores 4037 = Controller Get Physical Stores Count 4038 = *** 4038 no longer used *** 4039 = Controller Get Unassigned Host Ports 4040 = Controller Get Unassigned Host Ports Count 4041 = Controller Get Enclosure Status 4042 = Controller Set Enclosure Fan High Speed Mode 4043 = Controller Set Enclosure Temp Trip Point 4044 = Controller Get Hardware Info 4045 = Controller Get Fibre Channel Node Id 4046 = Controller Get Fibre Channel Port Address 4047 = Controller Get Fibre Channel Port Condition 4048 = Controller Get Fibre Channel Port Id 4049 = Controller Get Fibre Channel Port Type 4050 = Controller Get ILF Component Mask 4051 = Controller Get ILF Component Class Mask 4052 = Controller Get ILF Disk Slot 4053 = Controller Set ILF Component Mask 4054 = Controller Set ILF Component Class Mask 4055 = Controller Set ILF Disk Slot 4056 = Controller Get Battery System Capacity 4057 = Controller Get Battery System Condition 4058 = Controller Get Battery Hardware Status 4059 = Controller Get UPS Condition 4060 = Controller Login 4061 = Controller Logout 4062 = Controller Save Firmware 4063 = Controller Use Firmware 4064 = Controller Locate 4065 = Controller Login Step1 4066 = Controller Login Step2 4067 = Controller Get Disk Enclosures 4068 = Controller Get Disk Enclosures Count 4069 = Controller Get Disk Enclosures Status 4070 = Controller Get Disk Enclosure Page 4071 = Controller Locate Disk Enclosure 4072 = Controller Set Disk Enclosure Audible Alarm 4073 = Controller Get Host Port Info 4074 = Controller Get Drive Code Load Info 4075 = Controller Get Loop Port Node Info 4076 = Controller Get Fibre Channel Port Info 4077 = Controller Get Physical Stores Info 4078 = Controller Read Termination Events 4079 = Controller Read Events Activeq 4080 = Controller Open Events Activeq 4081 = Controller Close Events Activeq 4082 = Controller Get Crash Dump Info 4083 = Controller Open Crash Dump 4084 = Controller Read Crash Dump 4085 = Controller Close Crash Dump 4086 = Controller Open ILF Memory 4087 = Controller Read ILF Memory 4088 = Controller Close ILF Memory 4089 = Controller Enable Loop Port 4090 = Controller Get Loop Port Node Error 4091 = Controller Clear Loop Port Node Error 4092 = Controller Start DILX 4093 = Controller Stop DILX 4094 = Controller Get DILX Summary 4095 = Controller Get ncs info 4096 = Controller Get memory size 4097 = Controller Free Unassigned Host Ports 4098 = Get EPBC Error counts 4099 = Controller Read CHECKPOINT Memory 4100 = Controller Close CHECKPOINT Memory 4101 = Controller Open CHECKPOINT Memory 4102 = Request log size Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 5001 = *** 5001 not used *** 5002 = *** 5002 not used *** 5003 = *** 5003 not used *** 5004 = *** 5004 not used *** When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 6001 = Physical Store Clear Failed 6002 = Physical Store Erase Volume 6003 = Physical Store Get Capacity 6004 = Physical Store Get Condition 6005 = Physical Store Get LUN 6006 = Physical Store Get Maintenance Mode 6007 = Physical Store Get Physical Device 6008 = Physical Store Get Volume 6009 = Physical Store Is Failed 6010 = Physical Store Is Failure Predicted 6011 = Physical Store Is Media Inaccessible 6012 = Physical Store Read Inquiry Strings 6013 = *** 6013 no longer used *** 6014 = Physical Store Read Volume Is Quorum Disk 6015 = Physical Store Read Volume Disk Group Id 6016 = Physical Store Read Volume Storage System Id 6017 = Physical Store Read Volume Storage System Name 6018 = Physical Store Send Command 6019 = Physical Store Set Maintenance Mode 6020 = Physical Store Read Node Id 6021 = Physical Store Locate 6022 = Physical Store Get drive type Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c 6023 = Physical Store Get drive type When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 7001 = Presented Unit Create 7002 = Presented Unit Discard 7003 = Presented Unit Get Derived Unit 7004 = Presented Unit Get LUN 7005 = Presented Unit Get Storage System Client 7006 = Presented Unit Set LUN 7007 = *** 7007 no longer used *** 7008 = *** 7008 no longer used *** 7009 = Presented Unit Get Reservation Type When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 8001 = Storage System Create 8002 = Storage System Discard 8003 = Storage System Get Context Id 8004 = *** 8004 no longer used *** 8005 = Storage System Get Device Addition Policy 8006 = *** 8006 not used *** 8007 = Storage System Get Events 8008 = *** 8008 no longer used *** 8009 = *** 8009 no longer used *** 8010 = Storage System Get Master Controller 8011 = *** 8011 no longer used *** 8012 = Storage System Get Name 8013 = *** 8013 no longer used *** 8014 = *** 8014 no longer used *** 8015 = Storage System Get Supported Class Versions 8016 = Storage System Get Time 8017 = Storage System Get Volume Replacement Delay 8018 = Storage System Lookup Object 8019 = Storage System Lookup Object Count 8020 = Storage System Prepare Create 8021 = *** 8021 no longer used *** 8022 = Storage System Set Device Addition Policy 8023 = *** 8023 no longer used *** 8024 = Storage System Set Name 8025 = *** 8025 no longer used *** 8026 = Storage System Set Time 8027 = Storage System Set Volume Replacement Delay 8028 = Storage System Translate Id To Handle 8029 = *** 8029 no longer used *** 8030 = Storage System Free Command Lock 8031 = Storage System Get Command Lock Description 8032 = Storage System Get Command Lock Status 8033 = Storage System Set Default Lock Timeout 8034 = Storage System Set Override Lock Timeout 8035 = Storage System Take Command Lock 8036 = Storage System Get SACD Settable Id 8037 = Storage System Set SACD Settable Id 8038 = Storage System Read Controller Termination Events 8039 = Storage System Sync Reset 8040 = *** 8040 not used *** 8041 = Storage System Get Ups Mode 8042 = Storage System Set Ups Mode 8043 = Storage System Resolve Condition 8044 = Storage System Get Connection Status 8045 = Storage System Get Performance Geometry 8046 = Storage System Get Performance Data 8047 = Storage System Create New 8048 = Storage System Get Logical Disks Info 8049 = Storage System Get Groups Info 8050 = Storage System Get Vdisk Info 8051 = Storage System Get Object Class Status 8052 = Storage System Update Object Class Status Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 9001 = *** 9001 no longer used *** 9002 = Storage System Client Create 9003 = Storage System Client Discard 9004 = Storage System Client Get Client Connections 9005 = Storage System Client Get Client Connections Count 9006 = *** 9006 no longer used *** 9007 = *** 9007 no longer used *** 9008 = *** 9008 no longer used *** 9009 = Storage System Client Add Port WWN 9010 = Storage System Client Get Port WWNs 9011 = Storage System Client Get Port WWNs Count 9012 = Storage System Client Remove Port WWN 9013 = Storage System Client Get Client Mode 9014 = Storage System Client Set Client Mode 9015 = Storage System Client Get Client Mode New 9016 = Storage System Client Set Client Mode New 9017 = Storage System Get Name 9018 = Storage System Set Name When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 10001 = Storage System Virtual Disk Create 10002 = Storage System Virtual Disk Disable 10003 = Storage System Virtual Disk Discard 10004 = Storage System Virtual Disk Enable 10005 = *** 10005 no longer used *** 10006 = Storage System Virtual Disk Get Capacity 10007 = Storage System Virtual Disk Get Derived Units 10008 = Storage System Virtual Disk Get Derived Units Count 10009 = Storage System Virtual Disk Get Logical Disk 10010 = Storage System Virtual Disk Get State 10011 = Storage System Virtual Disk Is Quiesced 10012 = *** 10012 no longer used *** 10013 = Storage System Virtual Disk Set Capacity 10014 = Storage System Virtual Disk Set Logical Disk 10015 = Storage System Virtual Disk Set Quiesced 10016 = Storage System Virtual Disk Get DRM Copy State 10017 = Storage System Virtual Disk Get Group Handle 10018 = Storage System Virtual Disk Is Log Unit 10019 = Storage System Virtual Disk Set Group 10020 = Storage System Virtual Disk Set Group None 10021 = Storage System Virtual Disk Get Disk Cache Policy 10022 = Storage System Virtual Disk Set Disk Cache Policy 10023 = Storage System Virtual Disk Get Remote Storage System Virtual Disk Count 10024 = Storage System Virtual Disk Get Remote Storage System Virtual Disks 10025 = Storage System Virtual Disk Set Name When adding new opcodes, first read comment above V_SCMI_cmd_table_index. 11001 = Volume Clear Failure Predicted 11002 = Volume Create 11003 = Volume Data Security Erase 11004 = Volume Fail Missing Blocks 11005 = Volume Get Capacity 11006 = Volume Get Condition 11007 = Volume Get Disk Group 11008 = Volume Get Occupancy 11009 = Volume Get Physical Store 11010 = Volume Get Requested Usage 11011 = Volume Get Usage 11012 = Volume Is Failure Predicted 11013 = Volume Is Insufficient Resources 11014 = Volume Is Quorum Disk 11015 = Volume Set Requested Usage 11016 = Volume Get RSS Info When adding new opcodes, first read comment above V_SCMI_cmd_table_index. Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c 12001 = Group Create 12002 = Group Discard 12003 = Group Get DRM Log State 12004 = Group Get Failsafe 12005 = Group Get Failsafe Locked 12006 = Group Get Log Storage System Virtual Disk Handle 12007 = Group Get Member Count 12008 = Group Get Members 12009 = Group Get Mode 12010 = Group Get Operation 12011 = Group Get Remote Storage System Count 12012 = Group Get Remote Storage Systems 12013 = Group Get Suspend 12014 = Group Set Site Failover 12015 = Group Set Mode 12016 = Group Set Failsafe 12017 = Group Set Operation 12018 = Group Set Suspend 12019 = Group Get Generation 12020 = Group Get Group Name 12021 = Group Get Read Only 12022 = Group Set Read Only 12023 = *** 12023 not used *** 12024 = *** 12024 not used *** 12025 = Group Get Comment 12026 = Group Get User Name 12027 = Group Set Comment 12028 = Group Set User Name 12029 = Group Get Capacity For Logging 12030 = Group Get Member Condition 12031 = 12031 No longer used 12032 = Group Invalidate Log 12033 = Group Set Max Log Size 12034 = Group Set Destination Presentation 12035 = Group Set Auto Suspend 12036 = V4 and later style Group Create 12037 = Group Get Info 12038 = Group Set Defer Copy When adding new opcodes, first read comment above V_SCMI_cmd_table_index. Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c 13001 = Remote Node Discard 13002 = Remote Node Get Info 13003 = Remote Node Purge 13004 = Remote Node Reset DRM Port Pref 13005 = Remote Node Set DRM Port Preferences %[scmi_nsc_shutdown_poweroff_option] 0 = Remain in the power on state 1 = Power itself off %[scmi_temp_system_state] 1 = Normal 2 = Critical 3 = Over Temperature 4 = Unknown %[scmi_nsc_condition] 1 = Normal 2 = *** 2 not used *** 3 = Failed %[scmi_volume_usage] 1 = Disk Group 2 = Reserved 3 = *** 3 no longer used *** 4 = Temporarily reserved for drive code load 5 = Temporarily reserved for drive code load 6 = Temporarily reserved for drive code load 7 = Temporarily reserved for drive code load 8 = Temporarily reserved for drive code load 9 = Temporarily reserved for drive code load 10 = Temporarily reserved for drive code load 11 = Temporarily reserved for drive code load 12 = Temporarily reserved for drive code load 13 = Temporarily reserved for drive code load 14 = Temporarily reserved for drive code load 15 = Temporarily reserved for drive code load 16 = Temporarily reserved for drive code load 17 = Temporarily reserved for drive code load 18 = Temporarily reserved for drive code load 19 = Temporarily reserved for drive code load 20 = Temporarily reserved for drive code load %[scmi_volume_condition] 1 = Normal - Volume is present and operating normally 2 = Migrating - Data from this volume is being moved to other storage in this Disk Group 3 = Missing - Volume is inaccessible 4 = Reconstructing - Volume is inaccessible; redundant data is being regenerated and moved to other storage in this Disk Group 5 = Completing - This previously inaccessible volume has become accessible; data migration is being completed 6 = Reverting - This previously inaccessible volume has become accessible; data is being regenerated 7 = Failed - Volume is not being used in the Disk Group; disk errors are preventing normal usage %[scmi_storagecell_device_addition_policy] 1 = Manual (Extrinsic) 2 = Automatic (Intrinsic) %[scmi_write_disk_cache_policy_type] 1 = Writethrough 2 = Writeback %[scmi_shutdown] 1 = Success 2 = Failure 3 = Not Applicable %[scmi_power_supply_state] 1 = Good 2 = Bad 3 = Unknown 4 = Not Present %[scmi_battery_brick_status_code] 0 = Unknown 16 = Too Old 32 = Charger Fault 48 = Faulted 64 = Temperature Fault 80 = Charging 96 = Charged 112 = Under Load Test 128 = Code Load 144 = Bad Charger %[scmi_nsc_fanps_present_condition] 0 = Not present 1 = Present %[scmi_group_operation_type] 1 = Synchronous 2 = Asynchronous %[scmi_nsc_battery_use_condition] 0 = Not in use 1 = In use %[scmi_physical_store_condition] 1 = Normal 2 = Degraded 3 = Failed 4 = Not present 5 = Single port on Fibre %[scmi_nsc_shutdown_encl_poweroff_option] 0 = Remain in the power on state 1 = Powered off %[scmi_logical_disk_type] 1 = Original Disk 2 = Space Efficient Snapshot 3 = Space Inefficient Snapshot 4 = Snapclone 5 = Unknown 6 = Empty Container 7 = Mirror Clone %[scmi_group_drm_ld_state] 1 = Operative 2 = Inoperative %[scmi_group_suspend_state] 1 = Connection between the Data Replication Source and Data Replication Destination is active. 2 = Connection between the Data Replication Source and Data Replication Destination is inactive. %[scmi_ldad_condition] 1 = Normal 2 = Disk Group with no redundancy is inoperative 3 = Disk Group with parity redundancy is inoperative 4 = Disk Group with mirrored redundancy is inoperative 5 = Disk Group with no redundancy is inoperative, marked for re-use 6 = Disk Group with parity redundancy is inoperative, marked for re-use 7 = Disk Group with mirrored redundancy is inoperative, marked for re-use %[scmi_volume_resource_availability_condition] 0 = Sufficient resources available 1 = Insufficient resources available %[scmi_group_readonly_type] 0 = Data Replication Destination Storage System Virtual Disk disabled for read access. 1 = Data Replication Destination Storage System Virtual Disk enabled for read access. %[scmi_group_drm_mode] 0 = Normal Active Source 1 = Normal Active Destination 2 = Active/Active (Master) 3 = Active/Active (Slave) %[scmi_nsc_shutdown_battass_failure_mode] 0 = No failure indicated. 1 = Failed only on this controller 2 = Failed only on the other controller of the pair. 3 = Failed on both controllers. %[scmi_battery_brick_state] 1 = Good 2 = Bad 3 = Unknown 4 = Not Present %[scmi_volume_quorum_disk_condition] 0 = Not quorum disk 1 = Quorum disk %[scmi_mirror_disk_cache_policy_type] 1 = Mirror 2 = No mirror %[scmi_logical_disk_redundancy_type] 1 = Vraid0 2 = Vraid1 3 = Vraid5 %[scmi_nsc_fan_present_condition] 0 = Not present 1 = Present %[scmi_group_dest_present_state] 0 = Data Replication Destination Storage System Virtual Disk disabled for destination presentation. 1 = Data Replication Destination Storage System Virtual Disk enabled for destination presentation. %[scmi_logical_disk_condition] 1 = Normal 2 = Replacement delay in progress 3 = Redundancy lost, restore in progress 4 = Redundancy lost, restore stalled 5 = Failed 6 = Creation in progress 7 = Snapshot is inoperative due to lack of snapshot space 8 = Deletion in progress 9 = Capacity expand in progress + progress + 10 = Inoperative due to data lost 11 = Capacity reservation in progress 12 = Capacity unreservation in progress 13 = Snap deletion in progress 14 = Attaching empty container as snapclone in progress 15 = Attaching empty container as snapshot in progress 16 = Clearing container in progress 17 = Attaching empty container as mirror clone in progress 18 = Resyncing mirror clone in progress + 19 = Detaching mirror clone in progress + 20 = Fracture mirror clone in progress + 21 = Mirror clone fractured + 22 = Invalidated 23 = Source of instant restore + 24 = Target of instant restore + 25 = Instant restore taking place in tree + 26 = Capacity shrink in progress + %[scmi_logical_disk_snap_attach_type] 0 = Snapshot 1 = SnapClone 2 = Mirror Clone %[scmi_du_write_protect_condition] 0 = Write protect off 1 = Write protect on %[scmi_state] 1 = Disabled 2 = Enabled %[scmi_client_mode] 0 = Unknown 1 = User defined 2 = *** 2 not used *** 3 = WINNT with SecurePath 4 = VMS 5 = TRU64 UNIX 6 = Sun UNIX 7 = NetWare 8 = HP 9 = IBM 10 = LINUX 11 = SCO UNIX 12 = VMWARE 13 = Windows "Longhorn" Server %[scmi_scvd_quiescent_condition] 0 = Not quiescent 1 = Quiescent %[scmi_nsc_battery_system_condition] 1 = Good 2 = *** 2 not used *** 3 = Low 4 = *** 4 not used *** 5 = Bad 6 = Unkown %[scmi_group_defer_copy_state] 1 = Connection between the Data Replication Source and Data Replication Destination is active. 2 = Connection between the Data Replication Source and Data Replication Destination is inactive. %[scmi_nsc_shutdown_battass_option] 0 = Enabled 1 = Disabled %[scmi_response_status_value] 0 = 0x00 Success 1 = 0x01 Already Exists 2 = 0x02 Buffer Too Small 3 = 0x03 Id Already Assigned 4 = 0x04 Insufficient Data Storage Available 5 = 0x05 Internal Error 6 = 0x06 Invalid Storage System State Logical Disk 7 = 0x07 Invalid Class 8 = 0x08 Invalid Function 9 = 0x09 Invalid Logical Disk Block State 10 = 0x0A Invalid Loop Configuration 11 = 0x0B Invalid Parameter 12 = 0x0C Invalid Parameter Handle 13 = 0x0D Invalid Parameter Id 14 = 0x0E Invalid Quorum Configuration 15 = 0x0F Invalid Target Handle 16 = 0x10 Invalid Target Id 17 = 0x11 Invalid Time 18 = 0x12 Media Inaccessible 19 = 0x13 No Fibre Channel Port 20 = 0x14 No Image 21 = 0x15 No Permission 22 = 0x16 No Storage System 23 = 0x17 Not Loop Port 24 = 0x18 Not Participating 25 = 0x19 Object In Use 26 = 0x1A Parameter Object Does Not Exist 27 = 0x1B Target Object Does Not Exist 28 = 0x1C Timeout 29 = 0x1D Unknown Id 30 = 0x1E Unknown Parameter Handle 31 = 0x1F Unrecoverable Media Error 32 = 0x20 Invalid State 33 = 0x21 Transport Error 34 = 0x22 Volume Missing 35 = 0x23 Invalid Cursor 36 = 0x24 Invalid Target Logical Disk 37 = 0x25 No More Events 38 = 0x26 Lock Busy 39 = 0x27 Time Not Set 40 = 0x28 Not Supported Version 41 = 0x29 No Logical Disk For Storage System Virtual Disk 42 = 0x2A Logical Disk Presented 43 = 0x2B Denied On Slave 44 = 0x2C Not DRM Licensed 45 = 0x2D Not DRM Member 46 = 0x2E Invalid DRM Mode 47 = 0x2F Is Copying 48 = 0x30 Login Needed 49 = 0x31 Login Failed 50 = 0x32 Already Logged In 51 = 0x33 Storage System Connection Down 52 = 0x34 Group Empty 53 = 0x35 Incompatible Attribute 54 = 0x36 Is DRM Member 55 = 0x37 Is Log Unit 56 = 0x38 Not Online 57 = 0x39 Not Presented 58 = 0x3A Other Controller Failed 59 = 0x3B Maximum Objects 60 = 0x3C Maximum Size 61 = 0x3D Password Mismatch 62 = 0x3E Is Merging 63 = 0x3F Is Logging 64 = 0x40 Is Suspended 65 = 0x41 Bad Image Header 66 = 0x42 Bad Image 67 = 0x43 Image Too Large 68 = 0x44 EMU Not Available 69 = 0x45 EMU Indefinite Delay 70 = 0x46 Image Incompatible 71 = 0x47 Bad Image Segment 72 = 0x48 Image Already Loaded 73 = 0x49 Image Write Error 74 = 0x4A Logical Disk Sharing 75 = 0x4B Bad Image Size 76 = 0x4C Image Load Busy 77 = 0x4D Volume Failure Predicted 78 = 0x4E Invalid Object Condition 79 = 0x4F Invalid Pred Logical Disk Condition 80 = 0x50 Invalid Volume Usage 81 = 0x51 Minimum Volumes In Disk Group 82 = 0x52 Shutdown In Progress 83 = 0x53 Not Ready 84 = 0x54 Is Snapshot 85 = 0x55 Incompatible Mirror Policy 86 = 0x56 Inoperative 87 = 0x57 Disk Group Inoperative 88 = 0x58 Storage System Inoperative 89 = 0x59 Failsafe Locked 90 = 0x5A Data Flush Incomplete 91 = 0x5B Redundancy Mirrored Inoperative 92 = 0x5C Duplicate LUN 93 = 0x5D Other Remote Controller Failed 94 = 0x5E Unknown Remote Unit 95 = 0x5F Unknown Remote Group 96 = 0x60 PLDMC Failed 97 = 0x61 Storage System Management Interface Lock Failed 98 = 0x62 Remote SCS Error 99 = 0x63 Storage System Connection Up 100 = 0x64 Login Needed Pwd Changed 101 = 0x65 Maximum Logins 102 = 0x66 Invalid Cookie 103 = 0x67 Login Timedout 104 = 0x68 Maximum Snapshot Depth 105 = 0x69 Attribute Mismatch 106 = 0x6A Password Not Set 107 = 0x6B Not Host Port 108 = 0x6C Duplicate LUN WWID 109 = 0x6D System Inoperative 110 = 0x6E Snapclone Active 111 = 0x6F EMU Load Busy 112 = 0x70 Duplicate User Name 113 = 0x71 Drive Reserved For Code Load 114 = 0x72 Already Presented 115 = 0x73 Invalid Remote Storage System 116 = 0x74 No Storage System Management Interface Lock 117 = 0x75 Maximum Members 118 = 0x76 Maximum Destinations 119 = 0x77 Empty User Name 120 = 0x78 Storage System Exists 121 = 0x79 Already Open 122 = 0x7A Session Not Open 123 = 0x7B Not Marked Inoperative 124 = 0x7C Media Not Available 125 = 0x7D Battery System Failed 126 = 0x7E Member Is Cache Data Lost 127 = 0x7F Internal Lock Collision 128 = 0x80 OCP error 129 = 0x81 Mirror temporarily offline 130 = 0x82 Failsafe Mode enabled 131 = 0x83 Drive FW load abort due to Vraid0 Vdisk 132 = 0x84 FC Ports Unavailable 133 = 0x85 Only two remote relations are allowed 134 = 0x86 The requested SRC mode is not possible 135 = 0x87 Src group discarded, but dest group NOT discarded 136 = 0x88 Invalid DRM Group Tunnel specified 137 = 0x89 Specified DRM Log size is too small 138 = 0x8A Invalid DRM Log LDAD specified 139 = 0x8B DRM Group is already read-only 140 = 0x8C DRM Group is already active-active 141 = 0x8D DILX is already running 142 = 0x8E DILX is not running 143 = 0x8F invalid user defined log size 144 = 0x90 Invalid second handle parameter passed to scmi 145 = 0x91 DRM Group already Auto Suspended. 146 = 0x92 Specified option is not implemented yet 147 = 0x93 DRM Group is already present_only 148 = 0x94 The PU NOID is invalid 149 = 0x95 SCS Internal Error 150 = 0x96 Invalid SCS Function Code 151 = 0x97 Unsupported SCS Function Code 152 = 0x98 Init PS Failed 153 = 0x99 Target BAD NOID 154 = 0x9A PStore Is Volume 155 = 0x9B Bad Volume Usage 156 = 0x9C Bad LDAD_Usage 157 = 0x9D No LDAD Handle 158 = 0x9E Bad Quorum Flag 159 = 0x9F SCS U_T_TAG Invalid 160 = 0xA0 SCS U_T_TAG Bad UUID 161 = 0xA1 Too Many PS Tags 162 = 0xA2 Bad Routine 163 = 0xA3 No Tag for NOID 164 = 0xA4 Bad Loop Num 165 = 0xA5 Too Many Port WWNS 166 = 0xA6 Port WWN Not Found 167 = 0xA7 No DU For PU 168 = 0xA8 No SCCL For PU 169 = 0xA9 Unsupported 170 = 0xAA SCS Operation Failed 171 = 0xAB Has Members 172 = 0xAC Incompatible Preferred Mask 173 = 0xAD Too Few Vol Tag 174 = 0xAE ILF Debug Flag Not Set 175 = 0xAF Invalid POID 176 = 0xB0 Too Few Drives 177 = 0xB1 Too Few PS Tags 178 = 0xB2 Unexpected SCS Error 179 = 0xB3 Unsupported Capacity 180 = 0xB4 One or both controllers do not have the required 512MB of memory. 181 = 0xB5 Insuffcient drives of required type to create LDAD 182 = 0xB6 LDAD contains mixed drive types. 183 = 0xB7 Operation already in on state 184 = 0xB8 Operation already in off state 185 = 0xB9 CS$LD_GET_VDISK_INFO failed. 186 = 0xBA No Derived Unit For Storage System Virtual Disk 187 = 0xBB Invalid on mixed DRM configuration 188 = 0xBC Invalid Port number spefified 189 = 0xBD DRM group does not exist 190 = 0xBE Target Object is inoperative 191 = 0xBF A read16 command requested that is unknown. 192 = 0xC0 The controller requested is not A or B 193 = 0xC1 A get special page scsi cmd requested an unknown page. 194 = 0xC2 Cannot set failsafe because async enabled 195 = 0xC3 The Logical Disk is not an empty container/not a mirror clone 196 = 0xC4 The source LD and empty container are in different LDAD's 197 = 0xC5 This operation is not allowed on an empty container 198 = 0xC6 This operation is not allowed in AA mode 199 = 0xC7 The redundancy specified for snap is not allowed 200 = 0xC8 The redundancy in a snapshot tree must be the consistent 201 = 0xC9 No path was found to DR destination 202 = 0xCA Nonexistent group for operation 203 = 0xCB Invalid async log size 204 = 0xCC Generic async log size failure going to async 205 = 0xCD Is not in syncronous mode 206 = 0xCE An instant restore operation is in progress on this LD (or others in tree). 207 = 0xCF The logical disk is a mirror clone 208 = 0xD0 The mirror clone is resyncing 209 = 0xD1 The logical disk has a mirror clone. 210 = 0xD2 Unknown Remote Node 211 = 0xD3 Instant Restore mode incompatible. 212 = 0xD4 The DRM group is not suspended. 213 = 0xD5 The Logical Disks are not in the same snapshot tree 214 = 0xD6 The operation is not allowed on an original Logical Disk. 215 = 0xD7 Recontructing or reverting is in progress in LDAD. 216 = 0xD8 Not enough quorum disks for redundancy to do drive codeload. 217 = 0xD9 The requested operation has already been done. 218 = 0xDA A drive is in maintenance mode. 219 = 0xDB Invalid snapshots are being deleted. 220 = 0xDC Temp Sync Set 221 = 0xDD Maximum instant restores - wait for one to finish. 222 = 0xDE SCELL Not Locked 223 = 0xDF SCELL Lock Busy 224 = 0xE0 DRM Group already set to Defer Copy. 225 = 0xE1 Related operation in set of operations has failed 226 = 0xE2 A Log Shrink is currently in progress 227 = 0xE3 A Log Dealloc is currently in progress %[fcs_fail] 1 = Excessive exchange timeouts on loop 2 = Excessive link errors on loop 3 = Exhausted Link Down retries on loop with signal 4 = Exhausted Link Down retries on loop with loss of signal 5 = Excessive link inits on loop without completing device %[scsi_asc_ascq] 0x0000 = No additional sense information 0x0001 = No index/sector signal 0x0002 = No seek complete 0x0003 = Peripheral device write fault 0x0004 = Logical unit not ready, cause not reportable 0x0006 = No reference position found 0x0007 = Multiple peripheral devices selected 0x0008 = Logical unit communication failure 0x0009 = Track following error 0x000A = Error log overflow 0x000C = Write error 0x0010 = Id crc or ecc error 0x0011 = Unrecovered read error 0x0012 = Address mark not found for id field 0x0013 = Address mark not found for data field 0x0014 = Recorded entity not found 0x0015 = Random positioning error 0x0016 = Data synchronization mark error 0x0017 = Recovered data with no error correction applied 0x0018 = Recovered data with error correction applied 0x0019 = Defect list error 0x001A = Parameter list length error 0x001B = Synchronous data transfer error 0x001C = Defect list not found 0x001D = Miscompare during verify operation 0x001E = Recovered id with ecc correction 0x001F = Read Defect command allocated space overflow 0x0020 = Invalid command operation code 0x0021 = Logical block address out of range 0x0022 = Illegal function 0x0022 = Present Only Read Violation 0x0024 = Invalid field in cdb 0x0025 = Logical unit not supported 0x0026 = Invalid field in parameter list 0x0027 = Write protected 0x0028 = Not ready to ready transition, medium may have changed 0x0029 = Power on, reset, or bus device reset occurred 0x002A = Parameters changed 0x002B = Copy cannot execute since host cannot disconnect 0x002C = Command sequence error 0x002D = Overwrite error on update in place 0x002F = Commands cleared by another initiator 0x0030 = Incompatible medium installed 0x0031 = Medium format corrupted 0x0032 = No defect spare location available 0x0033 = Tape length error 0x0035 = Unspecified enclosure services failure 0x0036 = Ribbon, ink, or toner failure 0x0037 = Rounded parameter 0x0039 = Saving parameters not supported 0x003A = Medium not present 0x003B = Sequential positioning error 0x003D = Invalid bits in identify message 0x003E = Logical unit has not self-configured yet 0x003F = Target operating conditions have changed 0x0040 = Ram failure 0x0041 = Data path failure 0x0042 = Power-on or self-test failure 0x0043 = Message error 0x0044 = Internal target failure 0x0045 = Select or reselect failure 0x0046 = Unsuccessful soft reset 0x0047 = SCSI parity error 0x0048 = Initiator detected error message received 0x0049 = Invalid message error 0x004A = Command phase error 0x004B = Data phase error 0x004C = Logical unit failed self-configuration 0x004E = Overlapped commands attempted 0x0050 = Write append error 0x0051 = Erase failure 0x0052 = Cartridge fault 0x0053 = Media load or eject failed 0x0054 = SCSI to host system interface failure 0x0055 = System resource failure 0x0057 = Unable to recover table-of-contents 0x0058 = Generation does not exist 0x0059 = Updated block read 0x005A = Operator request or state change input 0x005B = Log exception 0x005C = Rpl status change 0x005D = Failure prediction threshold exceeded 0x0060 = Lamp failure 0x0061 = Video acquisition error 0x0062 = Scan head positioning error 0x0063 = End of user area encountered on this track 0x0064 = Illegal mode for this track 0x0065 = Voltage fault 0x0080 = Vendor specific. 0x0081 = Reassign power fail recovery failed 0x0100 = Filemark detected 0x0103 = No write current 0x0104 = Logical unit is in process of becoming ready 0x0108 = Logical unit communication time-out 0x0109 = Tracking servo failure 0x010B = Temperature exceeded 0x010C = Recovered data - data auto-reallocated 0x0111 = Read retries exhausted 0x0114 = Record not found 0x0115 = Mechanical positioning error 0x0117 = Recovered data with retries 0x0118 = Recovered data with error correction & retries applied 0x0119 = Defect list not available 0x011C = Primary defect list not found 0x0121 = Invalid element address 0x0126 = Parameter not supported 0x0128 = Import or export element accessed 0x0129 = Power on occurred 0x012A = Mode parameters changed 0x012C = Too many windows specified 0x0130 = Cannot read medium - unknown format 0x0131 = Format command failed 0x0132 = Defect list update failure 0x0135 = Unsupported enclosure function 0x013B = Tape position error at beginning-of-medium 0x013F = Microcode has been changed 0x0140 = DRAM parity error 0x0150 = Write append position error 0x0153 = Unload tape failure 0x0155 = XOR cache not available 0x015A = Operator medium removal request 0x015B = Threshold condition met 0x015C = Spindles synchronized 0x0161 = Unable to acquire video 0x0200 = End-of-partition/medium detected 0x0203 = Excessive write errors 0x0204 = Logical unit not ready, initializing command required 0x0208 = Logical unit communication parity error 0x0209 = Focus servo failure 0x020C = Write error - auto reallocation failed 0x0211 = Error too long to correct 0x0214 = Filemark or setmark not found 0x0215 = Positioning error detected by read of medium 0x0217 = Recovered data with positive head offset 0x0218 = Recovered data - data auto-reallocated 0x0219 = Defect list error in primary list 0x021C = Grown defect list not found 0x0226 = Parameter value invalid 0x0229 = SCSI bus reset occurred 0x022A = Log parameters changed 0x022C = Invalid combination of windows specified 0x0230 = Cannot read medium - incompatible format 0x0235 = Enclosure services unavailable 0x023B = Tape position error at end-of-medium 0x023F = Changed operating definition 0x0240 = DRAM parity error 0x0250 = Position error related to timing 0x0253 = Medium removal prevented 0x025A = Operator selected write protect 0x025B = Log counter at maximum 0x025C = Spindles not synchronized 0x0261 = Out of focus 0x0300 = Setmark detected 0x0304 = Logical unit not ready, manual intervention required 0x0309 = Spindle servo failure 0x030C = Write error - recommend reassignment 0x030E = Invalid Field in Command Information Unit 0x0311 = Multiple read errors 0x0314 = End-of-data not found 0x0315 = End of user area encountered on this track 0x0317 = Recovered data with negative head offset 0x0318 = Recovered data with circ 0x0319 = Defect list error in grown list 0x0326 = Threshold parameters not supported 0x0329 = Bus device reset occurred 0x032A = Reservations Preempted 0x0330 = Cleaning cartridge installed 0x0335 = Enclosure transfer failure 0x033B = Tape or electronic vertical forms unit not ready 0x033F = Inquiry data has changed 0x035A = Operator selected write permit 0x035B = Log list codes exhausted 0x0400 = Beginning-of-partition/medium detected 0x0404 = Logical unit not ready, format in progress 0x0409 = Head Select Fault 0x0411 = Unrecovered read error - auto reallocate failed 0x0414 = Block sequence error 0x0417 = Recovered data with retries and/or circ applied 0x0418 = Recovered data with lec 0x0426 = Invalid release of persistent reservation 0x0429 = Internal reset 0x042A = Reservations Released 0x0435 = Enclosure transfer refused 0x043B = Slew failure 0x045D = exceeded -- disk reassign DST table 0x0500 = End-of-data detected 0x0511 = L-ec uncorrectable error 0x0517 = Recovered data using previous sector id 0x0518 = Recovered data - recommend reassignment 0x052A = Registrations preempted 0x053B = Paper jam 0x053F = Device identifier changed 0x053f = Device identifier has changed 0x055D = exceeded -- disk reassign AST table 0x0600 = I/O process terminated 0x0611 = Circ unrecovered error 0x0617 = Recovered data without ecc - data auto-reallocated 0x0618 = Recovered data - recommend rewrite 0x062A = Asymmetric access state changed 0x063B = Failed to sense top-of-form 0x065D = exceeded -- disk reassign DDT table 0x0711 = Data resynchronization error 0x0717 = Recovered data without ecc - recommend reassignment 0x0718 = Recovered data - data rewritten 0x072A = Asymmetric access state transition failed 0x073B = Failed to sense bottom-of-form 0x0811 = Incomplete block read 0x0817 = Recovered data without ecc - recommend rewrite 0x083B = Reposition error 0x0911 = No gap found 0x092A = Capacity data changed 0x093B = Read past end of medium 0x0A11 = Miscorrected error 0x0A3B = Read past beginning of medium 0x0B11 = Unrecovered read error - recommend reassignment 0x0B3B = Position past end of medium 0x0C11 = Unrecovered read error - recommend rewrite the data 0x0C3B = Position past beginning of medium 0x0D3B = Medium destination element full 0x0E19 = Defect list error -- fewer than 50% defect list copies 0x0E3B = Medium source element empty 0x0E3F = Reported LUNs data has changed 0x1100 = Audio play operation in progress 0x1200 = Audio play operation paused 0x1300 = Audio play operation successfully completed 0x1400 = Audio play operation stopped due to error 0x1500 = No current audio status to return 0x315D = Failure prediction threshold exceeded -- head failure 0x325D = Failure prediction threshold exceeded -- recovered data error rate 0x375D = Failure prediction threshold exceeded -- recovered TA 0x385D = Failure prediction threshold exceeded -- hard TA event 0x415D = Failure prediction threshold exceeded -- SSE DPF smoothing 0x435D = Failure prediction threshold exceeded -- seek DPF smoothing 0x455D = Failure prediction threshold exceeded -- track following errors 0x5B5D = Failure prediction threshold exceeded -- spinup DFP smoothing 0x803F = Read after write buffer contents changed 0x8047 = Fibre Channel Sequence Error -- frame not received by E_D_TOV 0x8080 = FC FIFO error during read transfer 0x8180 = FC FIFO error during write transfer 0x8280 = DISC FIFO error during read transfer 0x8380 = DISC FIFO error during write transfer 0x8480 = LBA seeded LRC error on read 0x8580 = LBA seeded LRC error on write 0x8603 = Write error - recommend reassignment 0x8680 = IOEDC error on read 0x8780 = IOEDC error on write 0x903F = Invalid CAP block -- servo Flash SAP HDA serial number does not match the ETF SAP HDA serial number 0x9131 = Format corrupted World Wide Name invalid 0x913F = World Wide Name mismatch 0x9726 = Invalid field parameter -- TMS firmware tag 0x9826 = Invalid field parameter -- check sum 0x9926 = Invalid field parameter -- firmware tag 0xEE5D = Failure prediction threshold exceeded -- no control table on disk 0xFF5D = False failure prediction threshold exceeded %[scsi_sensekey] 0x0 = NO SENSE 0x1 = RECOVERED ERROR 0x2 = NOT READY 0x3 = MEDIUM ERROR 0x4 = HARDWARE ERROR 0x5 = ILLEGAL REQUEST 0x6 = UNIT ATTENTION 0x7 = DATA PROTECT 0x8 = BLANK CHECK 0x9 = Vendor Specific 0xA = COPY ABORTED 0xB = ABORTED COMMAND 0xC = EQUAL 0xD = VOLUME OVERFLOW 0xE = MISCOMPARE 0xF = RESERVED %[scsi_cmds] 0x00 = TEST UNIT READY 0x01 = REZERO UNIT 0x03 = REQUEST SENSE 0x04 = FORMAT UNIT 0x07 = REASSIGN BLOCKS 0x08 = READ (6 byte) 0x0A = WRITE (6 byte) 0x0B = SEEK (6 byte) 0x12 = INQUIRY 0x14 = RECOVER BUFFERED DATA 0x15 = MODE SELECT (6 byte) 0x16 = RESERVE UNIT 0x17 = RELEASE UNIT 0x18 = COPY 0x1A = MODE SENSE (6 byte) 0x1B = START STOP UNIT 0x1C = RECEIVE DIAGNOSTIC RESULTS 0x1D = SEND DIAGNOSTIC 0x1E = PREVENT-ALLOW MEDIUM REMOVAL 0x25 = READ CAPACITY 0x28 = READ (10 byte) 0x2A = WRITE (10 byte) 0x2B = SEEK (10 byte) 0x2E = WRITE AND VERIFY (10 byte) 0x2F = VERIFY (10 byte) 0x30 = SEARCH DATA HIGH (10 byte) 0x31 = SEARCH DATA EQUAL (10 byte) 0x32 = SEARCH DATA LOW (10 byte) 0x33 = SET LIMITS (10 byte) 0x34 = PRE-FETCH 0x35 = SYNCHRONIZE CACHE 0x36 = LOCK-UNLOCK CACHE 0x37 = READ DEFECT DATA (10 byte) 0x38 = MEDIUM SCAN 0x39 = COMPARE 0x3A = COPY AND VERIFY 0x3B = WRITE BUFFER 0x3C = READ BUFFER 0x3E = READ LONG 0x3F = WRITE LONG 0x40 = CHANGE DEFINITION 0x41 = WRITE SAME 0x4C = LOG SELECT 0x4D = LOG SENSE 0x50 = XDWRITE (10 bytes) 0x51 = XPWRITE (10 bytes) 0x52 = XDREAD (10 bytes) 0x55 = MODE SELECT (10 byte) 0x56 = SCSI-3 SPC p.70 0x57 = SCSI-3 SPC p.88 0x5A = MODE SENSE (10 byte) 0x5E = PERSISTENT RESERVE IN 0x5F = PERSISTENT RESERVE OUT 0x81 = REBUILD 0x82 = REGENERATE 0x88 = READ (16 byte) 0x8A = WRITE (16 byte) 0x9E = READ CAPACITY (Jumbo Version) 0xA0 = REPORT LUNS 0xA8 = READ (12 byte) 0xAA = WRITE (12 byte) 0xAE = WRITE AND VERIFY (12 byte) 0xAF = VERIFY (12 byte) 0xB0 = SEARCH DATA HIGH (12 byte) 0xB1 = SEARCH DATA EQUAL (12 byte) 0xB2 = SEARCH DATA LOW (12 byte) 0xB3 = SET LIMITS (12 byte) 0xEB = WRITE ID 0xEC = REPORT ID %[els_codes] 0x01 = Link service reject 0x02 = Accept 0x03 = N_Port login 0x04 = F_port login 0x05 = Logout 0x06 = Abort exchange 0x07 = Read connection status 0x08 = Read exchange status block 0x09 = Read sequence status block 0x0A = Read sequence initiative 0x0B = Establish streaming 0x0C = Estimate credit 0x0D = Advise credit 0x0E = Read timeout value 0x0F = Read link status 0x10 = Echo 0x11 = Test 0x12 = Reinstate recovery qualifier 0x13 = Read Exchange Concise 0x20 = Process login 0x21 = Process logout 0x22 = State change notification 0x23 = Test process login state 0x24 = Third party process logout 0x25 = Login Control List Management 0x30 = Get alias id 0x31 = Fabric activate alias id 0x32 = Fabric deactivate alias id 0x33 = N_Port activate alias id 0x34 = N_Port deactivate alias id 0x40 = Quality of service request 0x41 = Read virtual circuit status 0x50 = Discover N_Port service parms 0x51 = Discover F_Port service parms 0x52 = Discover address 0x53 = Report Node Capabilites 0x56 = Read Port Status Block 0x57 = Read Port List 0x58 = Bandwidth Allocation 0x59 = Bandwidth DeAllocation 0x60 = Fabric Address Notification 0x61 = Registered State Change Notification 0x62 = State Change Registration 0x63 = Report Node FC-4 Types 0x68 = Clock Sync Request 0x69 = Clock Sync Update 0x70 = Loop Initialize 0x71 = Loop Port Control 0x72 = Loop Status 0x77 = Request Topology Information 0x78 = Request Node Identification Information 0x79 = Registered Link Incident Record 0x7A = Link Incident Record Registration 0xF0 = Vendor Unique - SCS message %[fm_terminate_routines] 0 = FM_TERMINATE_START 1 = FM_TERMINATE_PREP1 2 = FM_TERMINATE_LOAD_LTE_GLUE_REGS 3 = FM_TERMINATE_PREP2 4 = FM_TERMINATE_LOAD_LTE_INFO 5 = FM_TERMINATE_LOAD_LTE_POLMEMCTRLR_REGS 6 = FM_TERMINATE_LOAD_LTE_CACMEMCTRLR_REGS 7 = FM_TERMINATE_LOAD_LTE_TACHYON0_REGS 8 = FM_TERMINATE_LOAD_LTE_TACHYON1_REGS 9 = FM_TERMINATE_LOAD_LTE_TACHYON2_REGS 10 = FM_TERMINATE_LOAD_LTE_TACHYON3_REGS 11 = FM_TERMINATE_LOAD_LTE_TACHYON4_REGS 12 = FM_TERMINATE_LOAD_LTE_TACHYON5_REGS 13 = FM_TERMINATE_LOAD_LTE_TACHYON6_REGS 14 = FM_TERMINATE_LOAD_LTE_TACHYON7_REGS 15 = FM_TERMINATE_LOAD_LTE_TACHYON8_REGS 16 = FM_TERMINATE_LOAD_LTE_TACHYON9_REGS 17 = FM_TERMINATE_LOAD_LTE_TOY_REGS 18 = FM_TERMINATE_LOAD_LTE_UART1_REGS 19 = FM_TERMINATE_LOAD_LTE_UART2_REGS 20 = FM_TERMINATE_LOAD_LTE_UART3_REGS 21 = FM_TERMINATE_LOAD_LTE_UART4_REGS 22 = FM_TERMINATE_DECODER_REGS 23 = FM_TERMINATE_EXPANSION6 24 = FM_TERMINATE_EXPANSION7 25 = FM_TERMINATE_EXPANSION8 26 = FM_TERMINATE_CBIC_TALK_OFF 27 = FM_TERMINATE_DECODE_MACHINE_CHECK 28 = FM_TERMINATE_PRESERVE_EVENTS 29 = FM_TERMINATE_SEND_LAST_GASP 30 = FM_TERMINATE_CRASH_DUMP_PREP 31 = FM_TERMINATE_CRASH_DUMP 32 = FM_TERMINATE_COMPUTE_LTE_EDC 33 = FM_TERMINATE_RESTART_INIT 34 = FM_TERMINATE_RESTART_ACTION 35 = FM_TERMINATE_END %[fm_ue] 0 = Unrecognized Unexpected Event code 1 = Power failure before initialization could complete 2 = Recursive termination before initialization could complete 3 = Terminated during the first part post-termination preparation 4 = Terminated during the load of the G3 Glue registers 5 = Terminated during the second part post-termination preparation 6 = Terminated during event report block load 7 = Terminated during initialization of all hardware components and software data structures in preparation for restart 8 = Terminated during execution of an unrecognized post-termination operation (premature) 9 = Power failure during execution of a post-termination operation 10 = No good entries found in Termination Event Array. (Note that this condition is expected following the first boot of a newly manufactured HSV200 controller. In that case this event can be safely ignored; no action is necessary.) 11 = The edc of one or more Last Termination Event Array entries is bad 12 = Last Termination Event Array entry control block revision is different 13 = Last Termination Event Array entry information block revision is different 14 = Last Termination Event Array entry up time value is greater than the system's up time value 15 = Last Termination Event Array entry up time value is less than the previous entry's up time value 16 = Last Termination Event Array entry sequence number value is less than the previous entry's sequence number value 17 = Detected an unrecognized dump/restart control code 18 = Failed to terminate the entity dump loop 19 = Unexpected dump entity size 20 = Unexpected elp processing stage code 21 = Number of Termination Parameters supplied not equal to maximum allowed as required 22 = Detected an unexpected address map companion block control code 23 = Original TP[0] value replaced by DIMM size load 24 = Unexpected meal commit stage code %[fm_mpvfc] 0 = Success 1 = Cookie value is not as expected 2 = Event data overflows the buffer 3 = Event data size is not a multiple of 4 bytes, is less than the minimum, or is greater than the maximum 4 = Event Information Packet type is greater than the maximum 5 = Event information size is not a multiple of 4 bytes, is less than the minimum, is greater than the maximum, doesn't match the eip type size, or when combined with the entry header size doesn't equal the entry size 6 = Event code is zero 7 = Event is out of sequence (0) 8 = Dead space area at the end of a partially packed buffer contains a nonzero value 9 = An event data block containing a nonzero value was found after end of event data was detected 10 = Sequence number reset flag not set as expected 11 = The event log contains no entries 12 = Event data block read failed during maintenance verification 13 = Event data block read failed during maintenance completion 14 = Event data block erase failed during maintenance completion 15 = Control block read failed during maintenance verification 16 = Control block write failed during maintenance verification 17 = Event data block write failed during maintenance update 18 = Control block write failed during maintenance completion 19 = Storage System Termination Event Log related send was unsuccessful or the master found that the Storage System Termination Event Log is inaccessible 20 = Control block read failed during maintenance verification by the other HSV200 controller 21 = Control block read failed during update retrieval 22 = Event data block read failed during retrieval request 23 = Log has been prepared for re-initialization 24 = Event is out of sequence (1) 25 = Event is out of sequence (2) 26 = Event is out of sequence (3) %[fm_quiesce] 0 = Make FM quiescent on both controllers 1 = Make FM quiescent on slave controller only %[rcse] 0 = Requested by Storage System Management Interface use image 1 = Requested by CTRL_F 2 = Requested by Storage System Management Interface, shutdown 3 = Emergency drive firmware upgrade 4 = Emergency drive firmware upgrade done 5 = Attempt to check new device for System WWN 6 = Existing cell lost quorum 7 = Quorum disks have changed in existing cell 8 = An active cell has lost its quorum 9 = WWN has been found on new quorum 10 = ID has changed on a physical store 11 = System has been scrubbed 12 = Logged in port for ILF cannot be found 13 = The ILF disk is no longer logged in 14 = The ILF id block failed to write 15 = Scrub requested from OCP 16 = The system Disk Group changed 17 = An attempt to realize a logical disk failed 18 = The master crashed during a resync recovery window 19 = The master crashed during a resync window with no cell 20 = The slave failed before returning status of an unshare 21 = An operation to get a cmap failed 22 = A CVMDB access failed 23 = A cache metadata i/o failed 24 = An initiate logical disk expand failed 25 = An attempt to take a logical disk online failed 26 = A flush unit operation failed on the slave 27 = Recovery to handle too much frozen data 28 = An attempt to take a logical disk offline failed 29 = An attempt to unrealize a logical disk failed 30 = An attempt to update the RSSM on media failed 31 = Container Services failed to initiate a merge operation 32 = A new WWN was entered on the OCP 33 = Deadlock avoidance for drive code load 34 = A drive appeared while the system was inoperative 35 = A drive has failed a BBR check 36 = A drive has appeared which may fix a multi disk failure 37 = A failure was detected during hierarchy lookup 38 = A virtual disk could not be presented 39 = Quorum disk could not be found after a failover 40 = An attempt to realize the csld failed 41 = A storage cell went undetected during realization 42 = Quorum was lost during cell realization 43 = A drive disappeared during cell realization 44 = Cell realization failed but device discovery will not complete 45 = An attempt to realize the scscb failed 46 = A snapshot or snapclone tree was split across the master and slave 47 = A reduced quorum set was reconstructed 48 = A migration operation initiation failed 49 = An attempt to delete a logical disk failed 50 = An attempt to take a logical disk offline other failed 51 = An attempt to synch the mirror for a logical disk failed 52 = Container Services failed to initiate a split operation 53 = A virtual disk could not be unpresented 54 = An attempt to take a unit operative failed 55 = Debug flags are being committed 56 = Requested by the OCP 57 = DRM went offline 58 = DRM went offline with writes in progress 59 = A memory allocation failed 60 = A loop initiator disruptor drive was bypassed 61 = ID blocks on a drive were erased 62 = An attempt to realize the PLDMC failed 63 = A logical disk in an inoperative Disk Group was expected to be inoperative but was not 64 = An unshare operation failed 65 = An rss member failed during cell realization 66 = A Disk Group has become RAID 1 inoperative 67 = Requested by maintenance or SCS debug command 68 = A confirmation was refused on the OCP 69 = A confirmation was approved on the OCP 70 = An attempt to unmirror a logical disk failed 71 = An attempt to quiesce a unit failed 72 = Container Services failed to add a Disk Group 73 = Container Services failed to delete a Disk Group 74 = Print flags have changed 75 = Debug flags have changed 76 = The master failed while trying to get information from it 77 = An attempt to erase quorum failed 78 = An attempt to copy psars failed 79 = Container Services failed to initiate a marry operation 80 = An attempt to update or init rss meta failed so an attempt was made to fault a drive 81 = A system inoperative controller was activated by the master indicating that inoperative condition was fixed 82 = A drive has unexpectedly changed its worldwide name 83 = A drive has unexpectedly changed its worldwide name 84 = PRLI handler detected other controller reboot 85 = host port topology change detected 86 = Slave failed during staggered code load, so reboot now 87 = The configuration changed while the system was inoperative 88 = I/O commited, log inop so no place to put it, so reboot now 89 = About to write an ID block, but drive pointer changed 90 = Enter safe mode 91 = The slave failed before returning status of a mirrorclone resync 92 = Starting a mirror clone resync failed 93 = Couldn't clear the ldrm to finish fracture 94 = Starting a mirror clone fracture failed 95 = The slave failed before returning status of an instant restore 96 = Completing a LD restore failed 97 = Couldn't clear the ldrm to finish detach 98 = Starting a mirror clone detach failed 99 = Scrub requested from SCMI 100 = Scrub requested from CONSOLE 101 = Starting a lun shrink failed 256 = Active/Active write collision 257 = Trying to close tunnel with outstanding qsce operation %[drv_inop] 0x0 = Unknown 0x001 = Container Services I/O failure 0x002 = Scrubber I/O failure 0x003 = Attempt to set CBIT on normal drive 0x004 = Attempt to set CBIT on merging drive 0x100 = Target Discovery Service Descriptor retry count exceeded 0x101 = Inoperable for Bad Block Replacement 0x102 = Soft error count exceeded 0x103 = Exchange timeout count exceeded 0x104 = Drive communication failure count exceeded 0x105 = Command retries exceeded 0x106 = Medium/Hardware Errors encountered on this physical disk drive 0x107 = Directed LIP threshold exceeded 0x108 = Transport error count threshold exceeded 0x109 = The user intentionally added this drive to the DSL 0x200 = Smart event from a physical disk drive not in Storage System 0x201 = Smart event from a physical disk drive not a Volume 0x202 = Smart event from a physical disk drive not a Redundant Storage Set 0x203 = Failure predicted from physical disk drive 0x204 = Cannot read from physical disk drive from the poll 0x205 = Failure predicted from physical disk drive while deleting Disk Group 0x206 = physical disk drive forced inoperative from maintenence command for temporary POID 0x207 = physical disk drive forced inoperative from maintenence command for POID 0x208 = Bad block recovery failed or cannot read FPAB 0x209 = Failure to remove volume from Storage System 0x20a = Failure to update metadata 0x20b = Failure to update metadata - physical disk drive is missing - will NOT be marked inoperable 0x210 = About to write ID block 0 to wrong physical disk drive 0x211 = About to write ID blocks to wrong physical disk drive 0x212 = About to write ID block 2 to wrong physical disk drive 0x213 = About to write ID blocks after retry to wrong physical disk drive %[fcs_mtl] 1 = The physical disk drive left itself bypassed 2 = The Drive Enclosure Environmental Monitoring Unit bypassed the drive bay %[cac_mnemonic] 0x00 = CAC_NO_ACTION 0x01 = CAC_NOTIFY_FUSION_DEV 0x02 = CAC_NOTIFY_OPSYS 0x03 = CAC_SEE_TC 0x04 = CAC_TC_RECURSED 0x05 = CAC_SEE_OTC 0x06 = CAC_SEE_ASSOC_TEVENT 0x07 = CAC_ADVISEW_FUSION_DEV 0x08 = CAC_ADVISEI_FUSION_DEV 0x09 = CAC_DETERMINE_PFC 0x0a = CAC_LOW_MEM_ACC_ADVICE 0x0b = CAC_GLUE_POWEROFF 0x20 = CAC_REPLACE_CB 0x22 = CAC_REPLACE_BATTA 0x23 = CAC_REPLACE_BATTB 0x24 = CAC_REPLACE_BLOWERA 0x25 = CAC_REPLACE_BLOWERB 0x26 = CAC_REPLACE_BLOWERPSA 0x27 = CAC_REPLACE_BLOWERPSB 0x28 = CAC_REP_REMOVED_BATTA 0x29 = CAC_REP_REMOVED_BATTB 0x2a = CAC_REP_REMOVED_BLWRA 0x2b = CAC_REP_REMOVED_BLWRB 0x2c = CAC_REP_REMOVED_BLWRPSA 0x2d = CAC_REP_REMOVED_BLWRPSB 0x2e = CAC_REDUCE_AMBIENT 0x2f = CAC_CHECK_BATTS 0x30 = CAC_GBIC_CHECK_FAILURE 0x36 = CAC_OVER_TEMP 0x37 = CAC_TEMP_UNDETERMINED 0x38 = CAC_REPLACE_BATTCAUTION 0x39 = CAC_RECUR_REPLACE_CB 0x3a = CAC_GBIC_NOT_PRESENT 0x3b = CAC_SRAM_TEST_ERROR 0x40 = CAC_REPLACE_DRIVE 0x41 = CAC_REP_REMOVED_DRIVE 0x42 = CAC_REMOVE_REPLACE_DRIVE 0x43 = CAC_MOVE_DRIVE 0x44 = CAC_PORT_FAILURE 0x46 = CAC_REPLACE_DRIVE_PORT 0x47 = CAC_FRAME_TIMEOUT 0x48 = CAC_UNEXPECTED_WORK 0x49 = CAC_BAD_ALPA 0x4a = CAC_LINK_FAILURE 0x4c = CAC_SPOF_DRIVE 0x4d = CAC_UPDATE_DRIVE_FW 0x4e = CAC_SPOF_SHELF 0x4f = CAC_REMOVE_DRIVE 0x50 = CAC_DELSCLD 0x51 = CAC_EVAL_LD 0x52 = CAC_IRDEL_LD 0x5f = CAC_CHECK_CONN 0x60 = CAC_CHECK_SRC_UNIT 0x61 = CAC_CHECK_DEST_UNIT 0x62 = CAC_CHECK_LOG 0x63 = CAC_CHECK_SITE_VERSIONS 0x64 = CAC_DRM_CHECK_REM_BACKEND 0x65 = CAC_DRM_RESTART_REM 0x66 = CAC_DRM_RESTART_LOCAL 0x67 = CAC_DRM_CHECK_ISL 0x68 = CAC_DRM_CHECK_RMTNODES 0x69 = CAC_DRM_CHECK_ISL_SWITCH 0x80 = CAC_REMOVE_REPLACE_DEPS 0x81 = CAC_REPLACE_DEPS 0x82 = CAC_REMOVE_REPLACE_DEBLWR 0x83 = CAC_REPLACE_DEBLWR 0x84 = CAC_REPLACE_DEBLWR_IMM 0x85 = CAC_DE_CTRLR_SHUTDN 0x86 = CAC_CORRECT_TEMP 0x87 = CAC_CORRECT_TEMP_IMM 0x88 = CAC_RESET_DEEMU 0x89 = CAC_REPLACE_DEEMU 0x8a = CAC_AUTOREC_DEEMU 0x8b = CAC_RECOVER_DEEMU_COMBO 0x8c = CAC_AUTOREC_COMBO_DEEMU 0x8d = CAC_DE_INITIALIZE 0x8e = CAC_DE_JB_TROUBLE 0x8f = CAC_DEMU_DISCOPS 0x90 = CAC_DE_CHECK_XCVR 0x91 = CAC_REPLACE_DE 0x92 = CAC_AUTOREC_DE 0x93 = CAC_REPLACE_DEIOM 0x94 = CAC_AUTOREC_DEIOM 0x95 = CAC_RESET_DEIOM 0x96 = CAC_UPLOAD_DEEMU_NEW_CODE 0x97 = CAC_CABINET_BUS_CABLE 0x98 = CAC_REDUCE_DE 0x99 = CAC_CHECK_DEIOM_CABLE 0x9a = CAC_CHECK_RACK_PDU 0x9b = CAC_MONITOR_DEEMU 0x9c = CAC_CYCLE_DRIVE_EMU 0xb4 = CAC_CHANGE_OCCUPANCY 0xb5 = CAC_CHANGE_LDAD_CONFIG 0xb6 = CAC_RESTORE_SPOFRC 0xb9 = CAC_EVAL_OTHER_NSC 0xba = CAC_EVAL_PWR_OTHER_NSC 0xbf = CAC_EVAL_VOL 0xc3 = CAC_EVAL_PORT 0xc4 = CAC_NEW_DRIVE_FW 0xc5 = CAC_CAB_BUS_CABLE 0xc8 = CAC_REPLACE_BATT0 0xc9 = CAC_REPLACE_BATT1 0xca = CAC_REPLACE_BATT2 0xcb = CAC_REPLACE_BATT3 0xcc = CAC_REP_REMOVED_BATT0 0xcd = CAC_REP_REMOVED_BATT1 0xce = CAC_REP_REMOVED_BATT2 0xcf = CAC_REP_REMOVED_BATT3 0xd0 = CAC_CHECK_BATTS_XL 0xd1 = CAC_REPLACE_BATTCAUTION_XL 0xd2 = CAC_REPLACE_BLOWER0 0xd3 = CAC_REPLACE_BLOWER1 0xd4 = CAC_REP_REMOVED_BLWR0 0xd5 = CAC_REP_REMOVED_BLWR1 0xd6 = CAC_CHECK_REPLACE_PS0 0xd7 = CAC_CHECK_REPLACE_PS1 0xd8 = CAC_REP_REMOVED_PS0 0xd9 = CAC_REP_REMOVED_PS1 0xda = CAC_CHECK_BATT_COMM 0xdb = CAC_MISMATCH_CODE %[storage_usage] 0 = Unallocated 1 = Quorum Space 2 = CSLD Logical Data 3 = Primary Logical Disk 4 = Primary LD Metadata 5 = LD Base RSD (LDDIR) 6 = Physical Metadata 7 = DRM LOG OD storage 8 = Supported USAGE Types %[exec_tod] 1 = TOY clock unavailable, this controller's time reset to default 2 = TOY clock time is less than previously stored time, this controller's time reset to default 3 = Bad EDC for previously stored time, this controller's time reset to default 4 = TOY clock not running, this controller's time reset to default 5 = TOY clock is accurate, this controller's time set to TOY clock time value 6 = This controller's time was set from policy memory metadata following a controller resynchronization operation 7 = This controller's time was set to the current time value 8 = Following Storage System time synchronization the primary controller requested that the secondary controller set its TOY clock to the current time value 9 = The secondary controller set its TOY clock to the current time value as requested by the primary controller 10 = This controller's TOY clock was set to the current time value STRUCTURE REVISION LEVELS: eip01: 3. eip02: 3. eip03: 5. eip04: 6. eip05: 4. eip07: 1. eip08: 3. eip09: 5. eip0A: 2. eip0B: 4. eip0C: 4. eip0D: 1. eip0E: 3. eip0F: 2. eip10: 0. eip11: 3. eip12: 2. eip13: 5. eip14: 2. eip15: 0. eip16: 0. eip17: 1. eip18: 0. eip19: 0. eip1A: 0. eip1B: 1. eip1C: 1. eip1D: 0. eip1E: 1. eip1F: 0. eip20: 0. eip21: 0. elp_event: 2. lte_control_block: 1. lte_info_block: 255. MAPPING INFORMATION: 00030000 00000010 d7f3a73172fc3ce78154bbd9 00030010 00000028 d7f3a73172f436ea8a58b9 00030038 0000005c d7f3a73172e737e39a5dadd7449f 00030094 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0003009c 00000018 e0ce911d58c711cb8a6687e67eba75b4f0583c1d85 000300b4 00000030 e0ce911d58c711cb8a6687e67eba75b4 000300e4 0000015c f6cdbd114cc506dba76eb7e078bd6eb5db5026 00030240 0000002c d6edbd025fda11cba678 0003026c 00000178 d6edb22d58c516cfa16eb7cc458345b2da5f3c119d7ddce96c5f 000303e4 000000ac f6cd922d44db1bda8a7b8dfa719169b2ce4521 00030490 000001a0 d6edbd1b43dc06 00030630 00000fdc f6cd922d4cd611dbb87e84e963ab45b6ca43342b8256d9fc6b 0003160c 00000068 f6cd922d4ed917cfa7549eec7ebd7199dc45330082 00031674 000001d0 f6cdbd1142d91ecbb67f 00031844 00000084 d6edbd144cde17f1b6799a 000318c8 00001370 f6cd922d4ed41ecd8a6887e575a774a3cb6e21009056cb 00032c38 0000011c d6edbd0159d406c7a67f81eb64 00032d54 00000144 f6cdbd0848c71df1b66484e472ad6e 00032e98 00000218 f6cdbd1142d91ecbb67f87fa 000330b0 00000100 f6cd922d5ec01ff1b6679ad763bc7fa3f04520159f51e7eb764a54 000331b0 0000012c f6cd922d5ec01ff1b6679ad770bc6a99db43331a827ddbe66c4d 000332dc 000000dc f6cd922d48c313c28a7f9ae979bd45a5c14521 000333b8 000000a4 f6cd922d58c516cfa16eb7fc65af74b5c6453b1b9f7ddbe76d505371 0003345c 000000a4 f6cdbd115fc42dcfb660 00033500 00000138 f6cdbd115fc42dcca06284ec 00033638 00000068 f6cdbd115fc72dcfb660 000336a0 00000138 f6cdbd115fc72dcca06284ec 000337d8 000000f4 f6cdbd075ec62dcfb660 000338cc 00000160 f6cdbd075ec62dcca06284ec 00033a2c 000000f4 f6cdbd045ec62dcfb660 00033b20 000010a0 f6cdbd1f44c611f1b86d8bd767bc75a5ca4221 00034bc0 00000110 f6cdbd045ec62dcca06284ec 00034cd0 00000068 d6edbd005aea16dab1 00034d38 0000003c d6edbd005aea14cbb1 00034d74 0000003c d6edbd005aea1edcb7 00034db0 0000003c d6edbd005aea1fddb267 00034dec 0000005c d6edbd005aea00cbb8649eed 00034e48 0000003c d6edbd005aea01ddb267 00034e84 0000003c d6edbd005aea0aca 00034ec0 0000003c d6edbd005aea1cd8b7 00034efc 0000003c d6edbd005aea01c0b47bb7eb78be63 00034f38 00000068 d6edbd0058db2ddea7648bed64bd45a8c046 00034ff8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00035000 00000924 f6cdbd005aea11c6b06883 00035924 00000178 f6cd92 00035a9c 00000068 f6cd922d5fc01cf1a57987eb72bd6999c15e25 00035b04 000000a0 d6edb22d5dda01da8a7c87fa7c 00035ba4 0000002c d6edb22d5cc017f1a6729bd776ad6eafd958260dae41d9f86c4b5567 00035bd0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00035bd8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00035be0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00038578 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00038580 00000028 f1c48c1444d22dd9a7629ced 000385a8 00000028 f1c48c1444d22ddcb06a8c 000385d0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000385d8 0000010c ffce8f115dcc 000386e4 00000128 ffce8f1f42c317 0003880c 0000018c ffce8f0148c1 00038998 00000028 f0d1870042 000389c0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000389c8 000000ac f1df8d13 00038a74 0000011c f1df8d131b81 00038b90 00000578 f6c4bd1442c71fcfa1 00039108 00000130 e2d98b1c59d3 00039238 00000064 e1db901b43c114 0003929c 00000034 e2de961145d400 000392d0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000392d8 000000b8 f1c48c0142d917f1bc6581fc 00039390 00000014 f1c48c0142d917f1a56484e4 000393a4 000000c0 f1c48c0142d917f1a76e89ec 00039464 00000004 f1c48c0142d917f1a76e89ec48a876b3dc59 00039468 00000244 f1c48c0142d917f1a27981fc72 000396ac 000000f4 f1c48c0142d917f1a27981fc72917caada423a 000397a0 00000030 f1c48c0142d917f1a67e9bf872a07e 000397d0 00000078 f1c48c0142d917f1b66486fb62a37f99ce422b1a927ddbe0794c54 00039848 00000020 f1c48c0142d917f1b46f8cd767bc7fa0c649 00039890 00000000 cdf4941372d400c9 000399e8 00000101 cdc8960b5dd02d 00039aec 00000028 d7f3a73172e233e78154bcc15a8b5e 00039b14 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00039b1c 00000070 fdc8922d4cd619 00039b8c 000002e0 fdc8922d44db1bda 00039e6c 00000070 fdc8922d5ed01cca8a6286fc48ba7599c75f361883 00039edc 00000068 fdc8922d44c600 00039f44 00000e6c dde8b22d69f3 0003adb0 00000410 fdc8922d44db06f1bd658ce465 0003b614 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0003b61c 00000004 fbc58b0672da11de8a7f89ea7bab69 0003c608 00000028 d7f3a73172e233e78154bcc15a8b5e 0003c630 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0003c638 00000030 fbc2812d42d602f1a66e86ec48ad75abc2503c10 0003c668 000000b4 fbc2812d42d602f1a27981fc72916aa7c854 0003c71c 000000b4 fbc2812d42d602f1a76e89ec48be7ba1ca 0003c7d0 00000088 fdc8922d5dc006f1b16a9ce948be7ba1ca 0003c858 00000024 fdc8922d5dc006f1b16a9ce948be7ba1ca6e300d8547cb 0003c87c 0000002c fdc8922d4ad006f1b16a9ce948be7ba1ca 0003c8a8 00000024 fdc8922d4ad006f1b16a9ce948be7ba1ca6e300d8547cb 0003c8cc 0000002c fdc8922d4ad006f1b66486fc65a17699df503511 0003c8f8 00000024 fdc8922d4ad006f1b66486fc65a17699df503511ae40c1fc7d4d 0003c91c 00000024 fdc8922d5dc006f1b66486fc65a17699df503511ae40c1fc7d4d 0003c940 0000002c fdc8922d4ad006f1b1629beb78b87fb4d66e22159647 0003c96c 00000024 fdc8922d4ad006f1b1629beb78b87fb4d66e22159647e7ea614a4271 0003c990 000000cc fdc8922d4cd606c7a36a9ced48a37fa8da 0003ca5c 00000058 fdc8922d5dc006f1b77e9cfc78a045a5c05f26069e4e 0003cab4 00000060 fdc8922d5ed006f1b77e9cfc78a045afc145 0003cb14 00000038 fdc8922d5ed006f1b77e9cfc78a045abca5f27 0003cb4c 000000e4 fdc8922d5ac71bdab05484e179ab 0003cc30 00000074 fdc8922d5ac71bdab05485ed64bd7ba1ca 0003cca4 000000b4 fdc8922d5ed01cca8a6f8dd77abd7d 0003cd58 00000018 fdc8922d40db07f1b96a9bfc48a87bb3c345 0003cd70 00000018 fdc8922d40db07f1b3679cd773ba7699d9583703 0003cd88 00000044 fdc8922d40db07f1b66486ee48aa7fb2ce583e 0003cdcc 00000090 fdc8922d40db07f1b66486ee48a77da8c04337 0003ce5c 00000028 fdc8922d40db07f1b366b7eb62bc45a0c345 0003ce84 00000028 fdc8922d40db07f1b366b7ee7bba45a7dd432b 0003ceac 00000330 fdc8922d40db07f1b366b7e17ba845aac052 0003d1dc 00000188 fdc8922d40db07f1b366b7fa64ba45a8c0433f 0003d364 000002c8 fdc8922d40db07f1b366b7fa64ba45b3c1583c1d85 0003d62c 00000064 fdc8922d5ed006f1a57981e765a76ebf 0003d690 000000a4 fdc8922d40db07f1b1629aed74ba 0003d734 000000a4 fdc8922d40db07f1b36a8afa7ead 0003d7d8 00000114 fdc8922d40db07f1b67e9afa72a06e99df502107864dcaec 0003d8ec 00000120 fdc8922d40db07f1b86a9bfc72bc45b5db50260182 0003da0c 000000b4 fdc8922d40db07f1a57981e663917caac842 0003dac0 000000b4 fdc8922d40db07f1b16e8afd70917caac842 0003db74 0000003c fdc8922d4eda1fdea07f8dd760b973a2f0543617 0003dbb0 00000020 eac7830648ea47ccbc7f9bd763a145a5c75020 0003dbd0 000000e4 fdc8922d4ad006f1b6638deb7cbd6fab 0003dcb4 00000038 fdc8922d58c516cfa16eb7eb71a945a3dd430d198245 0003dcec 000000ac fdc8922d4eda1cc8bc7985e963a775a8f0413d06857dcce768514b6d4326 0003dd98 000001c0 fdc8922d4eda1cc8bc7985e963a775a8 0003df58 00000028 fdc8922d40db07f1a0658af167af69b5 0003df80 00000028 fdc8922d40db07f1b1629be975a27f99dd54311b8747caf1 0003dfa8 00000028 fdc8922d40db07f1b06589ea7bab45b4ca523d029450c1 0003dfd0 00000028 fdc8922d40db07f1b1629be975a27f99c65e0d109040 0003dff8 00000028 fdc8922d40db07f1b06589ea7bab45afc06e361593 0003e020 00000028 fdc8922d40db07f1a5649afc258c 0003e048 00000028 fdc8922d40db07f1a5649afc258f 0003e070 00000028 fdc8922d40db07f1a5649afc268c 0003e098 00000028 fdc8922d40db07f1a5649afc268f 0003e0c0 00000028 fdc8922d40db07f1b66486ee48bc6999da5f3b1a9856 0003e0e8 00000028 fdc8922d40db07f1b66486ee48bc6999c15e2019 0003e110 00000028 fdc8922d40db07f1b6678de965916aa7dc42251b8346 0003e138 00000028 fdc8922d40db07f1b66389e670ab45b6ce4221039e50dc 0003e160 00000028 fdc8922d40db07f1bc6581fc48bd63b5 0003e188 00000028 fdc8922d40db07f1a5649fed659175a0c9 0003e1b0 00000028 fdc8922d40db07f1a76e9bfc76bc6e 0003e1d8 0000003c fdc8922d5ed01cca8a789df848a07599cc503c17944ee7e56b59 0003e214 0000009c fdc8922d5ec002f1b66485e57eba45a0c3503507 0003e2b0 00000254 fdc8922d5ec002f1a6639dfc73a16da8 0003e504 0000002c fdc8922d5ec002f1a5649fed65a17ca0f0422b078547d5 0003e530 0000002c fdc8922d5ec002f1a7789cfa639169bfdc453719 0003e55c 00000064 fdc8922d5ec002f1bc6581fc7eaf76afd5540d078851cced75 0003e5c0 0000010c fdc8922d5ec002f1b6678de965916aa7dc42251b8346 0003e6cc 00000130 fdc8922d5ec002f1b66389e670ab45b6ce4221039e50dc 0003e7fc 00000158 fdc8922d5ec002f1b06589ea7bab45a0ce53201d92 0003e954 00000154 fdc8922d5ec002f1b06589ea7bab45a2c643371785 0003eaa8 00000110 fdc8922d5ec002f1b06589ea7bab45b6c0432645b0 0003ebb8 00000110 fdc8922d5ec002f1b06589ea7bab45b6c0432645b3 0003ecc8 00000110 fdc8922d5ec002f1b06589ea7bab45b6c0432646b0 0003edd8 00000110 fdc8922d5ec002f1b06589ea7bab45b6c0432646b3 0003eee8 0000010c fdc8922d5ec002f1b06589ea7bab45afc06e3301854de7ea614e467157 0003eff4 0000010c fdc8922d5ec002f1b1629be975a27f99c65e0d158456d7d77a475763572c 0003f100 0000010c fdc8922d5ec002f1b06589ea7bab45b4ca523d029450c1 0003f20c 0000010c fdc8922d5ec002f1b1629be975a27f99dd54311b8747caf1 0003f318 000000e8 fdc8922d5ec002f1a0658af167af69b5f05537029841ddfb 0003f400 00000098 fdc8922d5ec002f1b6658ee548bc7fa7cc453b029056ddd7715a4b67 0003f498 00000024 fdc8922d5ec002f1a76e89eb63a76ca7db540d179745e7ed6a4c 0003f4bc 000001d4 fdc8922d5ec002f1b17898e46e917caadb 0003f690 0000048c fdc8922d5ec002f1b366b7ec64be76bff0573e00 0003ff28 00000028 d7f3a73172e233e78154bcc15a8b5e 0003ff50 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0003ff58 00000364 dde8b22d41d016 000402bc 000002c4 dde8b22d4ad006f1a27c81ec 00040580 000000e0 dde8b22d4cd71ddca1548be779a873a1f05420069e50 00040660 000001b0 dde8b22d58c516cfa16eb7ec6ea045a2ce4533 00040810 000000e0 dde8b22d49dc01deb96a91d77ba774a3 000408f0 0000015c dde8b22d49dc01deb96a91d77abd7d 00040a4c 00000244 dde8b22d4eda1cc8bc7985e963a775a8 00040c90 00000034 dde8b22d5ed006f1bc6f84ed48ba73abca5e2700 00040cc4 000001a0 dde8b22d4eda1cc8bc6cb7ed65bc75b4 00040e64 00000114 dde8b22d4cd606c7a36a9ced48a77eaaca6e3f1b9547 00040f78 00000044 dde8b22d4ed917cfa7548ce164be76a7d6 00040fbc 00000038 dde8b22d49dc01cfb7678dd775bb6eb2c05f21 00040ff4 000000d4 dde8b22d49d013cda1629ee963ab 000410c8 0000016c dde8b22d4ad006f1a46c9ae762be 00041234 000001ec dde8b22d41da11cfa16e 00041420 000000b0 dde8b22d4edd13dc8a6a86e17aaf6eafc05f 000414d0 00000054 dde8b22d4ad006f1bc659cfa67ba45a7c1550d168456cce776 00041524 000004f4 dde8b22d4bd82dc8b47f89e448ad68a7dc59 00041a18 00000114 dde8b22d45c22ddba56f89fc729177a9cb540d119f56ddfa 00041b2c 000000b0 dde8b22d45c22ddba56f89fc729177a9cb540d109851c8e47947786f5738 00041bdc 000000b4 dde8b22d45c22ddba56f89fc729177a9cb540d11894bcc 00041f20 00000058 e1df901140c5 00041f78 00000038 e1df90115dcc 00041fb0 00000028 e1df901e48db 00041fd8 0000007c e1df901c4ec50b 00042054 00000178 e1df900642c01e 000421cc 0000012c e1df900642d9 000422f8 00000028 f3df8d1b 00042320 00000028 f3df8d1e 00042348 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00042350 00000008 f5ce962d5fd015f1a27981fc72 00042358 0000000c ffd2bd1548c12ddcb06cb7fa72af7e 00042364 00000054 fb99812148c133cdbe4981fc 000423b8 00000050 fb99813b43dc06efa16789e663a769 00042408 00000054 fb99813141d013dc9c659cce7baf7d 0004245c 00000050 fb99812048d416e7bb7faee476a9 000424ac 00000054 fb99813548db17dcb47f8ddb63a16a84c645 00042500 00000158 fb99813548db17dcb47f8ddb63af68b2ed5826 00042658 000003c8 fb99812258c130d7a16e9b 00042a20 0000017c f1c38d1d5ed02dcbb07b9ae77a 00042b9c 0000041c fb99813548c130d7a16e9b 00042fb8 000000f4 dbe2a12d5fd013ca8a6e8dd773ab6cafcc54 000430ac 00000140 dbe2a12d5ac71bdab0548ded48aa7fb0c65237 000431ec 0000013c e0ce831e72c200c7a16eb7e474aa 00043328 00000180 dbe2a12d7ae73bfa9054a4cb53 000434a8 00000138 e0ce831e72c717cfb15484eb73 000435e0 00000180 dbe2a12d7ff033ea8a47abcc 00043760 000000e0 e0ce831e72c717cfb1548ded67bc75ab 00043840 00000108 dbe2a12d5fd013ca8a6e8df865a177 00043948 000000e0 e0ce831e72c200c7a16eb7ed72be68a9c2 00043a28 00000108 dbe2a12d5ac71bdab0548ded67bc75ab 00043b30 000000f8 dbe2a12d5ac71bdab0548ced75bb7d99c95d331382 00043c28 000000f8 dbe2a12d5ac71bdab05498fa7ea06e99c95d331382 00043d20 00000054 dbe2a12d5fd013ca8a6f8dea62a945a0c3503507 00043d74 00000054 dbe2a12d5fd013ca8a7b9ae179ba45a0c3503507 00043dc8 00000298 dbe2a12d4cd116f1b06e98fa78a345a3dd433d06 00044060 0000011c dbe2a12d4ad006f1bb6e90fc48ab7fb6dd5e3f2b9450cae76a 000442a8 00000038 d7f3a73172f137ff804eb7cc46 000442e0 0000001c d7f3a73172f03cff804eb7cc46 000442fc 00000028 d7f3a73172f436ea8a58b9 00044324 0000005c d7f3a73172e737e39a5dadd7449f 00044380 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00044388 00000044 d1f8bd005ed015f1bc78b7fb7faf68a3cb 000443cc 00000008 f5ce963b63e331ef 000443d4 00000030 f5ce962064f0 00044404 00000024 f5ce96255ffd1bc9bd5c89fc72bc 00044428 00000024 f5ce96255ff91dd9826a9ced65 0004444c 00000028 def9b72d44db01cba77fa9fc5fab7ba2 00044474 00000030 def9b72d44db01cba77fa0e164ba75b4d670263c9443dc 000444a4 00000028 def9b72d5fd01fc1a36e 000444cc 00000168 d1eaa13a689131e19b5fa1c6428b4580e364013c 00044634 000002a8 d1eaa13a689131e19b5fa1c6428b4595fb631b24ae64f4dd4b76 000448dc 0000005c f1ca811a48ea13cab1549aed66bb7fb5db6e261bae41d5d77e5252714c 00044938 00000140 d1eaa13a68ea02dcb07b89fa729d6eb4c64114188451d0 00044a78 00000310 d1eaa13a68ea11c2ba658ddf65a76ea3 00044d88 0000006c d1eaa13a68ea04cbb67f87fa40bc73b2ca 00044df4 00000050 d1eaa13a68ea11c2ba658ddf65a76ea3ee5f36229441cce76a 00044e44 00000398 d1eaa13a68ea11c2ba658dc7659d75b3dd523723834bcced5b514a72483a617e 000451dc 0000003c d1eaa13a68ea11c2ba658dce76a776a3cb63301d8551fce7765b 00045218 00000074 d1eaa13a689134e28058a0d7528c5392fc 0004528c 000000cc d1eaa13a689134e28058a0d7528c5392fc6e163bbf67 00045358 00000074 d1eaa13a689134e28058a0d7528c5392fc6e0120a36be8 000453cc 000000f8 d1eaa13a689134e28058a0d7528c5392fc6e0120a36be8d75c716947 000454c4 0000015c d1eaa13a689134e28058a0d7458c5392fc6e163bbf67 00045620 00000044 d1eaa13a689134e28058a0d7458c5392fc 00045664 00000150 d1eaa13a689134e28058a0d7458c5392fc6e0120a36be8d75c716947 000457b4 00000044 d1eaa13a689134e28058a0d7458c5392fc6e0120a36be8 000457f8 000000a4 d1eaa13a689134e28058a0d759814591ee7806 0004589c 000002e4 d1eaa13a689134e28058a0d7448c5392fc6e163bbf67 00045b80 00000034 d1eaa13a689134e28058a0d7448c5392fc 00045bb4 000004a8 d1eaa13a689134e28058a0d759815e83 0004605c 00000340 d1eaa13a689134e28058a0d7448c5392fc6e0120a36be8d75c716947 0004639c 00000034 d1eaa13a689134e28058a0d7448c5392fc6e0120a36be8 000463d0 00000c18 d1eaa13a689134e28058a0 00046fe8 00000284 d1eaa13a68ea34e28058a0d7459d4e89fd74 0004726c 00000198 d1eaa13a689136eb944fa5c959915c8afa621a 00047404 0000007c d1eaa13a689134e28058a0d7569d4388ec79 00047480 000000d0 d1eaa13a689134e28058a0d7519c5f83f574 00047550 00000034 d1eaa13a689134e28058a0d742805392f0620b3ab26a 00047584 00000034 d1eaa13a689134e28058a0d742805392f0620b3ab26ae7db5b6d 000475b8 00000034 d1eaa13a689134e28058a0cd53914f88e6650d24b070f1dc41 000475ec 0000008c d1eaa13a689134e28058a0d742805392f062063ba1 00047678 000000b4 d1eaa13a689134e28058a0d742805392f062063ba17debcb4b 0004772c 0000051c d1eaa13a689122ef8742bcd148885693fc79 00047c48 000000b8 d1eaa13a68ea00cba67f87fa729176b4da6e341a9e46ddfb 00047d00 0000030c d1eaa13a689121f7865fadc548885693fc79 0004800c 00000220 d1eaa13a689127e09c5fb7ce5b9b498e 0004822c 000000d4 d1eaa13a689122fc9c44bac143974593e178062bb76eeddb50 00048300 00000130 d1eaa13a689134e28058a0d753815483 00048430 000000d4 d1eaa13a689122fc9c44bac143974580e364013c 00048504 0000021c d1eaa13a689134e28058a0d742805392f0751d3ab4 00048720 000000ac d1eaa13a689134e28058a0d742805392f0621127 000487cc 00000090 d1eaa13a689134e28058a0d742805392 0004885c 00000080 d1eaa13a68ea34e28058a0d742805392f073173cb86cfc 000488dc 00000098 d1eaa13a689134e28058a0d742805392f0770031b478fd 00048974 0000012c d1eaa13a689134e28058a0d742805392f070012dbf61f0 00048aa0 0000076c d1eaa13a689134e28058a0d75a8f5388 0004920c 0000024c d1eaa13a68ea25fc9c5fadd7558b528fe175 00049458 00000024 d7f3a73172f137e29c45a3d7539f 0004947c 0000001c d7f3a73172f03cff804eb7cc46 00049498 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000494b0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000494b8 00000040 f5ce962d40dc00dcba79b7ea7aaf7f 000494f8 00000008 f5ce963b63e331ef 00049500 00000030 f5ce962064f0 00049530 00000008 f5ce963f44c700c1a742a6de548f 00049538 00000030 f5ce963f44c700c1a745abc952 00049568 0000056c d1eaa13a68913fe78759a7da488d5683ee7f0724 00049ad4 0000004c d1eaa13a68913fe78759a7da489d4981e36e0535b876 00049b20 00000038 d1eaa13a68913fe78759a7da489d4388ec790d39b761 00049b58 00000044 d1eaa13a68913fe78759a7da48965e99f8701b20 00049b9c 000008f0 d1eaa13a68913fe78759a7da489d4388ec79 0004a48c 00000078 d1eaa13a689120eb975ea1c453914995e87d 0004a504 000000f0 d1eaa13a68ea21eb9b4fb7dc5891578ffd631d26 0004a5f4 00000094 d1eaa13a68ea3fe78759a7da488a5b92ee 0004a688 000002ac d1eaa13a689127e09842bada589c4593e17806 0004a934 00000074 dffca03109f727e7994fb7c95a8a 0004a9a8 000000a4 dffca03109f727e7994fb7cc449d4582ee6513 0004aa4c 00000098 dffca03109f727e7994fb7cc449d4596ee631b20a8 0004aae4 00000078 dffca03109f727e7994fb7cc449d4595f67f113c 0004ab5c 00000074 dffca03172f727e7994fb7cc449d4595f67f1f 0004abd0 00000078 dffca03109f727e7994fb7cc43814582ee6513 0004ac48 00000078 dffca03109f727e7994fb7cc43814596ee631b20a8 0004acc0 00000078 dffca03172f727e7994fb7cc43814595f67f1f 0004ad38 0000007c dffca03109f727e7994fb7c5538f 0004adb4 000000ec dffca03109f727e7994fb7d85e88 0004aea0 00000074 dffca03109f727e7994fb7d8538f 0004af14 00000064 dffca03172f727e7994fb7d85a9e 0004af78 00000094 dffca03172f727e7994fb7d84783 0004b00c 000001f4 dffca03109f727e7994fb7da469c4582e663062d 0004b200 00000154 dffca03109f727e7994fb7da469c458be66201 0004b354 00000170 dffca03109f727e7994fb7da469c4596ee631b20a8 0004b4c4 000001c0 dffca03109f727e7994fb7da469c4595f67f113c 0004b684 00000124 dffca03172f727e7994fb7da469c4595f67f1f 0004b7a8 0000008c dffca03109f727e7994fb7da439c4582ee6513 0004b834 0000008c dffca03109f727e7994fb7da439c4596ee631b20a8 0004b8c0 0000008c dffca03172f727e7994fb7da439c4595f67f1f 0004b94c 00000074 dffca03172f727e7994fb7db538f 0004b9c0 00000198 dffca03109f727e7994fb7df5588 0004bb58 000001b4 dffca03109f727e7994fb7df55884595fb631b24 0004bd0c 000001b8 dffca03109f133fa9454a9ca589c4e83eb 0004bec4 00000988 d1eaa13a68913fe78759a7da488c4889e4741c 0004c84c 00000068 dffca03172d113dab45489ea64a168a4ca55 0004c8b4 000000f8 dffca03109f133fa9454bbcd599a 0004c9ac 00000208 dffca03109f833e59054a1da52915e87fb70 0004cbb4 0000004c dffca03109fd33f89054acc9438f4589f77816 0004cc00 0000015c dffca03109f833e59054a1da52914a87fd78062d 0004cd5c 0000004c dffca03109fd33f89054b8c945874e9ff07e0a3db5 0004cda8 00000160 dffca03172f833e59054a1da5291499fe17c 0004cf08 0000004c dffca03172fd33f89054bbd159834589f77816 0004cf54 000000b8 dffca03172f837e39a59b1d7448b5492 0004d00c 00000220 dffca03109e533fc9c5fb1d7458b5983e6671730 0004d22c 000000e0 dffca03109e533fc9c5fb1d7448b5492 0004d30c 00000080 dffca03109e520e1964ebbdb488f5782 0004d38c 0000010c dffca03109e520e1964ebbdb488a4995f0611326b876e1 0004d498 0000010c dffca03172e520e1964ebbdb488a4995f0620b3abc 0004d5a4 000000a4 dffca03109e520e1964ebbdb488a4e89f0611326b876e1 0004d648 000000a4 dffca03109e520e1964ebbdb488a4e89f0620b3ab26a 0004d6ec 00000104 dffca03109e520e1964ebbdb488a4e89f0751320b0 0004d7f0 000000a4 dffca03172e520e1964ebbdb488a4e89f0620b3abc 0004d894 00000174 dffca03109e520e1964ebbdb48835e87f06916 0004da08 000001b0 dffca03109e520e1964ebbdb48835e87 0004dbb8 00000164 dffca03109e520e1964ebbdb489e5e87 0004dd1c 00000160 dffca03109e520e1964ebbdb489e5380 0004de7c 000002f0 dffca03109e520e1964ebbdb489c4b94f0751320b0 0004e16c 0000023c dffca03109e520e1964ebbdb489c4b94f0611326b876e1 0004e3a8 000000b8 dffca03172e520e1964ebbdb489c4b94f0620b3abc 0004e460 00000174 dffca03172e520e1964ebbdb489d5e87 0004e5d4 00000348 dffca03109e520e1964ebbdb48995880 0004e91c 0000014c dffca03172e527e29954a5cd5a81489f 0004ea68 000000e0 d1eaa13a68ea22fb9947b7c552835594f6 0004eb48 00000070 dffca03172fd33f89054b8dd5b824589f77816 0004ebb8 00000154 dffca03172e527fd9d54a5cd5a81489f 0004ed0c 000000bc dffca03172e637e09154acc9438f 0004edc8 000000b4 dffca03172e520e1964ebbdb489c4e94f0620b3abc 0004ee7c 000000a8 dffca03109e520e1964ebbdb489c4e94f0620b3ab26a 0004ef24 000000c0 dffca03109e520e1964ebbdb489c4e94f0611326b876e1 0004efe4 00000118 dffca03109f833e59054bcda52915e87fb70 0004f0fc 000000e4 dffca03109e520e1964ebbdb489c4e94f0751320b0 0004f1e0 00000070 ffdc801172c617c0b15485ec76 0004f250 00000128 dffca03109e520e1964ebbdb488a4995f0751320b0 0004f378 00000360 dffca03109f133fa9454bacd548b5390ea75 0004f6d8 000000c0 dffca03172e637e09154a5c7458b 0004f798 000000dc dffca03109e62be09643b7db52804e 0004f874 000002bc dffca03172e62be09854bacd548b5390ea75 0004fb30 000000dc dffca03172e62be09854bbcd599a 0004fc0c 0000006c dffca03109f43fea8a4aabc3 0004fc78 000000d4 dffca03109f121fd8a4fa9dc56915b85e4 0004fd4c 000000c4 dffca03109f121fd8a5ba9da5e9a4399ee7219 0004fe10 000000c8 dffca03109f121fd8a58b1c654864587ec7a 0004fed8 00000144 dffca03172f121fd8a58b1c65a915b85e4 0005001c 00000090 dffca03109f126e18a4fa9dc56915b85e4 000500ac 00000090 dffca03109f126e18a5ba9da5e9a4399ee7219 0005013c 00000090 dffca03172f126e18a58b1c65a915b85e4 000501cc 000000a4 dffca03109f836ef8a4aabc3 00050270 0000006c dffca03109e536ef8a4aabc3 000502dc 0000006c dffca03109e536ef8a45a7dc488f598d 00050348 000000dc dffca03109e53be88a4aabc3 00050424 00000084 dffca03172e53ffe8a4aabc3 000504a8 000000a8 dffca03172e522e38a4aabc3 00050550 00000174 dffca03172f837e39a59b1d7458b5983e6671730 000506c4 000000d4 dffca03109e723fc8a4fa9dc56915b85e4 00050798 000000c8 dffca03109e723fc8a5ba9da5e9a4399ee7219 00050860 000000cc dffca03109e723fc8a58b1c654864587ec7a 0005092c 00000144 dffca03172e723fc8a58b1c65a915b85e4 00050a70 000000f8 dffca03109e726fc8a4fa9dc56915b85e4 00050b68 00000118 dffca03109e726fc8a5ba9da5e9a4399ee7219 00050c80 00000118 dffca03172e726fc8a58b1c65a915b85e4 00050d98 0000006c dffca03172e636ef8a4aabc3 00050e04 000000e8 dffca03109e230e88a4aabc3 00050f10 0000000c d7f3a73172fc3ce78154acd9 00050f1c 00000024 d7f3a73172f137e29c45a3d7539f 00050f40 0000001c d7f3a73172f03cff804eb7cc46 00050f5c 00000028 d7f3a73172f436ea8a58b9 00050f84 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 00050fc8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00050fd0 00000040 f5ce962d40dc00dcba79b7ea7aaf7f 00051010 00000034 f5ce962d5dc71bc3b47991d775a37ba3 00051044 00000008 f5ce963b63e331ef 0005104c 00000038 f5ce96356ef437 00051084 00000030 f5ce963c6ef437 000510b4 00000030 f5ce962064f0 000510e4 00000030 f5ce963060f437 00051114 00000008 f5ce963f44c700c1a742a6de548f 0005111c 00000030 f5ce963f44c700c1a745abc952 0005114c 00000024 f5ce96255ffd1bc9bd5c89fc72bc 00051170 00000024 f5ce96255ff91dd9826a9ced65 00051194 00000054 f1c6bd1548c12ddcbb67 000511e8 00000028 def9b72d44db01cba77fa9fc5fab7ba2 00051210 00000030 def9b72d44db01cba77fbfe163a65ea7db501300b947d9ec 00051240 00000028 def9b72d5fd01fc1a36e 00051268 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 0005127c 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 00051290 00000244 d1eaa13a689127e08644baca48995899e2780127 000514d4 000000a0 d1eaa13a689133ec9a59bcd7408c458be66201 00051574 00000278 d1eaa13a689127e08644baca48995899eb780020a8 000517ec 000000a0 d1eaa13a689133ec9a59bcd7408c4582e663062d 0005188c 00000430 d1eaa13a689136e18644baca48995899eb780020a8 00051cbc 000000c8 d1eaa13a689133ec8644baca48995899eb780020a8 00051d84 00000064 dffca03109f727e7994fb7cc5e9d5b84e374 00051de8 00000074 d1eaa13a689130fc904aa3d75a874894e063 00051e5c 000000a0 d1eaa13a689131e69048a3d7528c5392fc 00051efc 00000064 d1eaa13a689131e29a45add759815e83 00051f60 000000c8 d1eaa13a689131e1985ba4cd438b4580ee781e3ba767ead756716347 00052028 000007a4 d1eaa13a689131e1985ba4cd438b4595fb631b24ae64f4dd40 000527cc 00000084 d1eaa13a689131e1985ba4cd438b4595fb631b24ae64f4dd4b76 00052850 000000cc d1eaa13a689131e1985ba4cd438b4594ee781647ae75eac14c7b 0005291c 0000002c d1eaa13a689137f69643a9c6508b 00052948 00000428 d1eaa13a689134ef9c47a7de529c4588e07517 00052d70 0000006c d1eaa13a689134ef9c47adcc48814c83fd6e1c3bb567 00052ddc 000005e4 d1eaa13a689134e28053b7df55915e8ffd650b 000533c0 000000c8 d1eaa13a689134e28058a0d7408c4582e663062d 00053488 000003d8 d1eaa13a689134e28053b7df5591578ffc62 00053860 000000c8 d1eaa13a689134e28058a0d7408c458be66201 00053928 00000104 d1eaa13a68ea34e18045acd75e835b81ea 00053a2c 00000094 d1eaa13a689134fc904eb2cd 00053ac0 0000003c d1eaa13a689135eb8154abc954865f99ec7e1c30b876f1c756 00053afc 00000018 d1eaa13a689135eb8154abc954865f99fc780831 00053b14 0000007c d1eaa13a689135eb8154acc9438f 00053b90 00000058 d1eaa13a689135eb8154bddd5e8a49 00053be8 00000160 d1eaa13a689135fc9a5eb8d75e805596ea631320b874fd 00053d48 00000040 d1eaa13a68913aef834eb7df55915e87fb70 00053d88 00000570 d1eaa13a68ea3be3944cadd754814a9f 000542f8 000000e4 d1eaa13a68913be09644a5d85b8b4e83f063133db511e7df4a777347 000543dc 00000480 d1eaa13a68913be09644a5d85b8b4e83f0771e21a26a 0005485c 00000208 d1eaa13a68ea3fed8a5ba9da43875b8af0721d39a16efddc5171695d761e5c5f2c25d137f5ff2d 00054a64 000001dc d1eaa13a68913be09644a5d85b8b4e83f063133db517e7df4a777347 00054c40 00000368 d1eaa13a68913be09644a5d85b8b4e83f0620626b872e7ce546b744a 00054fa8 00000280 d1eaa13a68913be09a5badda569a5390ea 00055228 0000006c d1eaa13a68913bfd8a4fa1c950915893e9771726 00055294 00000624 d1eaa13a68913be09c5fb7c641 000558b8 000001c4 d1eaa13a68913ee19640b7c5529a5b 00055a7c 000000a0 dffca03109f727e7994fb7c453915580e97d1b3ab4 00055b1c 00000158 dffca03109e520e1964ebbdb48825e99e0771438b86cfd 00055c74 00000084 dffca03109f936f19a4daec45e805f99ee7219 00055cf8 00000410 d1eaa13a68913de89347a1c652 00056108 00000104 d1eaa13a68913de89347a1c652915592e77400 0005620c 00000140 dffca03109f727e7994fb7c453915588e3781c31 0005634c 000000e8 dffca03109f936f19a45a4c1598b4587ec7a 00056434 00000084 d1eaa13a68913de09942a6cd48814e8eea63 000564b8 00000ce8 d1eaa13a68913dfe9059a9dc5e985f 000571a0 000007f4 d1eaa13a689122ef875fa1c95b91528ffb 00057994 000001bc d1eaa13a689122fc904daddc54864582ee6513 00057b50 000005a4 d1eaa13a689122fc904daddc5486 000580f4 00000098 d1eaa13a689122fc904daddc5486458ee665 0005818c 00000054 d1eaa13a68ea01cba1589cfa7ebe4981e374111b844cccfb 000581e0 00000194 d1eaa13a68ea01cba15891e544ba68afdf621538b461d7fd764a54 00058374 000000a4 d1eaa13a68ea10dbbc678cdb50826980da5d3e278550d1f8 00058418 00000278 d1eaa13a68ea10dbbc678cdb6ea34981e34214019d4eebfc6a5757 00058690 0000040c d1eaa13a689122fc905ba9da52914887e6756227ae75eac14c7b 00058a9c 0000040c d1eaa13a689122fc905ba9da52914887e6756327ae75eac14c7b 00058ea8 00000508 d1eaa13a689122fc905ba9da52914887e675612ba670f1dc5d 000593b0 00000044 d1eaa13a68ea20ef9c4fdbd7478f488ffb680d30be6cfd 000593f4 00000130 d1eaa13a689122fc905ba9da52914992fd78022bb76eeddb5061635069135a5c 00059524 00000368 d1eaa13a689122fc905ba9da52914d84f0751b26a57b 0005988c 000000ac dffca03109f727e7994fb7cd598f588aea 00059938 0000015c dffca03109f03cef9747add7568d51 00059a94 000006f0 d1eaa13a689122fc9a48addb44915490f0751320b0 0005a184 00000054 d1eaa13a689122fb874cad 0005a1d8 000000b8 d1eaa13a68ea02dba76c8dd765ab7dafc05f 0005a290 0000019c dffca03109f727e7994fb7d8538a 0005a42c 000001a0 dffca03109f727e7994fb7d8538a4588e07517 0005a5cc 00000060 dffca03109f727e7994fb7d8538a4595ec631333 0005a62c 00000070 dffca03109e536ea8a4aabc3 0005a69c 00000078 dffca03109e536ea8a45a7cc52915b85e4 0005a714 00000078 dffca03109e536ea8a58abda56894587ec7a 0005a78c 000002d8 f1ca811a48ea16c18a7b9dfa70ab45a2c643260d 0005aa64 00000104 d1eaa13a68ea02dba76c8dd773a768b2d66e2011964bd7e6 0005ab68 000000e4 d1eaa13a689123ed9d4eabc3488b588ffb62 0005ac4c 000000b4 d1eaa13a689123fb9059b1d7458b5b82f0701120b874f1dc41 0005ad00 000000d8 d1eaa13a689123fb9059b1d7429d5f94f0701120b874f1dc41 0005add8 0000020c d1eaa13a689123fb9b47a7cb5c 0005afe4 00000114 d1eaa13a689120eb975ea1c453915987ec79172bbd6bebdc 0005b0f8 00000218 d1eaa13a689134ef9c47a7de529c 0005b310 00000068 d1eaa13a689120eb994ea9db5291598ae07f17 0005b378 00000188 d1eaa13a689121ed874aafd75a874894e063 0005b500 000002cc d1eaa13a689121ed874aafd7479c538bee630b 0005b7cc 0000021c d1eaa13a689122fb874cadd753874892f6 0005b9e8 000000f0 dffca03109e520e1964ebbdb489e5e82 0005bad8 000002c4 dffca03109e520e1964ebbdb48825e99e07f1e3dbf67 0005bd9c 00000654 d1eaa13a689131e2904abad7538f4e87f07d1d27a5 0005c3f0 00000118 d1eaa13a689121e0945bbbc0589a4595f67f113c 0005c508 000000c8 d1eaa13a689121f79b48a0 0005c5d0 000001c4 d1eaa13a689122fc904daddc54865f82 0005c794 00000060 d1eaa13a68ea21f79b46b7cc58805f 0005c7f4 0000025c d1eaa13a689121f79b48a0d75a874894e063 0005ca50 00000490 d1eaa13a689131fc9458a0c7418b48 0005cee0 00000334 d1eaa13a689131e1985ba4cd438b4580ee781e3ba767ea 0005d214 00000ba8 d1eaa13a68913de09942a6cd 0005ddbc 0000020c d1eaa13a689126e19458bcd7548f598eea 0005dfc8 000000a0 d1eaa13a689127e09944abc348835f92ee 0005e068 0000013c d1eaa13a689127e09944abc348835f92ee6e0221a365fd 0005e1a4 000000e4 d1eaa13a689127fe914abccd488d5384 0005e288 000001a0 d1eaa13a689122fc9a48addb44915490 0005e428 00000248 dffca03109e520e1964ebbdb488b5487ed7d17 0005e670 000000ac d1eaa13a68ea3be3944cadd754814a8fea75 0005e71c 0000010c d1eaa13a689135eb8154a6db54914f93e675 0005e828 00000080 d1eaa13a689131e2904abad75a874894e0630d3db5 0005e8a8 000000cc dffca03109f13bfd9449a4cd488f598d 0005e974 000000d8 d6e2a33509f633ed9d4eb7c144915e8ffd650b 0005ea4c 00000068 f1c6bd1b43dc06f1a7658c 0005eab4 00000f78 d1eaa13a68ea1bc0bc7f 0005fe00 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0005fe08 00000008 f5ce963b63e331ef 0005fe10 00000030 f5ce962064f0 0005fe40 00000008 f5ce963f44c700c1a742a6de548f 0005fe48 00000060 e7db861359d02dcfbb6fb7eb7fab79adf0533d15 0005fea8 0000009c ffdc801172d217da8a7b9ae76fb745a2ce4533 0005ff44 00000080 dffca03172d81bdca7649ad760ac45a2ce4533 0005ffc4 00000050 ffdc801172dd13d8b05498fa78b66399c0493b10 00060014 0000031c ffdc801172d707c7b96fb7fa67aa 00060330 000001a8 ffdc801172c702ca8a6a8be3 000604d8 00000318 ffdc801172c500c1ad72b7ec76ba7b99dd522410 000607f0 000000d0 ffdc801172d707c7b96fb7f873bc 000608c0 000001e4 ffdc801172c516dc8a6a8be3 00060aa4 00000118 ffdc801172c500c1b66e9bfb48be7dab 00060bbc 00000174 ffdc801172c500c1b66e9bfb48aa69b6 00060d30 000001c0 ffdc801172c500cba56a9aed48a97fb2f0593d07857ddce96c5f 00060ef0 00000280 ffdc801172dd13d8b0549af873917ea7db50 00061170 0000031c ffdc801172c500c1b66e9bfb48bc6aa2 0006148c 000001ec ffdc801172d410ddba798ad767bc75bed66e36158543 00061678 0000018c ffdc801172c500c1ad72b7ec76ba7b99dc543c00 00061804 00000228 ffdc801172c500c1b66e9bfb48be7eb4 00061a2c 000000bc ffdc801172d707c7b96fb7ec64be 00061ae8 00000160 ffdc801172d101de8a6a8be3 00061c48 000000a0 ffdc801172d707c7b96fb7f870a3 00061ce8 000000cc ffdc801172c515c38a6a8be3 00061db4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00061dbc 00000094 dffca03172d300cbb05498fa78b66399cd44341282 00061e50 0000009c dffca03172d61ecbb4659df848be68a9d748 00061eec 00000050 dffca03172d81bdca7649ad773af6ea7 00061f3c 0000007c ffdc801172d707c7b96fb7fa64bc 00061fb8 000000ac ffdc801172c701dc8a6a8be3 00062064 000000b8 ffdc801172c500c1b66e9bfb48bc68a2 0006211c 000000fc ffdc801172c717cfb1548ce963af45b5ca5f26 00062218 00000134 ffdc801172c500c1b66e9bfb48bc7eb4 0006234c 00000088 ffdc801172d707c7b96fb7ec64bc 000623d4 000000ac ffdc801172d101dc8a6a8be3 00062480 0000008c ffdc801172d217da8a7b9ae76fb745a4da573407 0006250c 0000010c ffdc801172c500c1b66e9bfb48bc69b4 00062618 00000090 ffdc801172dd13d8b0548afd71a869 000626a8 00000090 ffdc801172dd13d8b0549aed76aa45a9d75836 00062738 00000100 ffdc801172d707c7b96fb7fa65aa 00062838 00000150 ffdc801172c700ca8a6a8be3 00062988 00000280 ffdc801172c717cfb1548ce963af45b4cc4736 00062c08 000000c4 ffdc801172d707c7b96fb7fa73bc 00062ccc 00000160 ffdc801172c716dc8a6a8be3 00062e2c 000000fc ffdc801172c500c1b66e9bfb48aa69b4 00062f28 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00062f30 00000050 ffdc801172d217da8a7d8dfa7ea86399cb502615 00062f80 00000030 dffca03172d81bdca7649ad761ab68afc9480d109056d9 00062fb0 0000005c ffdc801172dd13d8b0549eed65a77cbff05e2a1d95 0006300c 00000118 ffdc801172d707c7b96fb7fa61aa 00063124 0000013c ffdc801172c704ca8a6a8be3 00063260 000002c0 ffdc801172c317dcbc6d91d773af6ea7f043310295 00063520 000000d8 ffdc801172d707c7b96fb7fe73bc 000635f8 00000198 ffdc801172c316dc8a6a8be3 00063790 00000170 ffdc801172c500c1b66e9bfb48aa69b0 00063900 0000009c ffdc801172dd13d8b0549eed65a77cbff05327129751 0006399c 00000118 ffdc801172dd13d8b0549eed65a77cbff055330090 00063ab4 0000015c ffdc801172c500c1b66e9bfb48bc6ca2 00063c10 00000114 ffdc801172c317dcbc6d91d773af6ea7f042371a85 00063d24 000001a8 ffdc801172c500c1b66e9bfb48b87eb4 00063ecc 000000b8 ffdc801172d707c7b96fb7ec64b8 00063f84 00000130 ffdc801172d101d88a6a8be3 000640b4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000640bc 00000028 def9b72d5fd01fc1a36e 000640e4 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 000640f8 00000010 f1ca811a48ea1bc0bc7fa6de55bb7ca0ca4301009041d3 00064108 00000018 f1ca811a48ea11c1a0659cce65ab7f88f97327129747cafb 00064120 00000034 f1ca811a48ea17c0ba7e8fe051bc7fa3e16710019744ddfa6b 00064154 0000002c f1ca811a48ea15cba14d9aed72804c84da57341183 00064180 00000010 f1ca811a48ea1bc0bc7faafd71a87fb4fc4533179a 00064190 00000018 f1ca811a48ea11c1a0659cce65ab7f84da5734118351 000641a8 00000034 f1ca811a48ea17c0ba7e8fe051bc7fa3ed4434129450cb 000641dc 00000038 f1ca811a48ea14dcb06eaafd71a87fb4dc 00064214 0000000c f1ca811a48ea1bc0bc7fb8e77ba779bfed4434129450ebfc795d4c 00064220 00000014 f1ca811a48ea14dcb06eb8e77ba779bfed4434129450 00064234 0000003c d1eaa13a68ea14dcb06eb8e77ba779bfed4434129450cb 00064270 00000014 f1ca811a48ea11c1a0659cce65ab7f96c05d3b178860cdee7e5b5571 00064284 00000034 f1ca811a48ea17c0ba7e8fe051bc7fa3ff5e3e1d925bfafd7e58427057 000642b8 00000028 f1ca811a48ea15cba14d9aed729e75aac6522b368444deed6a 000642e0 00000070 d1eaa13a68ea07deb16a9ced48ac77a7ca 00064350 00000198 d1eaa13a68ea00cbb3798dfb7f916ca9c36e30019744c8e77752 000644e8 000000c4 f1ca811a48ea15cba14d9aed728c6fa0c9542007 000645ac 0000005c f1ca811a48ea15cba14d9aed728c6fa0c95420 00064608 00000178 d1eaa13a68ea00cbb3798dfb7f916ab4c05620159c7ddafd7e58576d4b33 00064780 00000078 d1eaa13a68ea15cba14d9aed729e75aac6522b368444deed6a4d 000647f8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00064800 00000028 def9b72d44db01cba77fa9fc5fab7ba2 00064828 00000030 def9b72d44db01cba77fbfe163a65ea7db501300b947d9ec 00064858 00000030 def9b72d44db01cba77fa0e164ba75b4d670263c9443dc 00064888 00000038 f1ca811a48ea1edca05481e664ab68b2 000648c0 00000028 def9b72d5fd01fc1a36e 000648e8 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 000648fc 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 00064910 00000198 d1eaa13a68ea00cbb3798dfb7f9179a8c055372b814dd7e4 00064aa8 000000c4 d1eaa13a68ea14dcb06eb7ec7ebc6ebff05327129747cafb 00064b6c 00000074 d1eaa13a68ea01deb9629cd771a768b5db 00064be0 00000064 d1eaa13a68ea01deb9629cd77baf69b2 00064c44 00000084 d1eaa13a68ea06dca0658be963ab45a4da5734118351 00064cc8 00000068 d1eaa13a68ea06dca0658be963ab45a0c6432100 00064d30 000000b0 d1eaa13a68ea11c0ba6f8dd771bc7fa3f05327129747cafb 00064de0 000001c0 d1eaa13a68ea14c0ba6f8dd771a776aaca550d1982 00064fa0 00000138 d1eaa13a68ea14c0ba6f8dd765ab7eb3cc54362b9c51 000650d8 000002c4 d1eaa13a68ea00cbb8649eed48aa73b4db480d179f4ddced 0006539c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000653a4 0000006c d1eaa13a68ea02dcb06d8dfc74a645a0c65f36 00065410 00000030 f1ca811a48ea02dcb06d8dfc74a645aadd443f1b8747 00065440 0000009c d1eaa13a68ea02dcb06d8dfc74a645b4ca5c3d02944cd7ec7d 000654dc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000654e4 00000054 f1c6bd1548c12ddcbb67 00065538 00000048 def9b72d44db01cba77fa9ee63ab6885da4320119f56 00065580 00000028 def9b72d44db01cba77fa9fc5fab7ba2 000655a8 00000030 def9b72d44db01cba77fbfe163a65ea7db501300b947d9ec 000655d8 00000030 def9b72d44db01cba77fa0e164ba75b4d670263c9443dc 00065608 00000038 f1ca811a48ea1edca05481e664ab68b2 00065640 00000028 def9b72d5fd01fc1a36e 00065668 0000000c f1c58d1648ea15cba1589ce963ab 00065674 00000008 f1c58d1648ea01cba1589ce963ab 0006567c 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 00065690 00000098 fbc5861755ea14c7bb6f 00065728 000000ac fbc5861755ea1bc0a66e9afc 000657d4 000000e0 fbc5861755ea15cba14587ec728f74a2e65f21118356 000658b4 00000078 fbc5861755ea1bc0a66e9afc47af68afdb48 0006592c 000001b4 fbc5861755ea1fcba76c8dc678aa7fb5 00065ae0 0000036c fbc5861755ea00cbb77e81e4738868a9c2731f35 00065e4c 00000188 fbc5861755ea00cbb8649eed 00065fd4 00000170 fbc5861755ea01deb9629cc678aa7f 00066144 00000024 d7f3a73172f137e29c45a3d7539f 00066168 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00066170 00000008 f5ce963b63e331ef 00066178 00000030 f5ce962064f0 000661a8 00000054 f1c6bd1548c12ddcbb67 000661fc 00000028 def9b72d44db01cba77fa9fc5fab7ba2 00066224 00000030 def9b72d44db01cba77fbfe163a65ea7db501300b947d9ec 00066254 00000030 def9b72d44db01cba77fa0e164ba75b4d670263c9443dc 00066284 00000038 f1ca811a48ea1edca05481e664ab68b2 000662bc 00000028 def9b72d5fd01fc1a36e 000662e4 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 000662f8 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 0006630c 000000c4 d1eaa13a68ea34fc904eb7d8569c5392f66e1c3bb567 000663d0 00000050 d1eaa13a68ea31e29a45add7408c5c99ec7e1f24bd67eccd 00066420 000000ac d1eaa13a68ea31e1985ba4cd438b4585e37e1c31ae64f4dd4b76 000664cc 000008f8 d1eaa13a689131e1985ba4cd438b4580e3640a 00066dc4 00000084 d1eaa13a689131e1985ba4cd438b4580e364013c 00066e48 000001cc d1eaa13a689135eb8154b8c945874e9ff07f1d30b4 00067014 000001cc d1eaa13a68913ee19640 000671e0 00000040 d1eaa13a689122e1855ea4c9438b 00067220 00000378 d1eaa13a689122fc905ba9da52915c8afa621a 00067598 000001fc d1eaa13a689122fc905ba9da52914887e675672ba670f1dc5d 00067794 00000220 d1eaa13a689122fc905ba9da52914d84f07c1b27a2 000679b4 0000008c d1eaa13a689122fb8154aec6588a5f99e3630727 00067a40 00000190 d1eaa13a689133fd8642afc648885489eb74 00067bd0 00000234 d1eaa13a689136e18644baca48995899e2780127 00067e04 000000c8 d1eaa13a689133ec8644baca48995899e2780127 00067ecc 00000214 d1eaa13a689127e09944abc3 000680e0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000680e8 00000238 d1f8bd2078fb2ded9d40acdb5c915596 00068320 0000033c d1f8bd1145de16ddbe549aeb619168a3de 0006865c 00000034 f1d8bd1145de16ddbe549bfc76bc6e99c3550d189e4dc8 00068690 00000290 f1d8bd1145de16ddbe549bed7bab79b2f045201194 00068920 000000f4 f1d8bd1145de16ddbe5499fd7eab69a5ca6e26069447 00068a14 0000009c f1d8bd1145de16ddbe549de666bb73a3dc52372b8550dded 00068ab0 00000240 f1d8bd1145de16ddbe5486ed6fba45aacb 00068cf0 0000009c f1d8bd1145de16ddbe5481fc72bc7bb2ca6e2007954fe7fa6b5a78634a2b70 00068d8c 0000001c f1d8bd1145de2dcbbb6a8ae472 00068da8 0000041c f1d8bd1145de16ddbe549bed63917fb4dd5e202b934bccfb 000691c4 00000094 f1d8bd025fdc1cda8a6880e373bd7199cc5e271a85 00069258 000000b0 f1d8bd1145de16ddbe5484e7709168b5cb6e3706834dca 00069308 00000104 f1d8bd1145de16ddbe5481fc72bc7bb2ca6e2007954fe7fa6b5a78724b2c61 0006940c 0000009c f1d8bd005ed12ddca66f85d774a67fa5c46e221582518a 000694a8 0000018c f1d8bd005ed12ddca678b7eb7fab79ad 00069634 00000068 f1d8bd1145de16ddbe5484e7709173a9f05420069e50 0006969c 00000068 f1d8bd1145de16ddbe5484e770916ca9c36e3706834dca 00069704 00000068 f1d8bd1145de16ddbe5484e770917cb4ca540d118350d7fa 0006976c 00000078 f1d8bd1145de16ddbe549bfd64be7fa8cb6e33189d 000697e4 00000074 f1d8bd1145de16ddbe549aed64bb77a3f0503e18 00069858 000000dc f1d8bd1145de16ddbe5481e67eba45a2c2543f 00069934 00000148 f1d8bd1145de16ddbe5481e67eba45b5c9413019 00069a7c 000001e4 f1d8bd1145de16ddbe5486ed6fba45b5c941301982 00069c60 00000098 f1d8bd1548c12dddb37b8ae548a67fa7cb5420 00069cf8 00000030 f1d8bd104cd619f1b86a98d761ac7b 00069d28 00000158 f1d8bd1145de16ddbe5498fa7ea06e99df423713ae4fd9f8 00069e80 000000c4 f1d8bd1444db16f1a36484d77bac7b99dd4236 00069f44 00000260 f1d8bd1145de16ddbe549afd799175b2c754202b9256cae46a 0006a1a4 000000a4 f1d8bd1145de2dddb07f9df8 0006a248 00000040 f1d8bd1145de16ddbe548de674a17ea3f05e22 0006a288 000000d4 f1d8bd1145de16ddbe5484e770917cb6cd5c0d118350d7fa 0006a35c 0000012c f1d8bd005ed11ff1b86a83ed48bd7cb6cd5c 0006a488 000000e8 f1d8bd1145d011c58a6486ed48bd7cb6cd5c 0006a570 00000398 f1d8bd014bc510c38a6d98ea7a9179aeca5239 0006a908 000000ec f1d8bd025fdc1cda8a6e9afa78bc45aac64226 0006a9f4 000000c4 f1d8bd1145de16ddbe549bed63916fb5ca430d179052e7e471534e7657 0006aab8 00000024 f1d8bd1145de16ddbe548fed639168b5ca560d18984fd1fc 0006aadc 00000648 f1d8bd005ed12ddca66f85d774a67fa5c46e2215825189 0006b124 0000004c f1d8bd005ed12ddca66f85d774a67fa5c4 0006b170 00000530 f1d8bd1b59d000cfa16eb7fa64aa77 0006b6a0 0000012c f1d8bd1b59d000cfa16eb7eb64a27e99dd42361982 0006b7cc 0000053c f1d8bd1b59d000cfa16eb7fa64aa 0006bd08 000001d8 f1d8bd1b59d000cfa16eb7fd64ab6899dd423607 0006bee0 00000188 f1d8bd1b59d000cfa16eb7f87baa77a5f043211082 0006c068 00000190 f1d8bd1b59d000cfa16eb7eb64a27e99dd423607 0006c1f8 00000190 f1d8bd1b59d000cfa16eb7e478ad7baaf043211082 0006c388 00000074 f1d8bd1145de2ddca66fb7fa64bd 0006c3fc 0000002c f1d8bd1145de2dc2b07d8de426 0006c428 000000ec f1d8bd1145de2dccb46883e576be 0006c514 00000118 f1d8bd1145de16ddbe548ee17ba245aacb6e21009056cdfb474a4660483a 0006c62c 0000003c f1d8bd1145de16ddbe548ced76a276a9cc6e21009056cdfb474a4660483a 0006c668 000000ac d1f8bd145fd017f1a16e85f878bc7bb4d66e2218954fdb 0006c714 000000a0 f1d8bd075dd113dab0549ced7abe45aac25022 0006c7b4 000002b0 d1f8bd1548c12ddab06698d765bd7eabdc 0006ca64 00000390 d1f8bd1e42d416f1a16e85f878bc7bb4d66e2218954fdb 0006cdf4 0000021c f1d8bd1b59d000cfa16eb7fd64ab6899dd42361982 0006d010 000001c0 f1d8bd1b59d000cfa16eb7f87baa77a5f04321109c51 0006d1d0 00000240 f1d8bd1b59d000cfa16eb7e478ad7baaf04321109c51e7fa6b5a54 0006d410 00000098 f1d8bd1145de2ddca66fb7fa64aa77 0006d4a8 0000002c f1d8bd1145de2dc2b07d8de425 0006d4d4 00000224 f1d8bd1b59d000cfa16eb7e97ba245b4dc553f07 0006d6f8 00000508 f1d8bd1145de2ddca66f85d771be78ab 0006dc00 0000002c f1d8bd1145de2dc2b07d8de424 0006dc2c 00000a48 d1f8bd2d6efd39ea8640b7c5568754 0006f714 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0006f71c 00000338 d1f8bd2d6ee63eea8a46a9c159 0006fa54 000000cc d1f8bd2d6efa22f78a5bbbc9459d 0006fb20 000001a4 d1f8c63f61f12dfc904aac 0006fcc4 00000198 d1f8c63f61f12df98742bccd 0006fe5c 0000010c d1f8bd2d60f936f1834ebac15197458bea631531 0006ff68 0000056c d1f8bd2d7ff033e29c51add7549d5682 000704d4 0000024c d1f8bd2d78fb20eb9447a1d252915995e375 00070720 000000a0 f1d8bd1441c001c68a7a9b 000707c0 0000013c f1d8bd1548c12ddca66f81e564916bb5 000708fc 000000a0 f1d8bd1b43dc06c7b46781f2729179b4ca502611ae41cbe47c 0007099c 000004f4 f1d8bd0242c507c2b47f8dd774bd76a2 00070e90 000000e8 d1f8bd2d7dfa22fb994abccd488d498aeb 00070f78 00000294 f1d8bd0448c71ff1b16e89e47ba179a7db54 0007120c 0000001c f1d8bd0448c71ff1b26e9cd764a760a3f05333 00071228 000001c8 f1d8bd115ed916f1a76e85e761ab45aacb50362b8747cae5 000713f0 00000228 d1f8bd2d6ee737ef814eb7cb44825e 00071618 000003f8 f1d8bd0448c71ff1a76e89e47eb47f 00071adc 00000024 d7f3a73172f137e29c45a3d7539f 00071b00 00000028 d7f3a73172f436ea8a58b9 00071b28 0000005c d7f3a73172e737e39a5dadd7449f 00071b84 00000028 d7f3a73172e233e78154bcc15a8b5e 00071bac 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00071bb4 00000030 d1f8bd3568e12ded9742bcd7479c5390ee6517 00071be4 000001b4 f1d8bd164fd22ddca678b7f865a774b2 00071d98 00000058 f1d8bd114cc51fc9a7549aed7aa16ca3f0552716 00071df0 00000080 f1d8bd114cc51fc9a75492ed65a145a0df5030 00071e70 00000140 f1d8bd1e49ea15cba1548be967af79afdb480d0682 00071fb0 00000060 f1d8bd1e49ea15cba15484ec76aa45a8c05836 00072010 00000064 f1d8bd1e49ea15cba1549ae97eaa45b2d64137 00072074 0000007c f1d8bd1e49ea15cba1549ee576be 000720f0 00000058 f1d8bd1e49ea1bdd8a6689fb63ab68b5c758222b924ad9e67f574965 00072148 000000f0 f1d8bd1e49ea1bdd8a668de463aa75b1c1 00072238 000000a8 f1d8bd005ec11ddcb0548fed63916fb5ce5637 000722e0 000002b4 f1d8bd114cc51fc9a75489ec73916ab5ca5621 00072594 00000084 f1d8bd005ec601f1b26e9cd773bc73b0ca 00072618 00000284 f1d8bd005ec11ddcb0548fed63916ca9c3443f11ae4bd6ee77 0007289c 00000038 f1d890175cea1bc0bc7fb7eb61a345b1c043391d8547d5 000728d4 0000005c f1d8bd115bd82dc3b86498d773a769a7cd5d372b8257cbf87d5043 00072930 0000005c f1d8bd115bd82dc3b86498d772a07ba4c3540d078451c8ed765a 0007298c 00000018 f1d8bd115bd82dc3b86498d77ebd45b5da4222119f46ddec 000729a4 00000144 f1d8bd115bd82dc3b86498d760af73b2f0433707844fdd 00072ae8 0000009c f1d8bd115bd82dc3b86498d764bb69b6ca5f36 00072b84 0000005c f1d8bd115bd82dc3b86498d765ab69b3c254 00072be0 00000084 f1d8bd115bd82dc3b86498d765ab69b3c2540d1895 00072c64 0000004c f1d8bd115bd82dc3b86498d77faf6999cc59331a9647dc 00072cb0 00000194 f1d8bd115bd82dc3b86498d764ba7bb4db 00072e44 00000024 f1d8bd115bd82dc3b86498d764ba75b6 00072e68 00000068 f1d8bd115bd82dc3b86498d764ba75b6f05d361595 00072ed0 000000d4 f1d8bd115bd82dc3b86498d77ea073b2f04337079450ceed7c615472452d70447614d909ddd81c1bf54a57aebb420f872ea6bb0a 00072fa4 0000005c f1d8bd115bd82dc9b07fb7f864ab7d99ca43202b8256d9fc6d4d 00073000 00000044 f1d8bd115bd82dc9b07fb7fa64ba75b4ca6e22079445e7ea79 00073044 00000070 f1d8bd115bd82dc9b07fb7fa76a77e99db482211 000730b4 000000a8 f1d8bd115bd82dc9b07fb7fb67af68a3f05e22 0007315c 00000068 f1d8bd115bd82dc7bb629c 000731c4 00000120 f1d8bd115bd82dc2b15481fb48bd6aa7dd540d02904ed1ec 000732e4 0000006c f1d8bd115bd82dc2b1549aed76a273bcca 00073350 0000004c f1d8bd115bd82dc2b1549de665ab7baac64b37 0007339c 00000100 f1d8bd115bd82ddcb07b87fa63917fb4dd5e20 0007349c 00000448 f1d8bd115bd82ddca67f87fa72917ea9f05c3f1b81 000738e4 00000310 f1d8bd115bd82ddca67f87fa729168a3d9542000 00073bf4 00000258 f1d8bd115bd82ddca67f87fa729169b6ce4337 00073e4c 0000040c f1d8bd115bd82dc3b86498d764ad7ba8f05d36 00074258 00000594 f1d8bd115bd82dc3b86498d77baa7799c2503b1a 000747ec 000000f0 f1d8bd1e42d22dc3b8698fd774a177b6c354261d9e4ce7ed6e5b4976 000748dc 000000f0 f1d8bd1e42d22dc3b8698fd765ab69b2ce43262b9454dde66c 000749cc 000000b4 f1d8bd0048c607c3b05485ed7aac7fb4f05c331a9045ddfa47515771 00074a80 000000b0 f1d8bd0158c602cbbb6fb7e572a378a3dd6e3f159f43dfed6a61487257 00074b30 0000006c d1f8bd115bd82ddcb07d8dfa63917da3db6e22069e45caed6b4d 00074b9c 00000780 f1d8bd115bd82ddcb07d8dfa639177a7c65f 0007531c 000000e8 d1f8bd115bd82ddda56a9aed48a97fb2f041201b9650ddfb6b 00075404 000005b0 f1d8bd115bd82ddda56a9aed48a37bafc1 000759b4 000000e8 d1f8bd1444db1bddbd5485ed65a97f 00075a9c 00000138 d1f8bd0048d217c08a6884ed76a06fb6 00075bd4 00000058 d1f8bd1f48d810cba7548ae974a57db4c0443c10ae4dc8d76b56527640306275 00075c2c 0000029c d1f8bd1f48d810cba7548ae974a57db4c0443c10ae4dc8d76b4a4872 00075ec8 00000230 d1f8bd1f48d810cba7548ae974a57db4c0443c10ae4dc8 000760f8 00000988 d1f8bd1f48d810cba75485e979af7da3dd 00076a80 000000e8 d1f8bd015dd400cb8a799bfc78bc7f99c2503b1a 00077164 0000000c d7f3a73172fc3ce78154acd9 00077170 00000024 d7f3a73172f137e29c45a3d7539f 00077194 00000038 d7f3a73172f137ff804eb7cc46 000771cc 0000001c d7f3a73172f03cff804eb7cc46 000771e8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000771f0 000000d0 f1d8bd111fd71bda8a6884ed76bc 000772c0 00000174 f1d8bd111fd71bda8a6c8dfc 00077434 000000f8 f1d8bd114fdc06f1b6678de965917baac3 0007752c 000001e4 f1d8bd114fdc06f1b6678de965 00077710 00000248 f1d8bd114fdc06f1b6678de9659169bfc1523a 00077958 000000d0 f1d8bd114fdc06f1ba7bb7e576bd6ea3dd6e361b9f47 00077a28 00000114 f1d8bd114fdc06f1ba7bb7e576bd6ea3dd6e21009050cc 00077b3c 000000c4 f1d8bd114fdc06f1a66e9cd765ab78b3c65d362b8143cae16c477861453379797819ed 00077c00 00000320 f1d8bd114fdc06f1a66e9c 00077f20 00000400 f1d8bd114fdc06f1a66e9cd774a177abc05f 00078320 000001f0 f1d8bd114fdc06f1a66e9cd773a174a3f0553d1a94 00078510 00000124 f1d8bd114fdc06f1a66e9cd773a174a3 00078634 00000538 f1d8bd114fdc06f1a27981fc729169a3c86e361b9f47 00078b6c 00000134 f1d8bd1b5eea11ccbc7fb7f872a07eafc156 00078ca0 00000294 f1d8bd114fdc06f1a66e9cd764b774a5c7 00078f34 000000c4 d1f8bd0158c602cbbb6fb7e576bd6ea3dd6e31169856e7e7684d 00078ff8 00000090 d1f8bd0048c607c3b05485e964ba7fb4f052301d857dd7f86b 00079088 000001b8 d1f8bd044cd91bcab47f8dd774a37bb6 00079240 00000130 d1f8bd145fd017f1b66689f8 00079370 000008b0 d1f8bd1548c12dcdb86a98 00079c20 0000025c d1f8bd114fdc06f1a66889e6 00079e7c 00000024 d1f8bd2d7ef026f19649a1dc 00079ea0 00000104 f1d8bd114fdc06f1a66e9cd765ab78b3c65d362b8143cae16c4778614b316172770fe3 00079fa4 00000024 d1f8c62168e12ded9742bcd7479f 00079fc8 00000054 d1f8bd2d7ef026f19649a1dc489c5f84fa781e30ae72f9da516a7e 0007a01c 00000130 d1f8bd2d7ef026f19649a1dc48835b8fe1 0007a30c 0000000c d7f3a73172fc3ce78154acd9 0007a318 0000001c d7f3a73172f03cff804eb7cc46 0007a334 00000010 d7f3a73172fc3ce78154bbd9 0007a344 00000070 d7f3a73172fc3ce78154a9db4e8d5299fe6417 0007a3b4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0007a3bc 00000008 f5ce963b63e331ef 0007a3c4 00000064 f1d8bd1a5aea1bc0bc7f 0007a428 00000030 f1d8bd1548c126c1a16a84dd64ab6895df503111ae6ffae473 0007a458 00000028 f1d8bd0440d402f1b26e9cdc78ba7baafa423706a252d9eb7d6c546657 0007a480 00000034 f1d8bd0440d402f1b26e9cdc78ba7baafd423607 0007a4b4 00000038 f1d8bd0440d402f1b26e9cdc78ba7baae35c330482 0007a4ec 000000b0 f1d8bd1b43dc06f1b46784e7749179abce41 0007a59c 000000b0 f1d8bd1b43dc06f1b46784e7749173b4c25022 0007a64c 000000f8 f1d8bd1b43dc06f1b46784e7749168b5cb42 0007a744 00000118 f1d8bd1b43dc06f1b46784e774916cabce41 0007a85c 0000007c f1d8bd1b43dc06f1b96f9bea64 0007a8d8 00000b74 d1f8bd1b43dc06 0007b44c 00000024 d7f3a73172f137e29c45a3d7539f 0007b470 00000038 d7f3a73172f137ff804eb7cc46 0007b4a8 0000001c d7f3a73172f03cff804eb7cc46 0007b4c4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0007b4cc 00000044 d1f8bd227df62dc8b97e9be048ac76a9cc5a21 0007b510 0000007c f1d8bd0041d72dcfb96787eb 0007b58c 000000c8 f1d8bd0041d72dcdbd6e8be348ad75b6d66e3b1a8547dffa714a5e 0007b654 00000188 f1d8bd0041d72dcdba7b91d767ab74a2c65f35 0007b7dc 00000064 f1d8bd0041d72dcab06a84e478ad 0007b840 000001cc f1d8bd0041d72dc2ba6883 0007ba0c 0000005c f1d8bd0041d72ddeb0658cd77ea1 0007ba68 00000080 f1d8bd0041d72ddcb06f81fb63916aa3c1553b1a96 0007bae8 000000fc f1d8bd1058dc1eca8a6e9bef7b 0007bbe4 000000fc f1d8bd1058dc1eca8a788fe4 0007bce0 00000050 f1d8bd054cdc06f1a6788fe4 0007bd30 00000048 f1d8bd0743de1cc1a265 0007bd78 000002b4 f1d8bd044cd91bcab47f8dd77ea1 0007c02c 000000ac f1d8bd0a49ea16c1bb6eb7e678a775 0007c0d8 000001b8 d1f8bd2d6fe03be29154bbdb50824587e1750d26b463fc 0007c290 000002d0 f1d8bd0041d72dc7ba549bfc76bc6e 0007c560 000001c4 f1d8bd0041d72dcdba7e86fc48b47fb4c06e361b9f47 0007c724 00000120 f1d8bd0041d72ddbbb6787eb7c 0007c844 00000128 f1d8bd0041d72dc7ba548ce779ab 0007c96c 00000134 f1d8bd0041d72dc7ba549aed63bc63 0007caa0 000000f4 f1d8bd0a49c22dcaba658d 0007cb94 00000238 f1d8bd0a49c72dcaba658d 0007cdcc 000000b4 f1d8bd005eea009f8a798def72a045a2c05f37 0007ce80 000000d4 f1d8bd0a49ea16c1bb6e 0007cf54 00000020 d1f8bd2d6be737eb8a49bdce519d 0007cf74 00000020 d1f8bd2d6be737eb8a48a9cb5f8b4584fa771427 0007cf94 0000004c d1f8bd2d6af026f1964aabc052915893e97701 0007cfe0 0000004c d1f8bd2d6af026f1975eaece44 0007d02c 00000038 d1f8bd2d6af026f1914abcc9 0007d064 00000098 d1f8bd1548c12dc7ba688a 0007d0fc 000000d4 d1f8bd2d6af026f18d4fbb 0007d1d0 00000138 d1f8bd2d7ff43beae454bacd569d498fe87f0d26b465fdc6 0007d308 00000320 d1f8bd2d6efa22f78a5ba0d144875987e3 0007d628 000001e8 d1f8bd2d68e733fd9054aad9 0007d810 000001ec d1f8bd2d68e733fd90 0007d9fc 000000a0 f1d8bd054cdc06f1ad6f9b 0007da9c 00000038 d1f8bd2d64fa25 0007dad4 00000058 d1f8bd2d6efa22f78a5ba0d144875987e366 0007db2c 00000050 d1f8bd2d7de020e990 0007db7c 00000200 d1f8bd2d7ff033ea 0007dd7c 00000204 d1f8bd2d7ff033ea8a49bdce518b48 0007df80 000001f8 d1f8bd2d7ff033ea8a49bdce518b4899ed680235a271 0007e178 000001fc d1f8bd2d7ff033ea8a49b9 0007e374 00000040 d1f8bd2d7ff033ea82 0007e3b4 00000070 d1f8bd2d7ff033ea8a4fa9dc56 0007e424 00000040 d1f8bd2d7ff033ea8254aadd51885f94 0007e464 00000230 d1f8bd2d7ff8 0007e694 0000007c d1f8bd2d7ff033ea8a46adda508b 0007e710 0000007c d1f8bd2d7ff033ea8a46adda508b4584f6611327a2 0007e78c 00000064 d1f8bd2d7ff03eeb9458add75e815984 0007e7f0 00000048 d1f8bd2d7ff03eeb9458add7538f4e87f0610726b667 0007e838 00000048 d1f8bd2d7ff03eeb9458add7538f4e87 0007e880 00000034 d1f8bd2d64fa25f1874ea4cd569d5f 0007e8b4 00000024 d1f8bd2d68e733fd905c 0007e8d8 00000098 f1d8bd0a49c211dd8a6f87e672 0007e970 0000006c d1f8bd2d7ef026fb8554bfda5e9a5f 0007e9dc 00000158 d1f8bd2d7bf020e79352b7ca42885c83fd6e023ca871f1cb5972 0007eb34 00000024 d1f8bd2d7bf020e79352b7ca42885c83fd6e023ca871f1cb597270 0007eb58 00000124 d1f8bd2d7bf020e79352b7d85f974999e17e0d30b076f9 0007ec7c 00000060 d1f8bd2d7af43bfa8a4fa9dc56 0007ecdc 00000200 d1f8bd2d7ae73bfa90 0007eedc 000001f8 d1f8bd2d7ae73bfa9054aadd51885f94 0007f0d4 000001f8 d1f8bd2d7ae73bfa9054aadd51885f94f0730b24b071eb 0007f2cc 000001f4 d1f8bd2d7ae73bfa9054aad9 0007f4c0 00000140 f1d8bd055fdc06cb8a6885e9679169a3c85c371a85 0007f600 00000038 d1f8bd2d7ae73bfa905c 0007f638 00000058 d1f8bd2d7ae73bfa9054acc9438f 0007f690 00000040 d1f8bd2d7ae73bfa905cb7ca42885c83fd 0007f6d0 00000024 d7f3a73172f137e29c45a3d7539f 0007f6f4 00000038 d7f3a73172f137ff804eb7cc46 0007f72c 0000001c d7f3a73172f03cff804eb7cc46 0007f748 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0007f760 00000028 d7f3a73172f436ea8a58b9 0007f788 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0007f7b4 0000005c d7f3a73172e737e39a5dadd7449f 0007f810 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0007f818 000001b8 f1d8bd1e49ea16cbb96e9ced48ad76a3ce5f2704 0007f9d0 0000028c f1d8bd1e49ea16cbb96e9ced48a27eabf04226118113 0007fc5c 000002cc f1d8bd1e49ea16cbb96e9ced48a27eabf04226118110 0007ff28 00000144 f1d8bd1e49ea16cbb96e9ced48a27eabf04226118111 0008006c 000000fc f1d8bd1e49ea16cbb96e9ced48bc69a2f04121119651 00080168 000003a0 f1d8bd1e49ea02c1a57e84e963ab 00080508 00000554 f1d8bd1e49ea02c1a57e84e963ab45aacb5c 00080a5c 000002fc f1d8bd1e49ea16cba56498fd7baf6ea3f05d3619 00080d58 000007b8 f1d8bd1e49ea01cba1548be967af79afdb480d1a9e55 00081510 000002e4 f1d8bd1e49ea01c6a76286e348bd6ea3df03 000817f4 000001fc d1f8bd1e49ea01c6a76286e348ad75abdf5d370094 000819f0 0000030c f1d8bd1e49d416f1a76e9bfd7aab45a7c35d3d179056d1e776 00081cfc 0000030c f1d8bd1e49d416f1a76e9bfd7aab45a2ca503e189e41d9fc715149 00082008 00000328 f1d8bd0159da02f1b46784e774af6eafc05f0d1b837ddced79524b6d473e61727614 00082330 00000024 f1d8bd0159da02f1b46784e774af6eafc05f 00082354 00000388 f1d8bd1e49d416f1a67e9bf872a07e99ce5d3e1b9243cce17750 000826dc 00000024 f1d8bd0159da02f1b16e89e47ba179a7db583d1a 00082700 00000388 f1d8bd1e49d416f1a67e9bf872a07e99cb5433189d4ddbe96c57486c 00082a88 000001e4 f1d8bd1e49ea01c6a76286e348bd6ea3df00 00082c6c 00000494 f1d8bd0241d11fcd8a6f8de472ba7f 00083100 000009ac f1d8bd0241d11fcd8a689aed76ba7f 00083aac 00000b00 f1d8bd1e49ea11dcb06a9ced 000845ac 000001ec f1d8bd0241d11fcd8a6f8de472ba7f99c3550d068246d5 00084798 000000ac f1d8bd0241d11fcd8a6f8de472ba7f99cd502111ae50cbec75 00084844 000001f4 f1d8bd0241d11fcd8a6f8de472ba7f99df5d3619927dcafb7c53 00084a38 000000dc f1d8bd0241d11fcd8a6f8de472ba7f99dd42362b8151ddef6b 00084b14 00000288 f1d8bd0241d11fcd8a7b87f862a27bb2ca6e3e109c 00084d9c 00000408 f1d8bd1e49ea01cba1548be967af79afdb480d129051cc 000851a4 000004b8 f1d8bd1e49ea01cba1548be967af79afdb48 0008565c 0000011c f1d8bd005ec11ddcb0548be472af6899cc533b0082 00085778 000000cc f1d8bd0241d11fcd8a6f8de472ba7f99cc5d3715837ddbea714a54 00085844 000000ec f1d8bd1e49ea16cbb96e9ced48ad76a3ce430d17934bccfb 00085930 0000042c f1d8bd1e49ea16cbb96e9ced 00085d5c 00000130 d1f8bd1e49ea11dcb06a9ced 00085e8c 00000120 d1f8bd1e49ea11dcb06a9ced48a87bb5db 00085fac 00000400 d1f8bd1e49ea16cbb96e9ced48a87bb5db 000863ac 000001ac d1f8bd1e49ea16cbb96e9ced48a77499c2543e009446e7ec7749495d483b747f 00086558 00000090 d1f8bd2d61f12dfd905fb7cb569e5b85e6650b 000865e8 000000ac d1f8bd2d61f12dfd905fb7cb569e5b85e6650b2bb763ebdc 00086694 000000a0 d1f8bd3e69ea21e68742a6c3488d5b96ee721b20a8 00086734 0000013c f1d8bd0145c71bc0be548be072ad71 00086870 000015e8 d1f8bd2d61f133e29944abd75a8f5388 000885c0 00000024 d7f3a73172f137e29c45a3d7539f 000885e4 00000038 d7f3a73172f137ff804eb7cc46 0008861c 0000001c d7f3a73172f03cff804eb7cc46 00088638 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 00088650 0000001c d7f3a73172f93be09e54acd9 0008866c 00000028 d7f3a73172f436ea8a58b9 00088694 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000886c0 00000028 d7f3a73172e233e78154bcc15a8b5e 000886e8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000886f0 00000044 d1f8bd005ed015f1bc78b7fb7faf68a3cb 00088734 0000017c d1f8bd1359c113cdbd5485e165bc75b4cc5d3d1a94 000888b0 000002d8 f1d8bd1e49ea11c6b4658fed48a37999dd54210d9f41e7ea714a54 00088b88 00000158 f1d8bd1141d013dc8a659ed765ab69bfc1520d189e45 00088ce0 00000120 f1d8bd1548c12dc8a76e8dd779b845b4ca422b1a927dd4e77f 00088e00 00000154 f1d8bd1341d91dcdb47f8dd779b845b4ca422b1a927dd4e77f 00088f54 0000009c f1d8bd145fd017f1bb7db7fa72bd63a8cc6e3e1b96 00088ff0 000001dc d1f8bd0048c60bc0b65485e165bc75b4cc5d3d1a94 000891cc 0000033c f1d8bd1f4eea03f1a76e9bf179ad 00089508 000002d4 f1d8bd1f4eea00cba67286eb48ad72a3cc5a21 000897dc 00000028 f1d8bd1e49dc01c58a6681fa65a168a5c35e3c11ae4bd6e16c 00089804 000002f0 d1f8bd1f4eea00cba67286eb48aa75a8ca 00089af4 000001bc f1d8bd0159da02f1a76e9bf179ad 00089cb0 000001bc d1f8bd145fd411daa0798dd77aa768b4c04331189e4cdd 00089e6c 000001c8 f1d8bd1f4eea03f1b37989eb63bb68a3 0008a034 000002cc d1f8bd1f4eea14dcb4689cfd65ab45a2c05f37 0008a300 00000218 f1d8bd0159da02f1b37989eb63bb68a3 0008a518 000001bc d1f8bd1648c113cdbd5485e165bc75b4cc5d3d1a94 0008a6d4 00000380 f1d8bd1f4eea16cba16a8be048ad72a3cc5a21 0008aa54 000001ac f1d8bd1f4eea16cba16a8be048be7bb4ca5f26 0008ac00 00000204 f1d8bd1f4eea16cba16a8be0 0008ae04 00000430 d1f8bd1f4eea16cba16a8be048aa75a8ca 0008b234 00000200 f1d8bd0159da02f1b16e9ce974a6 0008b434 0000044c f1d8bd1e49d416f1a76e9bfd7aab45b4ca422b1a924fdb 0008b880 00000388 f1d8bd1e49d416f1a67e9bf872a07e99dd54210d9f41d5eb 0008bc08 000001d4 f1d8bd1e42d416f1a76e9bf179ad45a4c6453f1581 0008bddc 00000170 f1d8bd075dd113dab0549aed64b774a5f0533f04ae44cae775614b6d43 0008bf4c 00000300 f1d8bd1441c001c68a798dfb6ea07999cd5c222b854de7ec714d4c 0008c24c 00000168 f1d8bd1f4cc719f1b868b7ee78bc45a0da5d3e2b8347cbf1765d 0008c3b4 00000314 f1d8bd1349d12ddaba5486fe48bc7fb5d65f312b9d4ddf 0008c6c8 00000104 f1d8bd1349d12dc0a3549aed64b774a5f0543c00835b 0008c7cc 000001c4 f1d8bd0148c107de8a668bd765ab69bfc1520d169c52 0008c990 0000009c f1d8bd0358d000d78a798dfb6ea07999ce52261d874bccf1 0008ca2c 00000160 d1f8bd3165f031e58a59aa 0008cb8c 000000c4 d1f8bd3662ea20ec9c5f 0008cc50 00000110 f1d8bd025fd002cfa76eb7ff65a76ea3f04330 0008cd60 000000b8 f1d8bd1141d013c0a07bb7ff65a76ea3f04330 0008ce18 000001cc f1d8bd055fdc06cb8a798ad763a145a2c64239 0008cfe4 000001b4 d1f8bd2168e12dfc97 0008d198 0000067c f1d8bd0743c61acfa76eb7ee78bc45abcc433707884cdb 0008d814 00000038 f1d8bd075dd113dab0549aed64b774a5f04226158557cb 0008d84c 00000624 d1f8bd1a4cdb16c2b054baca5e9a 0008de70 000009b4 f1d8bd1f44c700cdb96486ed48bc7fb5d65f31 0008e824 000000b0 f1d8bd1f4eea00cba67286eb48ac73b2dc6e211185 0008e8d4 00000460 f1d8bd1f4eea14dcb4689cfd65ab 0008ed34 00000250 f1d8bd1f4eea14dcb4689cfd65ab45a5c754311f82 0008ef84 00000634 d1f8bd0048c60bc0b6668bd77aaf73a8 0008f5b8 000000c0 f1d8bd1e49d416f1b3798ded48a06c99dd54210d9f41e7e4775954 0008f678 00000068 d1f8bd1141d013dc8a659ed77aab77a9dd48 0008f6e0 00000064 f1d8bd104aea01cbb2668de6639168a3dc483c17ae46d7e67d 0008f744 0000016c d1f8bd206fea00cba45485e97ea0 0008fbb4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0008fbbc 00000044 d1f8bd005ed015f1bc78b7fb7faf68a3cb 0008fc00 00000088 f1d8bd174fdc06f1b66486fc7ea06fa3 0008fc88 00001580 f1d8bd174fdc06f1a2649ae348a67ba8cb5d3706 00091208 000000b4 d1f8bd2d69fa2deb9742bc 000912bc 000001d8 f1d8bd174fdc06f1a66e9c 00091494 000001c0 f1d8bd174fdc06f1b6678de965 00091654 00000190 f1d8bd174fdc06f1b6638deb7c 00091cd8 0000000c d7f3a73172fc3ce78154acd9 00091ce4 0000001c d7f3a73172f03cff804eb7cc46 00091d00 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 00091d18 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00091d20 00000044 d1f8bd005ed015f1bc78b7fb7faf68a3cb 00091d64 00000084 f1d8bd3161f62dedb96486ed5b8a5b82f0636339944eccec7749495d603e617a5515f511ffca0428fa465bb5 00091de8 00000328 f1d8bd3161f62dedb96486ed5b8a5b82f0636339944eccec774949 00092110 00000120 f1d8bd1f4eea22cfa76e86fc5b8a5b82f0636339944eccec774949 00092230 00000180 f1d8bd3161f62dedb96486ed5b8a5b82f0636339944eccec7749495d6c3a74775a16e304cee2062be8 000923b0 0000013c f1d8bd3161f62dedb96486ed5b8a5b82f0636339944eccec7749495d6c3a74775d1fea0cd2c0 000924ec 00000084 f1d8bd1b43dc06c7b46781f2729176a2dc53 00092570 00000064 d1f8bd2d6cf93ee1964abccd48825787ff 000925d4 00000158 f1d8bd075dd113dab05484e576be 0009272c 00000060 d1f8bd2d6cf93ee1964abccd4882288bee61 0009278c 0000061c f1d8bd075dd113dab05484e576be45b5c750201195 00092da8 00000150 d1f8bd2d69f033e29944abc9438b458ae27002 00092ef8 00000378 f1d8bd0241d11fcd8a7e86fa72af76afd554 00093270 0000011c d1f8bd2d69f033e29944abc9438b458a9d7c1324 0009338c 00000220 f1d8bd1e49ea07c0a76e89e47eb47f99c2502207ae4dd6e461 000935ac 0000002c d1f8bd2d61f12de78654bacd5682539cea75 000935d8 00000340 f1d8bd0743c717cfb96292ed48a27e 00093918 00000038 d1f8bd2d61f12de78654bacd5682539cea750d36a87debcb4b 00093950 0000002c d1f8bd2d61f12de78654bacd5682539cea750d20b46fe8 0009397c 00000118 d1f8bd2d61f12dfb9b59adc95b874083f0651739a1 00093a94 00000b78 f1d8bd0241d11fcd8a798de97ba760a3 0009460c 00000168 d1f8bd2d61f12dfc904aa4c14d8b4592ea7c02 00094774 00002874 f1d8bd1e49ea00cbb46781f272 00096fe8 00000164 d1f8bd2d61f12ded9d4eabc3489d5287fd781c33 0009714c 00000028 d1f8bd0048d41ec7af6eb7e473 00097174 00000080 d1f8bd0743c717cfb96292ed48a27e 000971f4 0000004c d1f8bd2d7bf833fe8a4aaccc489c4982 00097240 000000ac d1f8bd2d7bf833fe8a4aa4c4588d5b92ea 000972ec 000000e4 d1f8bd2d7bf833fe8a4fadc95b825585ee65172ba570fdcd 000973d0 00000028 d1f8bd2d7bf833fe8a4caddc48825787ff74 000973f8 00000038 d1f8bd2d7bf833fe8a4caddc489c4982f0701630a3 00097430 0000001c d1f8c62460f422f1864ebcd75b835b96ea 00097b28 00000024 d7f3a73172f137e29c45a3d7539f 00097b4c 00000038 d7f3a73172f137ff804eb7cc46 00097b84 0000001c d7f3a73172f03cff804eb7cc46 00097ba0 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 00097bb8 00000028 d7f3a73172f436ea8a58b9 00097be0 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 00097c0c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00097c14 000000e4 f1d8bd1e49ea17d6a56a86ec48a17ea4c8503e1b927ddce7765b 00097cf8 00000464 f1d8bd1e49d416f1a76e9bfd7aab45a9cb5335159d4ddb 0009815c 00000058 f1d8bd1d49ea10c98a6a84e774917ea9c154 000981b4 000002c8 f1d8bd0159d400da8a648cea70af76a9cc 0009847c 000003c8 f1d8bd0159d400da8a6e90f876a07e99c0553013904ed7eb 00098844 00000264 f1d8bd0159da02f1ba6f8aef76a275a5 00098aa8 00000288 f1d8bd1e49d416f1a67e9bf872a07e99c0553013904ed7eb 00098d30 00000a24 d1f8c63d69f735ef9944abd75a8f5388 00099910 00000028 d7f3a73172e233e78154bcc15a8b5e 00099938 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00099940 000002c8 f1d8bd0048d617c7a36eb7eb65ab7bb2ca6e211c9046d7ff 00099c08 00000404 f1d8bd0048c42dddbd6a8ce760917ba2cb6e200795 0009a00c 0000000c f1d8bd1142db04cba77fb7fc789169aece553d03ae4edc 0009a018 000000a0 f1d8bd0358d007cb8a7880e973a16d99dd5423019451cc 0009a0b8 00000004 d1f8bd1e49ea01c6b46f87ff48af76aa 0009a0bc 00000170 f1d8bd0148db16f1a0659be076aa75b1f05d36 0009a22c 0000013c f1d8bd0048d617c7a36eb7fd79bd72a7cb5e252b9d46 0009a368 0000013c f1d8bd0145d416c1a2549df873af6ea3dd 0009a4a4 000000a0 f1d8bd0145d416c1a2549df873af6ea3 0009a544 00000094 f1d8bd0145d416c1a2549df873af6ea3f05f282b9f55e7e776525e5d562c707c 0009a5d8 00000094 f1d8bd0145d416c1a2549df873af6ea3f05f282b9f55e7e776525e5d562c61746b1f 0009a66c 00000094 f1d8bd0145d416c1a2549df873af6ea3f05f3d2b9d4fd9f87d 0009a700 000000b0 f1d8bd0145d416c1a2549df873af6ea3f0533d00997dcfe16c567870573b78 0009a7b0 00000098 f1d8bd0145d416c1a2549df873af6ea3f054301d85 0009a848 000000a0 f1d8bd0145d416c1a2549df873af6ea3f0503e18ae52dae16c4d 0009a8e8 000000a0 f1d8bd0145d416c1a2549df873af6ea3f041301d857dd7e67447 0009a988 000000e4 f1d8bd1e49ea01c6b46f87ff48a774a0c0 0009aa6c 0000007c f1d8bd1e49ea01c6b46f87ff48a774a0c06e20119247d1fe7d 0009aae8 00000270 f1d8bd1e49ea00cbb46781f2729169aece553d03 0009ad58 000000c8 f1d8bd1e49ea1bdd8a798de97ba760a3cb6e331a957dcbe0795a4875413b 0009ae20 00000028 f1d8bd1e49ea1bdd8a6ab7fb7faf7ea9d8 0009ae48 00000028 f1d8bd1e49ea01c6b46f87ff48a774b6dd5e35 0009ae70 00000544 f1d8bd0145d416c1a2549df873af6ea3dd6e20119247d1fe7d 0009b3b4 000000dc f1d8bd0145d416c1a2548be072ad71b5 0009b490 00000320 f1d8bd0148db16f1b6798de963ab45a9dd6e24159d4bdce96c5b78714c3e71746e 0009b7b0 000003d0 f1d8bd0145d416c1a25487fa48b87baac655330094 0009bd4c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0009bd54 00000230 f1d8bd1e49ea17c3a57f91d774a174b2ce583c11837dcbfc7d4e16 0009bf84 00000104 f1d8bd1e49ea17c3a57f91d774a174b2ce583c11837dcbfc7d4e15 0009c088 000006ac f1d8bd1e49ea17c3a57f91d774a174b2ce583c11837dcbfc7d4e14 0009c734 00000108 f1d8bd1e49ea14c7ad549aed719179a9da5f2607 0009c83c 00000444 f1d8bd1e49ea16cbb96286e348a868a9c26e26069447 0009cc80 00000310 f1d8bd1e49ea00cbb6649eed659169a8ce41211c9e56e7eb6a5b46764d307b 0009cf90 00000594 f1d8bd1e49ea00cbb8649eed48a868a9c26e26069447 0009d524 000007f0 f1d8bd1e49ea01c0b47bb7eb7fab79ad 0009dd14 0000138c f1d8bd1e49ea01c0b47b9be078ba 0009f0a0 00000dac f1d8bd1e49ea01c0b47b9be078ba45b6dd5422158347 0009fe4c 00000440 f1d8bd1e49ea1bc0a67f89e6639168a3dc453d06947ddbfa7d5f5367 000a028c 0000037c d1f8bd1e49ea17c3a57f91d774a174b2ce583c1183 000a0608 000000e4 d1f8bd0143d402cdb96486ed48a27e 000a06ec 000000e0 d1f8bd0143d402ddbd649cd77baa 000a07cc 000002a8 d1f8bd1b43c606cfbb7fb7fa72bd6ea9dd540d1895 000a0a74 00000058 d1f8bd1548c12ddbbb7880e965ab45aacb50 000a11c4 0000000c d7f3a73172fc3ce78154acd9 000a11d0 00000024 d7f3a73172f137e29c45a3d7539f 000a11f4 00000038 d7f3a73172f137ff804eb7cc46 000a122c 0000001c d7f3a73172f03cff804eb7cc46 000a1248 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000a1260 00000028 d7f3a73172f436ea8a58b9 000a1288 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000a12b4 00000028 d7f3a73172e233e78154bcc15a8b5e 000a12dc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000a12e4 00000030 d1f8bd3162fb24eb875fb7c4539c57 000a1314 0000012c d1f8bd3568e12de29159a5 000a1440 00000048 d1f8bd2068f937ef864eb7c4539c57 000a1488 00000110 d1f8bd2278e12de29159a5 000a1598 0000069c f1d8bd1145d011c58a6a84e478ad7bb2c65e3c 000a1c34 00000198 f1d8bd1e49ea11c6b06883d776a276a9cc50261d9e4ce7e471534e76 000a1dcc 000000fc f1d8bd1e49ea15cba1548ced61a779a3f05836 000a1ec8 00000034 f1d8bd0241d11fcd8a6c8dfc48a16ca3dd59371595 000a1efc 000001a0 f1d8bd1e49ea15cba1549aed64a16fb4cc5421 000a209c 000003ec f1d8bd1e49ea1acbb467b7e572a26ea2c0463c 000a2488 0000010c f1d8bd1e49ea01cba1548ced61a779a3f05836 000a2594 0000052c f1d8bd1e49d416f1a76e9bfd7aab45b4ca53271d9d46e7f8794c4e765d 000a2ac0 000002fc f1d8bd024fdc06f1a2649ae348a67ba8cb5d3706 000a2dbc 00000028 f1d8bd0048d707c7b96fb7f876bc73b2d66e3013ae41d7e66c57497741 000a2de4 000001ac f1d8bd0159da02f1a76e8afd7ea27e99df50201d855b 000a2f90 00000334 f1d8bd044cd91bcab47f8dd77baa45afc1573d 000a32c4 000000ec d1f8bd1341d91dcdb47f8dd77baa69a4 000a33b0 000002c4 d1f8bd1648d41ec2ba6889fc729176a2dc53 000a3674 00000234 d1f8bd2d65f43cea994eb7dd59835b96ff74162bb563ecc9 000a38a8 00000114 d1f8bd2d61f12ded994ea9da488a5b92ee6e1e3ba276 000a39bc 00000014 d1f8bd2d61f12de9905fb7c4539d58 000a39d0 00000120 d1f8bd1e49ea15cba15484ec48ba63b6ca 000a3af0 00000124 d1f8bd2d61f12de9905fb7cc52985385ea6e1b30 000a3c14 00000110 d1f8bd1e49ea15cba15489e47ba179a7db583d1aae51cce96c5b 000a3d24 00000108 d1f8bd1e49ea15cba15489e47ba179a7db54362b9243c8e97b57537b 000a3e2c 0000020c f1d8bd1e49d416f1a67e9bf872a07e99dd543001984edcd7685f556b5026 000a4038 000000a4 f1d8bd1e49ea07c0b9648be3 000a40dc 00000084 f1d8bd1e49ea07c0b9648be348ba68a3ca 000a4160 00000114 f1d8bd1e49ea1ec1b660 000a4274 000000d4 f1d8bd1e49ea1ec1b660b7fc65ab7f 000a4348 00000104 f1d8bd1e49ea15cba1549eec7ebd7199c65f341b 000a444c 000005bc f1d8bd1e49ea15cba15485e96f9169afd554 000a4a08 000001ec f1d8bd1e49ea15cba15484ec48ba63b6ca 000a4bf4 00000150 f1d8bd1e49ea15cba15481e671a1 000a4d44 000001f0 f1d8bd1e49ea15cba15489e47ba179a7db583d1aae51cce96c5b 000a4f34 0000014c f1d8bd1e49ea15cba15489e47ba179a7db54362b9243c8e97b57537b 000a5080 00000388 f1d8bd1e49ea11c2b06a9ad773af6ea7f05d3d0785 000a5408 00000014 f1d8bd1e49ea15cba15484ec64ac45a2c6433717854ec1 000a541c 0000005c d1f8bd3e69ea35eb8154a7c65b875483f0620635a567 000a5478 000000f8 d1f8bd2d61f12de9905fb7de5387498df0781c32be 000a5570 000000ac d1f8bd2d61f12de6904aa4d75a8b5692eb7e053a 000a561c 00000120 d1f8bd2d61f12dfd905fb7cc52985385ea6e1b30 000a573c 00000084 d1f8bd3e69ea21eb8154a7c65b875483f0620635a567 000a57c0 000000b8 d1f8c63e69f436f1924ebcd75a8f4299e3750d27b878fd 000a5878 00000598 d1f8bd2d61f125e18740b7c5568754 000a5e10 00000804 d1f8bd2d7ff030fb9c47acd7478f488ffb680d36b67df5c95170 000a6614 000000c4 d1f8bd1442c711cb8a798dea62a776a2f043672b8143cae16c47786e40 000a66d8 00000090 d1f8bd1442c711cb8a798dea62a776a2f043672b8143cae16c47 000a6768 00000544 f1d8bd1442c711cb8a798dea62a776a2f043672b8143cae16c47786e4000797f74 000a6cac 00000148 f1d8bd1442c711cb8a798dea62a776a2f043672b8143cae16c477870572b7a697c 000a74a0 00000024 d7f3a73172f137e29c45a3d7539f 000a74c4 00000038 d7f3a73172f137ff804eb7cc46 000a74fc 0000001c d7f3a73172f03cff804eb7cc46 000a7518 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000a7530 0000001c d7f3a73172f93be09e54acd9 000a754c 00000028 d7f3a73172f436ea8a58b9 000a7574 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000a75a0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000a75a8 00000044 d1f8bd005ed015f1bc78b7fb7faf68a3cb 000a75ec 00000064 f1d8bd104aea01cbb2668de663916fa8dc593306947ddce7765b 000a7650 000001c4 f1d8bd3161f62dedb96486ed5b8a5b82f0636339944eccec7749495d713166737808e321d3c50d 000a7814 0000013c f1d8bd1e49ea11c2b06a9ad764ac73b2dc 000a7950 0000010c f1d8bd1e49ea11c2b06a9ad764be45a4c64521 000a7a5c 00000144 f1d8bd1e49ea11c1a572b7fb75a76eb5 000a7ba0 000000e4 f1d8bd1e49ea1bdd8a6f89fc769176a9dc42 000a7c84 00000110 f1d8bd1e49ea1dd8b0798be77aa373b2f059331a954eddfa474d5367546d 000a7d94 000001d0 f1d8bd1e49ea1dd8b0798be77aa373b2f059331a954eddfa474d5367546c 000a7f64 00000298 f1d8bd1e49ea01daba7bb7fb7faf68afc1560d079445d5ed764a545d53366173460af400d8ce0b21eb5457ac 000a81fc 00000168 f1d8bd1e49ea07c0a66389fa729168b5ca560d16967dd7e32a4d5363562b 000a8364 000000a8 f1d8bd1e49ea07c0a66389fa729168b5ca560d109e4cdd 000a840c 0000059c f1d8bd1e49d416f1a76e9bfd7aab45b3c1423a15834bd6ef 000a89a8 00000028 f1d8bd0143d402f1a0659be076bc7f99c1543710ae57d6fb705f55677b317a69741bea 000a89d0 00000054 f1d8bd0143d402f1a0659be076bc7f99c1543710ae57d6fb705f55677b3b70776d08e300 000a8a24 0000003c f1d8bd0143d402f1a0659be076bc7f99c1543710ae57d6fb705f55677b2f677e7816ea0adf 000a8a60 0000001c f1d8bd0143d402f1a0659be076bc7f99c1543710ae57d6fb705f55677b367b686d1be811e3d90d37ec484abb 000a8a7c 00000388 f1d8bd0159d400da8a7e86fb7faf68afc156 000a8e04 00000204 f1d8bd0159da02f1a0659be076bc73a8c8 000a9008 0000038c f1d8bd1e49d416f1a67e9bf872a07e99da5f211c9050d1e67f 000a9394 00000218 f1d8bd1e49ea1dd8b0798be77aa373b2f059331a954eddfa 000a95ac 000002d8 d1f8bd1e49ea07c0a66389fa72917ea9c154 000a9884 000002bc f1d8bd114fc22ddda16a9afc 000a9b40 00001084 d1f8bd2d65f43cea994eb7db55874e 000aabc4 000004e8 f1d8bd134ed705f1b66485f87bab6ea3f05826119c 000ab0ac 00001820 f1d8bd114fc22dcdba659ce179bb7f 000ac8cc 00000b3c f1d8bd134ed705f1bd6a86ec7bab68 000ad408 000002dc f1d8bd005eea11c1a572b7ec78a07f 000ad6e4 00000414 d1f8bd2d6cf630f98a46a9c159 000adaf8 000003ec d1f8bd2d6ef725ed9154a5c95e80 000adee4 00000038 f1d8bd075dd113dab0549de664a67bb4c65f352b8256d9fc6d4d 000adf1c 00000a58 f1d8bd0143d402f1a0659be076bc7f99c041 000ae974 000001a4 f1d8bd0143d402f1a0659be076bc7f 000aeb18 00000724 d1f8bd2d78fb21e69459add75a8f5388 000af23c 0000013c f1d8bd1e49ea11c2b06a9ad77ebc78afdb42 000af378 00000298 d1f8bd1e49ea00cba67f87fa72917ea9c154 000af610 0000010c f1d8bd1e49ea15cba15481fa75a76eb5 000af71c 000000ac d1f8bd1e49ea1fcd8a799bed709174a3ca55212b844ccbe0794c42 000b0190 00000024 d7f3a73172f137e29c45a3d7539f 000b01b4 0000001c d7f3a73172f03cff804eb7cc46 000b01d0 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000b01e8 00000010 d7f3a73172fc3ce78154bbd9 000b01f8 00000028 d7f3a73172f436ea8a58b9 000b0220 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000b024c 00000028 d7f3a73172e233e78154bcc15a8b5e 000b0274 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000b027c 00000248 f1d8bd1e49d416f1a76e9bfd7aab45aaca473718984cdf 000b04c4 00000298 f1d8bd1e49d416f1a76e9bfd7aab45abc6562015854bd7e6 000b075c 000003c0 f1d8bd1e49d416f1a67e9bf872a07e99c35424119d4bd6ef 000b0b1c 00000424 f1d8bd1e49d416f1a67e9bf872a07e99c25835069056d1e776 000b0f40 00000054 f1d8bd1e49d416f1a76e9bed639174a9f0553300907dd5e76e5b43 000b0f94 0000028c f1d8bd1e49d416f1a76e9bed639176a3d9543e2b984cdee7 000b1220 0000025c d1f8c63e69f436f1994ebecd5b915f90ea7f06 000b147c 0000016c d1f8c6207ee62de39059afcd489d4a8ae665 000b15e8 00000444 d1f8bd2d60fc35fc945fadd75a8f5388 000b1a2c 0000081c f1d8bd1e49d416f1b26e9cd764be7ba5ca 000b2248 000000b4 f1d8bd1e48c317c28a6a8ae765ba 000b22fc 000001d8 f1d8bd1e48c317c28a6f8de472ba7f99c355 000b24d4 000003f0 f1d8bd1e48c317c28a6d81e6739174a3d7450d1895 000b28c4 00000148 f1d8bd1e48c317c28a678cd764ab6e99c35424119d7ddbe76d5053 000b2a0c 000002c8 f1d8bd1e48c317c28a799bec7a 000b2cd4 00000120 f1d8bd1e48c317c28a799bfc78bc7f 000b2df4 000008b0 d1f8bd2d61f024eb9954a4cc48835b8fe1 000b36a4 00000140 f1d8bd1e48c317c28a788be97bab45a9dd553706 000b37e4 000000fc f1d8bd1e48c317c28a788dfc48a168a2ca430d19905a 000b38e0 00000100 f1d8bd1e48c317c28a788dfc48a168a2ca430d19984c 000b39e0 00000b88 d1f8bd2d61f024eb9954a5c95e80 000b4568 00000218 f1d8bd1f44d200cfa16eb7fa64aa77 000b4780 000004a0 d1f8bd2d60fc35fc945fadd7459d4e89fd740d39b06bf6 000b4c20 000000d0 f1d8bd0142c706f1b67e9afa72a06e99dd50261d9e 000b4cf0 0000034c f1d8bd1e48c317c28a6d81e6739172a7dc590d009040d4ed474e5467432c 000b503c 00000684 f1d8bd1e48c317c28a6887e567bb6ea3f05c37199347cad7705f546a7b2b7479751f 000b56c0 000003f0 f1d8bd1e48c317c28a6887e567bb6ea3f0432107ae4ad9fb70615363463370 000b5ab0 00000504 f1d8bd1e48c317c28a6d81e673916ea7dd563700ae52cbed7f4d 000b5fb4 00000798 f1d8bd1f44d200cfa16eb7ee7ea07e99ce5d3e1b927dc8fb7d5954 000b674c 00000a94 f1d8bd1e48c317c28a6d81e673917baac35e312b8151ddef6b 000b71e0 00000140 f1d8bd0142c706f1b67e9afa72a06e99dd50261d9e7dd9fb7b5b49664d3172 000b7320 000008e4 f1d8bd0048d41ec2ba68b7fa64aa77 000b7c04 00000934 f1d8bd015dd400cb8a799bec7a 000b8538 000000b4 f1d8bd1f44d200cfa16287e648af78a9dd45 000b85ec 000002e4 f1d8bd0145da05f1a7789bd765af6eafc06e3b1a974d 000b8bcc 00000024 d7f3a73172f137e29c45a3d7539f 000b8bf0 00000028 d7f3a73172f436ea8a58b9 000b8c18 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000b8c44 0000005c d7f3a73172e737e39a5dadd7449f 000b8ca0 00000028 d7f3a73172e233e78154bcc15a8b5e 000b8cc8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000b8cd0 0000014c d1f8bd2d6bf631 000b8e1c 00000058 d1f8bd2d6bf636 000b8e74 0000010c d1f8bd2d6af026f1824aa1dc5e805d99ec73052ba966 000b8f80 00000024 d1f8bd2d60f331f19644a6dc52964e99ec791737ba 000b8fa4 00000018 f1d8bd1f4bd62dcdba659ced6fba45b5ca45 000b8fbc 00000164 d1f8bd1e49d416f1b26e9cd764bb69b6ca5f362b924dcde66c 000b9120 00000050 d1f8bd1e49d416f1b26e9cd774af6aa7cc58260d 000b9170 000000a8 d1f8bd1e49d416f1b26e9cd77bab6ca3c36e22069e45caed6b4d 000b9218 00000b1c d1f8bd0358dc17ddb66eb7fa72bf6fa3dc453710 000b9d34 00000090 f1d8bd0048d61dd8b079b7fc65af74b5ce52261d9e4ccbd77f5f53677b3c79746a1f 000b9dc4 00000098 f1d8bd0048d61dd8b079b7fc65af74b5ce52261d9e4ccbd77f5f53677b30657e77 000b9e5c 0000028c f1d8bd0048c607c3b0549be476b87f99dc442104944cdcfb 000ba0e8 0000008c d1f8bd0141d404cb8a6f81ed73 000ba174 00000128 d1f8bd0154c606cbb8549bfc76bc6eb3df6e3702944ccc 000ba29c 00000090 d1f8bd0442d907c3b0548be97bad6faace45372b8451ddfa475d4672453c7c6f60 000ba32c 0000006c d1f8bd0448c71bc8ac5485ed65a97f99de42 000ba398 00000048 d1f8bd0442d907c3b0548fed639175a5cc4422159f41c1 000ba3e0 0000005c f1d8bd0542c719f1b26a9ced48ad76a9dc54 000ba43c 00000070 d1f8bd0048d81ddab0548ce172aa 000ba4ac 0000005c f1d8bd0542c719f1b26a9ced48a16aa3c1 000ba508 0000005c f1d8bd0542c719f1b26a9ced48b97bafdb 000ba564 000000b8 d1f8bd1e49d416f1b26e9cd778ad79b3df503c1788 000ba61c 00000040 f1d8bd0743c61acfa76eb7fb63af6eb3dc 000ba65c 000002d4 f1d8881c41ea14c7bb6fb7ec72af76aac0520d048243ca 000ba930 000000b0 f1d8881c41ea15cba1548efa72ab45a3c145200d 000ba9e0 0000013c f1d8881c41ea18c1a07986e97b917fabdf452b 000bab1c 000000b8 f1d8881c41ea18c1a07986e97b9179aeca52392b9757d4e4 000babd4 000000e8 f1d8881c41ea18c1a07986e97b9176a9cc5a 000bacbc 0000008c f1d8881c41ea18c1a07986e97b916fa8c35e311f 000bad48 00000010 f1d8881c41ea06dcb4659bd770ab6e99dc4533008451 000bad58 00000024 f1d8881c41ea06dcb4659bd764ab6e99dc4533008451 000bad7c 00000188 f1d8881c41ea06dcb4659bd765ab7ba2 000baf04 000000a0 f1d8881c41ea06dcb4659bd765ab76a3ce4237 000bafa4 000000a0 f1d8881c41ea18c1a07986e97b9168b3c1553d039f 000bb044 000009c8 d1f8bd1e49d416f1a5798df876bc7f99cb543e118547 000bba0c 00000114 d1f8bd014ed01ec28a7b9aed67af68a3f05537189456dd 000bbb20 000001ac f1d8881c41ea06dcb4659bd760bc73b2ca 000bbccc 00000114 f1d8881c41ea18c1a07986e97b917caada423a 000bbde0 00000220 f1d8881c41ea18c1a07986e97b9179aaca5020 000bc000 0000032c f1d8881c41ea06dcb4659bd774a275b5ca 000bc32c 0000025c f1d8881c41ea06dcb4659bd77ba17d99df423713 000bc588 00000448 f1d8881c41ea06dcb4659bd778be7fa8 000bc9d0 000000bc f1d8bd1141da01cb8a7f9ae979bd7ba5db583d1a 000bca8c 000000fc f1d8bd1e49d416f1b366b7e965ab7b99dd543f1b8747 000bcb88 000000d0 f1d8bd1e49d416f1a57e9aef729177a3db5036158543 000bcc58 0000006c f1d8bd1e49d416f1b6649de6639174a9dd5c3318ae4fdde57a5b5571 000bccc4 00000314 d1f8bd1e49d416f1b46f8c 000bcfd8 0000006c f1d8bd1e49d416f1b6649de6639174a9dd5c3318ae50d9e17c0f787245366768 000bd044 0000034c d1f8bd1b43dc06f1a5789ce765ab 000bd390 0000006c f1d8bd1e49d416f1b6649de663917faac6563b169d47e7e57d534567562c 000bd3fc 0000006c f1d8bd1e49d416f1b6649de663917faac6563b169d47e7fa795743337b2f74726b09 000bd468 00000014 f1d8bd0048d61dd8b079b7fc65af74b5ce52261d9e4ccbd77e5f4e6e 000bd47c 00000c60 f1d8bd0048d61dd8b079b7fc65af74b5ce52261d9e4ce7e5714d44 000be0dc 000000dc f1d8bd0048d61dd8b079b7e473917ea3c3542611 000be1b8 00000398 d1f8bd115ed916f1a76e8be761ab6899db43331a8243dbfc71514971 000be550 00000088 f1d8bd0148c12dddac789ced7a9176a2ce55 000be5d8 000000f8 f1d8bd0148d917cda1549bf164ba7fabf05d361595 000be6d0 00000100 d1f8bd1e49d416f1b16e84ed63ab 000be7d0 000000c8 f1d8bd1548c12dddac789ced7a9176a2ce55 000be898 00000418 f1d8bd0743d11df1a76a9cfa65 000becb0 000006f4 d1f8bd0048d61dd8b079b7fc65af74b5ce52261d9e4ccb 000bf3a4 00000054 f1d8bd1548c12dcfa6689ce17aab 000bfac8 00000024 d7f3a73172f137e29c45a3d7539f 000bfaec 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000bfaf4 00000308 d1f8bd2d62f125e18740b7c5568754 000bfe68 00000028 d7f3a73172f436ea8a58b9 000bfe90 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000bfebc 00000028 d7f3a73172e233e78154bcc15a8b5e 000bfee4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000bfeec 0000012c f1d8bd1e49d416f1bc6581fc48a673b1ce453706 000c0018 000001ac f1d8bd1349df07dda1548cfd75917cb4ca540d179e57d6fc 000c01c4 00000104 f1d8bd1e49d416f1b6638deb7c9172afd850261183 000c02c8 00000028 f1d8bd1441c001c68a7b8be974a67f 000c02f0 00000038 f1d8bd1548c12dc8a56985d767bd7fa1 000c0328 0000016c d1f8bd1e49d416f1b9648be3 000c0494 000000e0 d1f8bd1e49d416f1a06584e774a5 000c0574 00000ae4 f1d8bd044cd91bcab47f8dd765ab69a3dd473710ae41d9f8795d4e765d 000c1058 00000018 d1f8bd2d6af026f1865ba9da529d4585fa630031bf76 000c1070 00000058 d1f8bd2d61f133ea8a58addc48815985fa61133ab27be7c051696656610d 000c10c8 000000a8 f1d8bd0142c706f1b66a98e974a76ebff0502006905b 000c1170 000000a4 e0c4971c49dc1cc9 000c1214 000007b8 d1f8bd2d7ef026f1865ba9da529d 000c19cc 0000006c d1f8c63b63fc26e79447a1d252914996ee631727 000c1a38 00000088 f1d8bd1b43dc06f1a6689afd75 000c1ac0 000000a8 f1d8bd1444db16f1a16285ed48ab76a7df423710 000c1b68 000001e0 f1d8bd1444db16f1a1649ce97b917baac35e31158547dcd7684d426557 000c1d48 000003dc f1d8bd014ec707cc8a678cd775af7e99cb502615 000c2124 000000ac f1d8bd005ec62dc9b07fb7e572a378a3dd6e360193 000c21d0 0000031c f1d8bd014ec707cc8a7d8dfa7ea86399cb58211fae46d9fc79 000c24ec 000000dc f1d8bd1e49ea16c7a660b7fb74bc6fa4 000c25c8 000000ec f1d8bd0241d11fcd8a6f81fb7c9169a5dd4430 000c26b4 00000050 f1d8bd115ed916f1b1629be348bd79b4da53 000c2704 0000004c fbd8bd237eea16c7a660 000c2750 00000130 f1d8bd014ec707cc8a7a9bd77aaa45a4ce550d109056d9 000c2880 000002bc f1d8bd035eea1fca8a6f81fb7c9169a5dd4430 000c2b3c 000003a0 d1f8bd1644c619f1a6689afd759177a7c65f 000c2edc 00000078 f1d8bd025ed401f1b36286ec48bb74a7c35d3d179056ddec475749664127 000c2f54 000000b0 f1d8bd025ed401f1bc6581fc7eaf76afd550261d9e4c 000c3004 00000238 f1d8bd025ed401f1b36286ec48a868a3ca6e22079445 000c323c 00000048 f1d8bd025ed401f1bc78b7f864ab7d99c9433711 000c3284 00000218 f1d8bd025ed401f1b46784e774916ab5ca56 000c349c 00000120 f1d8bd025ed401f1b3798ded48be69a3c8 000c35bc 00000170 f1d8bd025ed401f1b46784e774af6ea3f0443c018247dcd76a5b406b4b31 000c372c 00000074 f1d8bd025ed401f1b3798ded48af76aa 000c37a0 000000c0 f1d8bd025ed401f1a76e89e47eb47f 000c3860 00000090 d1f8bd025ed401f1b36286ec48ba72afdc6e3b1a9547c0 000c38f0 000000b8 d1f8bd025ed401f1b16e89e47ba179a7db54 000c39a8 0000013c d1f8bd025ed401f1b46784e774af6ea3 000c3ae4 000001ac f1d8bd1548c12dc0b0739cd776a276a9cc502611957dc8fb7d59 000c3c90 00000020 d1f8bd025ed401f1a76e89fb64a77da8f057221593 000c3cb0 000003c8 f1d8bd0154db11c6a76486e16dab45a0df5030 000c4078 00000164 f1d8bd114cc51fc9a7549aed7aa16ca3f041211196 000c41dc 0000020c f1d8bd005ed12dc8a76e8dd767bd7fa1dc 000c43e8 00000234 f1d8bd1648d41ec2ba6889fc72916ab5ca56 000c461c 000001f4 f1d8bd114cc51fc9a75489ec73916ab5ca56 000c4810 0000020c f1d8bd005ed12dcfb96787eb48be69a3c842 000c4a1c 0000044c f1d8bd025ed401f1a76e89e47eb47f99c355 000c4e68 00000198 f1d8bd1341d91dcdb47f8dd767bd7fa1 000c5000 000003a4 f1d8bd1341d91dcd8a7b9bed70 000c53a4 000001cc d1f8bd025ed401f1a67286eb7fbc75a8c64b372b9752d9ea 000c5570 000001d4 d1f8bd025ed401f1a67286eb7fbc75a8c64b372b9d46cbea 000c5744 000000f4 d1f8bd025ed401f1a76e89e47eb47f99c2503b1a 000c59ac 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000c59b4 000000bc d1f8bd2d6cf93ee1964abccd489c4982 000c5a70 00000044 d1f8bd2d69f033e29944abc9438b4594fc75 000c5ab4 00000268 d1f8c63b63fc26f18758bbd75a8b4e87 000c5d1c 0000002c d1f8bd2d7de020e99054badb44915783fb70 000c5d48 0000026c d1f8c6277df133fa9054badb44915783fb70 000c5fb4 0000009c f1d8bd1e49d11bdc8a6e86fc65b745a1ca45 000c6050 000000f4 f1d8bd1e49d11bdc8a6e86fc65b745b6da45 000c6144 00000118 f1d8bd1e49d11bdc8a6e86fc65b745b3df553300947ddee47959 000c625c 00000154 f1d8bd1e49d11bdc8a6e86fc65b745b3df553300947ddced6c5f446a7b3276 000c63b0 000001b0 f1d8bd1648d41ec2ba6889fc729168b5f05d3619 000c6560 00000170 f1d8bd1441c001c68a799beb76ad72a3 000c66d0 000000e8 d1f8bd1548c12dcaa7629eed 000c67b8 00000150 f1d8bd1648d41ec2ba6889fc729168b5 000c6908 000000d0 f1d8bd1548c12ddca66f81e5 000c69d8 00000108 f1d8bd1548c12ddca66f81e548ac63b6ce4221 000c6ae0 0000015c f1d8bd1548c12ddca66f85 000c6c3c 000004ec f1d8bd1548c12ddca66f85d767a663b5c6523318 000c7128 00000140 f1d8bd1548c12ddca66f85d765a36d 000c7268 00000150 f1d8bd1548c12ddca66f85fb 000c73b8 00000150 f1d8bd0258c12dcaa7629eed 000c7508 00000148 f1d8bd0258c12ddca66f81e5 000c7650 00000160 f1d8bd0258c12ddca66f85 000c77b0 000003ac f1d8bd0258c12ddca66f85d767a663b5c6523318 000c7b5c 000000cc f1d8bd0258c12ddca66f85d765a36d 000c7c28 000000d0 f1d8bd0142c706f1a7789b 000c7cf8 00000380 f1d8bd0848c71df1a778b7fa64aa77 000c8078 0000026c f1d8bd1341d91dcdb47f8dd765bd 000c82e4 00000390 f1d8bd0848c71df1a7788def48bc69a2c2 000c8794 00000028 d7f3a73172e233e78154bcc15a8b5e 000c87bc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000c87c4 00000114 f1d8bd0a40d311f1b6668cd773a174a3 000c88d8 00000050 f1d8bd0a40d311f1a77898d771a275b1 000c8928 00000050 f1d8bd0a40d311f1a77898d771a275b1f0532b049051cb 000c8978 00000110 f1d8bd0a40d311f1a77898d771a275b1f050311fae41d9e4745c46614f 000c8a88 00000050 f1d8bd0a40d311f1b16a9ce948af79adcb6e31159d4edae97b55 000c8ad8 000000d8 f1d8bd0a40d311f1b16a9ce948bc79b0cb 000c8bb0 00000488 f1d8bd0048c42dc6b4658ce472bc 000c9038 000000ec d1f8bd1548c12ddcb07a 000c9124 00000050 d1f8bd2d6ee62dfc905ab7cc58805f 000c9174 00000054 f1d8bd0048c42dcda66685d778be45a5c7503c1394 000c91c8 00000050 d1f8bd2d6ee62dfc905ab7cc58805f99ed680235a271 000c9218 00001010 d1f8bd2d6ee62dfc905ab7c5568754 000ca228 00000108 d1f8bd2d61f13ff1864ea6cc488d4999fd7403 000ca330 00000114 d1f8bd2d63fa3cf1994fa5d7448b5482f072012ba367e9 000ca444 000000c8 d1f8bd2d62e13aeb8754bbcd598a4585fc6e0031a0 000ca50c 00000078 d1f8bd2d62e13aeb8754bbcd598a4585fc6e0031a07df9db4170644a 000ca584 000000c0 d1f8c63d79fd37fc8a58adc653915e87fb70 000ca644 000007c0 d1f8bd2d7ff624f19658b7da529f 000cae04 0000044c f1d8bd0a40d311f1b6668cd765ad6ca2 000cb250 00000104 d1f8bd2d7ef63ff1864ea6cc488d4999fd7403 000cb354 000000e8 d1f8bd2d7ef63ff1864ea6cc488d4999fd74032bb071e1c65b76 000cb43c 000000b4 d1f8bd2d79fd3bfd8a58adc653915995f0631725 000cb654 00000024 d7f3a73172f137e29c45a3d7539f 000cb678 0000001c d7f3a73172f03cff804eb7cc46 000cb694 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000cb69c 00000030 d1f8bd3568e12ded9742bcd7479c5390ee6517 000cb6cc 0000096c d1f8bd2d6af026f1865ba9da52915987ff70113da57b 000cc038 00000054 d1f8bd1b43c313c2bc6f89fc72917cb6f0523d04887dd9fa7d5f 000cc08c 00000118 d1f8bd2d60f439eb8a5abdc7459b5799eb78013f 000cc1a4 0000005c d1f8bd2d60f03fec9059b7d8458b4a87fd740d39b871ebc15679 000cc200 00000360 d1f8bd2d7df936e39654a5c95e80 000cc560 000003b4 d1f8bd2d7ce62de39442a6 000cc914 00000050 d1f8bd2d7ce62de29a48a3 000cc964 00000050 d1f8bd2d7ce62dfb9b47a7cb5c 000cc9b4 0000004c d1f8bd2d7ff033fd8642afc6489e4983e86e113cb461f3 000cca00 0000024c d1f8bd2d7ff030fb9c47acd7478f488ffb68 000ccc4c 000000f4 d1f8bd2d7ff021fb984eb7ca50915596fc6e1426be6fe7db547f7147 000ccd40 000000f4 d1f8bd2d7ee021fe9045acd755894589ff620d32a36df5d74b72665461 000cce34 0000030c f1d8bd1341d91dcdb47f8dd767bd7fa1dc 000cd140 000002d8 f1d8bd1341d91dcdb47f8dd761af76afcb502611ae56cae9764d466150367a75 000cd418 00000200 f1d8bd1648d41ec2ba6889fc72916ab5ca5621 000cd618 00000118 f1d8bd1141d013dc8a7b8ae163 000cd730 000000ac d1f8bd1141d013dc8a7b8ae1639168b5ca56 000cd7dc 00000094 d1f8bd1141d013dc8a7b8ae1639168b5db5e2011 000cd870 000000e4 f1d8bd145fd017f1ad6f 000cd954 00000154 f1d8bd1548c12ddea66e8fd77ea07ea3d7 000cdaa8 000001f8 f1d8bd1548c12ddea66e8fd779bb77 000cdca0 00000100 f1d8bd1548c12ddcb06784ea76916aaf 000cdda0 000000bc f1d8bd1548c12dcaa069b7fa64bd45abca5c301183 000cde5c 00000108 f1d8bd1548c12dd6b1 000cdf64 0000015c f1d8bd1b5eea1fcbb8698dfa48af79a5ca42211d934edd 000ce0c0 000001b0 d1f8bd1b5eea02ddb06cb7ec76ba7b99ce5231118251d1ea745b 000ce270 000001ec f1d8bd1b5eea1fcbb8698dfa48ab76afc8583018947ddee76a61556747307b686d08f306c8 000ce45c 00000120 f1d8bd1e42d619f1a7789ce765ab45b7f0433705ae41d7e66c 000ce57c 00000440 f1d8bd1e42d619f1a7789ce765ab45b7f0433705 000ce9bc 00000358 d1f8bd2d7ff033fd8642afc6489e4983e8 000ced14 00000290 f1d8bd0048d41ec2ba68b7ee7ea07e99df42371382 000cefa4 00000104 f1d8bd0048d707c7b96fb7f876bc73b2d66e311b9f56d1e66d5b 000cf0a8 000000c0 f1d8bd0048d707c7b96fb7f876bc73b2d66e22169856e7ec775042 000cf168 000001c8 f1d8bd0048c42ddfa0628dfb74ab45aacb42302b9243d4e47a5f4469 000cf330 00000388 f1d8bd0048c607c3b0 000cf6b8 0000003c d1f8bd0048c607c3b0 000cf6f4 00000058 f1d8bd005eea00cbb26e86d773a174a3 000cf74c 0000025c f1d8bd015dd400cb8a6d81e673916ab5ca5621 000cf9a8 00000308 f1d8bd0158c602cbbb6f 000cfcb0 0000003c d1f8bd0158c602cbbb6f 000cfcec 0000017c d1f8bd2d7ff021fa9459bcd755894589ff62 000cfe68 00000434 f1d8bd0158c602cbbb6fb7f962ab6fa3f05826119c51 000d029c 000000b4 f1d8bd0743d91dcdbe549afb63a168a3 000d0350 000009b8 f1d8bd0048c606c1a76eb7fa64ba75b4ca6e36158543 000d0d08 00000268 f1d8bd1e42d619f1a7789ce765ab45b5ca5f362b9543cce9 000d0f70 00001970 f1d8bd075dd113dab0549afb63a168a3 000d28e0 000002ac f1d8bd075dd113dab0549afb63a168a3f05d3702944e 000d2b8c 00000294 f1d8bd075dd113dab0549afb63a168a3f05c3b138343cced 000d2e20 000001bc f1d8bd075dd113dab0549afb63a168a3f04337159d4ed7eb 000d2fdc 000001d0 f1d8bd075dd113dab0549afb63a168a3f04222158347 000d31ac 00000094 f1d8bd0148c12ddda56a9aed 000d3240 000000b0 f1d8bd1b5eea1eca8a798de973b745b2c06e3e118747d4 000d32f0 00000014 d1f8bd3162e03cfa8a4dbac74d8b5499e97d0727b9 000d3304 00000014 f1d8bd1548c12dc8a76492ed79917caada423a2b924dcde66c 000d3318 000000f0 f1d8bd1145d011c58a6d9ae76dab7499c95d27079947cb 000d3408 00000094 d1f8bd3165f031e58a4dbac74d8b5499e97d0727b97deacd49 000d3c18 0000000c d7f3a73172fc3ce78154acd9 000d3c24 00000024 d7f3a73172f137e29c45a3d7539f 000d3c48 00000038 d7f3a73172f137ff804eb7cc46 000d3c80 0000001c d7f3a73172f03cff804eb7cc46 000d3c9c 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000d3cb4 00000028 d7f3a73172f436ea8a58b9 000d3cdc 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 000d3d08 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000d3d10 00000290 f1d8bd1e49d416f1a76e9bfd7aab45bcca433d1d9f45 000d3fa0 0000052c f1d8bd1d49cf17dcba 000d44cc 00000204 f1d8bd0159da02f1af6e9ae77ea07d 000d46d0 0000020c f1d8bd1e49d416f1a67e9bf872a07e99d554201b984cdf 000d48dc 000000e8 f1d8bd1548c12ddca66fb7eb64bc7fb7 000d49c4 0000012c f1d8bd005ed12dc8b668 000d4af0 00000bc4 d1f8bd2d77f020e18a46a9c159 000d58b8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000d58c0 00000044 f1d8bd0158c602cbbb6fb7ec65a345aac0560d079950d1e673 000d5904 00000030 f1d8bd0048c607c3b0548cfa7a9176a9c86e211c834bd6e3 000d5934 00000094 d1f8bd2d66fc3ee28a47a7cf488f499fe1721a2bb56df6cd 000d59c8 00000364 d1f8bd2d7efd20e79b40b7c45889458aeb 000d5d2c 00000078 f1d8bd1145d011c58a799bfc78bc7f99ce5d3e1b92 000d5da4 00000120 f1d8bd1548c12dc2b4798fed64ba45a2dd5c0d189e45 000d5ec4 000000ac f1d8bd1548c12dcaa766b7e478a945b5c64b37 000d5f70 000000b0 f1d8bd145fd017f1b17985d77ba17d 000d6020 000001b4 f1d8bd165fd82dcbad7b89e6739176a9c86e271a9856 000d61d4 000000c8 f1d8bd0142c706f1b17985d77ba17d 000d629c 00000158 f1d8bd115fd013dab05484e770917bb4dd502b 000d63f4 0000007c d1f8bd2d63f037ea8a47a5c947 000d6470 00000064 d1f8c6367ff82dfd905fb7c6408c5392fc 000d64d4 00000178 f1d8bd165fd82dddb07fb7e660ac73b2dc 000d664c 00000004 f1d8bd0154db11c6a76486e16dab45a0df50302b9550d5d7745140 000d6650 000000a0 f1d8bd165fd82dcfb96787eb48aa75a8ca 000d66f0 000001e8 d1f8bd0145da05f1b17985d77ba17d 000d6a50 00000060 ffce8f1140c5 000d6ab0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000d6ab8 00000184 e0d8bd1a4cc716f1b66498f148bc7fa7cb 000d6c3c 00000184 e0d8bd1142c50bf1a56391fb7ead7baaf05d3b1a9a47dcd76b594b717b3b7a757c 000d6dc0 00000020 e0d8bd1a4cc716f1b66498f148aa75a8ca 000d6de0 00000110 e0d8bd1a4cc716f1b66498f148a97fb2f04337079e57caeb7d4d 000d6ef0 000001f4 c0f8bd1142c50bf1a56391fb7ead7baaf055330090 000d70e4 000000b8 e0d8bd1142c50bf1a56391fb7ead7baaf0553d1a94 000d719c 000000c4 e0d8bd1a4cc716f1b66498f148b968afdb540d109e4cdd 000d7260 00000154 e0d8bd1a4cc716f1b66498f148ab78afdb6e25069856ddd77f514866 000d73b4 000001a8 e0d8bd1a4cc716f1b66498f148bd7fb2f054301d8551 000d755c 00000098 e0d8bd1a4cc716f1b66498f148ab78afdb 000d75f4 0000018c e0d8bd1a4cc716f1b66498f148bc7fa7cb6e361b9f47 000d7780 00000218 e0d8bd1a4cc716f1b66498f148bd7fb2f054301d8551e7ec775042 000d7998 0000023c e0d8bd1a4cc716f1b66498f148ab78afdb6e20119046e7ec775042 000d7bd4 0000007c e0d8bd1a4cc716f1b66498f148ab78afdb6e25069856ddd76061436d4a3a 000d7c50 00000244 e0d8bd1142c50bf1a7788def48a97fb2f04337079e57caeb7d4d 000d7e94 00000144 e0d8bd1142c50bf1a7788def48a873a8c6423a 000d7fd8 00000250 e0d8bd1142c50bf1a7788def48aa7599dd010d069443dc 000d8228 000002b0 e0d8bd1142c50bf1a7788def48aa7599dd010d03834bcced 000d84d8 0000009c e0d8bd1142c50bf1a7788def48bc2a99d8433b00947ddce7765b 000d8574 000001c8 e0d8bd1142c50bf1a7788def48aa7599dd000d069443dc 000d873c 00000288 e0d8bd1142c50bf1a7788def48aa7599dd000d03834bcced 000d89c4 0000014c e0d8bd1142c50bf1a7788def48ac7ba2f043632b8650d1fc7d 000d8b10 00000098 e0d8bd1142c50bf1a7788def48bc2b99d8433b00947ddce7765b 000d8ba8 000001d8 e0d8bd1142c50bf1a7788def48aa7599dd040d069443dc 000d8d80 0000022c e0d8bd1142c50bf1a7788def48bd6ea7dd45 000d8fac 00000024 c0f8bd1142c50bf1a7788def 000d8fd0 000001bc e0d8bd1142c50bf1a7788def48aa7599dd040d03834bcced 000d918c 000001b0 e0d8bd1142c50bf1a7788def48bc2f99d8433b00947ddce7765b 000d933c 00000024 e0d8bd1142c50bf1a7788def48bc2f99d8433b00947ddbea714a78664b3170 000d9360 000001ac e0d8bd1142c50bf1a7788def48aa75999d552100ae5088d76f4c4e7641 000d950c 00000280 e0d8bd1142c50bf1a7788def48aa75999d552100ae5089d76f4c4e7641 000d978c 000001ac e0d8bd1142c50bf1a7788def48aa75999d552100ae508dd76f4c4e7641 000d9938 0000030c e0d8bd1142c50bf1a7788def48fc7eb5db6e3015957dcffa714a42 000d9c44 00000088 e0d8bd1142c50bf1a7788def48fc7eb5db6e25069856ddd77c514967 000d9ccc 0000037c e0d8bd1142c50bf1a7788def48fc7eb5db6e311b9f56d1e66d5b 000da048 00000208 e0d8bd1142c50bf1a7788def48fc7eb5db6e2045ae41dae16c 000da250 0000025c e0d8bd1142c50bf1a7788def48aa75999d552100ae43dae6474c165d532d7c6f7c 000da4ac 00000208 e0d8bd1142c50bf1a7788def48fc7eb5db6e2041ae41dae16c 000da6b4 0000017c e0d8bd1142c50bf1a7788def48aa75999d552100ae43dae6474c125d532d7c6f7c 000da830 00000144 e0d8bd1142c50bf1a7788def48aa75999d552100ae55cae16c5b 000da974 00000170 e0d8bd1142c50bf1a7788def48fc7eb5db6e33169f7dcffa714a42 000daae4 000000ec e0d8bd1142c50bf1a7788def48bc2f99dd543310ae46d7e67d 000dabd0 000002e4 e0d8bd1142c50bf1a7788def48bc2b99dd543310ae46d7e67d 000daeb4 00000184 e0d8bd1142c50bf1a7788def48bc2a99dd543310ae46d7e67d 000db038 00000080 e0d8bd175fc62ddeb17e 000db0b8 00000070 c0f8bd175fc62ddebd729b 000db128 00000078 e0d8bd175fc62ddebd729bd773a174a3 000db1a0 00000104 c0f8bd175fc62ddcb4628cb8 000db2a4 0000006c e0d8bd175fc62ddce5548ce779ab 000db310 00000198 c0f8bd175fc62ddcb4628cb9 000db4a8 000000c8 e0d8bd175fc62ddce4548ce779ab 000db570 00000150 c0f8bd175fc62ddfa6 000db6c0 00000128 e0d8bd175fc62ddfa6548ce779ab 000db7e8 00000050 c0f8bd175fc62ddbbb6a84e478ad 000db838 00000094 c0f8bd1548c12dc8b06f9b 000db8cc 00000068 e0d8bd054cdc06f1b36e8cfb 000db934 00000098 e0d8bd001cea00cc8a6f87e672 000db9cc 000001c8 e0d8bd001cea00cc8a789ce965ba 000dbb94 00000028 c0f8bd004cdc169f8a798df876a76899cd5d3d179a 000dbbbc 00000160 e0d8bd001cea00cc8a798de973917ea9c154 000dbd1c 0000003c e0d8bd001cea00cc8a7c9ae163ab45a2c05f37 000dbd58 000000dc e0d8bd0018ea00cc8a6f87e672 000dbe34 00000294 e0d8bd0018ea00cc8a789ce965ba 000dc0c8 00000028 c0f8bd004cdc169b8a798df876a76899cd5d3d179a 000dc0f0 00000128 e0d8bd0018ea00cc8a798de973917ea9c154 000dc218 00000138 e0d8bd0018ea00cc8a7387fa48aa75a8ca 000dc350 0000003c e0d8bd0018ea00cc8a7c9ae163ab45a2c05f37 000dc38c 000002bc e0d8bd0048d707c7b96fb7f876bc73b2d66e2045ae45ddfc474c42714b2a67787c09 000dc648 00000020 c0f8bd0048d707c7b96fb7f876bc73b2d66e2045 000dc668 00000108 e0d8bd0048d707c7b96fb7f876bc73b2d66e2045ae44d1e6714d4f 000dc770 00000038 e0d8bd0048d707c7b96fb7f876bc73b2d66e2045ae41dae16c61436d4a3a 000dc7a8 0000017c e0d8bd0048d707c7b96fb7f876bc73b2d66e2045ae55cae16c5b78664b3170 000dc924 00000318 e0d8bd0048d707c7b96fb7f876bc73b2d66e2045ae50dde97c61436d4a3a 000dcc3c 00000178 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae46d7d76a5b466657 000dcdb4 00000170 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae45ddfc474c42714b2a67787c09 000dcf24 00000020 c0f8bd0048d707c7b96fb7f876bc73b2d66e2041 000dcf44 000000f8 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae5ad7fa475a486c41 000dd03c 00000108 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae44d1e6714d4f 000dd144 00000024 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae41dae16c61436d4a3a 000dd168 00000074 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae55cafc475a486c41 000dd1dc 000001b8 e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae50dde97c61436d4a3a 000dd394 000000b8 e0d8bd004fd32ddeb17e 000dd44c 00000090 e0d8bd004fd32ddeb17eb7ea6ebe7bb5dc 000dd4dc 00000058 c0f8bd004fd32ddbbb6a84e478ad 000dd534 00000074 c0f8bd004fd32ddebd729b 000dd5a8 00000094 e0d8bd004fd32ddebd729bd773a174a3 000dd63c 00000070 c0f8bd004fd32ddebd729bd775b76aa7dc42 000dd6ac 000000dc c0f8bd004fd32ddfa6 000dd788 000000fc e0d8bd004fd32ddfa6548ce779ab 000dd884 000000d8 c0f8bd004fd32ddfa6548af167af69b5 000dd95c 0000012c e0d8bd004fd32ddfa6548af167af69b5f0553d1a94 000dda88 00000130 c0f8bd004fd32ddce4 000ddbb8 0000018c e0d8bd004fd32ddce4548ce779ab 000ddd44 00000108 c0f8bd004fd32ddce4548af167af69b5 000dde4c 0000018c e0d8bd004fd32ddce4548af167af69b5f0553d1a94 000ddfd8 00000118 e0d8bd004ed42dc9b07fb7fb70a2 000de0f0 000000bc c0f8bd004ed42ddebd729b 000de1ac 00000084 e0d8bd0245cc01f1b16486ed 000de230 00000138 c0f8bd004ed42ddfa6 000de368 00000114 e0d8bd004ed42ddfa6548ce779ab 000de47c 000002c0 c0f8bd004ed42ddbbb6a84e478ad 000de73c 00000084 e0d8bd004ed42ddebd729bd773a174a3 000de7c0 000001bc c0f8bd0040 000de97c 000002cc e0d8bd0040ea00f1b16486ed 000dec48 00000118 e0d8bd0040ea1bdda67e8dd765ab7ba2f0453d2b877ddcfa714842 000ded60 00000414 e0d8bd0040ea16c18a798df876a768 000df174 000000b4 e0d8bd0040ea04dc8a6f87e672 000df228 000000c4 e0d8bd0040ea04f1b16486ed 000df2ec 00000058 e0d8bd0040ea00cba56a81fa48aa75a8ca 000df344 00000170 c0f8bd0040ea03dd 000df4b4 000000fc e0d8bd0040ea03dd8a7d8dfa7ea86399c1542a00 000df5b0 000000f0 e0d8bd0040ea03dd8a629bfb62ab45b4ca50362b854de7fe475a556b523a 000df6a0 00000194 e0d8bd0040ea03dd8a6f87d765ab6aa7c643 000df834 00000150 e0d8bd0040ea03dd8a7d9ad773a174a3 000df984 000000ac e0d8bd0040ea03dd8a6f87e672 000dfa30 00000044 e0d8bd0040ea03dd8a798df876a76899cb5e3c11 000dfa74 000000fc e0d8bd0040ea03dd8a7db7ec78a07f 000dfb70 00000174 e0d8bd0040ea03dd8a79b7ec78a07f 000dfce4 00000180 c0f8bd0040ea03dd8a6991f876bd69 000dfe64 000000fc e0d8bd0040ea03dd8a6991f876bd6999d954201d975be7e67d4653 000dff60 000000f0 e0d8bd0040ea03dd8a6991f876bd6999c6422101947dcaed795a78764b0063447d08ef13d9 000e0050 000001a4 e0d8bd0040ea03dd8a6991f876bd6999cb5e0d069452d9e16a 000e01f4 00000150 e0d8bd0040ea03dd8a6991f876bd6999d9430d109e4cdd 000e0344 000000ac e0d8bd0040ea03dd8a6991f876bd6999cb5e3c11 000e03f0 00000044 e0d8bd0040ea03dd8a6991f876bd6999dd5422159850e7ec775042 000e0434 000000fc e0d8bd0040ea03dd8a6991f876bd6999d96e361b9f47 000e0530 00000174 e0d8bd0040ea03dd8a6991f876bd6999dd6e361b9f47 000e06a4 000000cc c0f8bd044fd32ddebd729b 000e0770 000000a4 e0d8bd044fd32ddebd729bd773a174a3 000e0814 000000bc c0f8bd0448c71bc8ac5498e06ebd45a8c06e36158543 000e08d0 00000084 e0d8bd0448c71bc8ac5498e06ebd45a8c06e36158543e7ec775042 000e0954 00000168 c0f8bd0448c71bc8ac549ae97eaa2a 000e0abc 00000074 e0d8bd0448c71bc8ac549ab848aa75a8ca 000e0b30 00000218 c0f8bd0448c71bc8ac549ae97eaa2b 000e0d48 000000d4 e0d8bd0448c71bc8ac549ab948aa75a8ca 000e0e1c 0000018c c0f8bd0448c71bc8ac549ae97eaa2f 000e0fa8 00000074 e0d8bd0448c71bc8ac549abd48aa75a8ca 000e101c 00000088 c0f8bd0455cd2ddbbb6a84e478ad45a5c05f261d9f57dd 000e10a4 000000b8 e0d8bd054fd32ddeb17e 000e115c 00000090 e0d8bd054fd32ddeb17eb7ea6ebe7bb5dc 000e11ec 00000074 c0f8bd054fd32ddebd729b 000e1260 00000094 e0d8bd054fd32ddebd729bd773a174a3 000e12f4 00000070 c0f8bd054fd32ddebd729bd775b76aa7dc42 000e1364 000001a0 c0f8bd054fd32ddfa6 000e1504 0000013c e0d8bd054fd32ddfa6548ce779ab 000e1640 000001cc c0f8bd054fd32ddfa6548af167af69b5 000e180c 00000164 e0d8bd054fd32ddfa6548af167af69b5f0553d1a94 000e1970 000001e0 c0f8bd054fd32ddcb4628cb9 000e1b50 000000c4 e0d8bd054fd32ddce4548ce779ab 000e1c14 00000198 c0f8bd054fd32ddcb4628cb948ac63b6ce4221 000e1dac 0000013c e0d8bd054fd32ddce4548af167af69b5f0553d1a94 000e1ee8 00000078 c0f8bd055fc62ddebd729b 000e1f60 00000074 e0d8bd055fc62ddebd729bd773a174a3 000e1fd4 0000010c c0f8bd055fc62ddcb4628cb8 000e20e0 00000068 e0d8bd055fc62ddce5548ce779ab 000e2148 000001c8 c0f8bd055fc62ddcb4628cb9 000e2310 000000c8 e0d8bd055fc62ddce4548ce779ab 000e23d8 00000158 c0f8bd055fc62ddfa6 000e2530 00000124 e0d8bd055fc62ddfa6548ce779ab 000e2654 00000050 c0f8bd055fc62ddbbb6a84e478ad 000e26a4 000000a4 e0d8bd055bcd2ddeb17e 000e2748 00000018 c0f8bd0a55cd2ddbbb6086e760a0 000e2760 0000021c c0f8bd0848c71df1b16486ed 000e297c 000001b0 c0f8bd0555cd2ddbbb6a84e478ad 000e2b2c 000002d0 c0f8bd0455cd2ddbbb6a84e478ad 000e2e30 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000e2e38 00000054 f1c6bd1548c12ddcbb67 000e2e8c 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 000e2ea0 00000074 e0d8bd1058dc1eca8a659ed774af79aeca6e21139d 000e2f14 0000008c c0f8bd0242c507c2b47f8dd7619169a1c3 000e2fa0 00000044 c0f8bd1648c51ddea06789fc72916c99dc563e 000e2fe4 00000214 c0f8bd1e42d619f1a56a9ae163b7 000e31f8 00000130 c0f8bd004ed42ddcb4628cb8 000e3328 00000058 e0d8bd004ed42ddce5548ce779ab 000e3380 000001e4 c0f8bd004ed42ddcb4628cb9 000e3564 000000d4 e0d8bd004ed42ddce4548ce779ab 000e3638 00000134 c0f8bd004ed42ddcb4628cbd 000e376c 0000005c e0d8bd004ed42ddce0548ce779ab 000e37c8 00000038 c0f8bd004cdc169ea6549ffa7eba7f 000e3800 00000190 e0d8bd004cdc169ea6549ffa63916ab4ca4133069446 000e3990 0000008c e0d8bd004cdc169ea6549ffa639179a7cc59372b954dd6ed 000e3a1c 00000080 e0d8bd004cdc169ea6549ffa63917ea9c154 000e3a9c 000000e8 c0f8bd004cdc169fa6549ffa7eba7f 000e3b84 00000294 e0d8bd004cdc169fa6549ffa63916ab4ca4133069446 000e3e18 0000008c e0d8bd004cdc169fa6549ffa639179a7cc59372b954dd6ed 000e3ea4 00000080 e0d8bd004cdc169fa6549ffa63917ea9c154 000e3f24 00000034 c0f8bd004cdc169d8a7c9ae163ab 000e3f58 0000006c e0d8bd004cdc169d8a7c9afc48a67bb5f05d3d179a 000e3fc4 0000029c e0d8bd004cdc169d8a7c9afc48a67bb5f04133069856c1 000e4260 0000008c e0d8bd004cdc169d8a7c9afc48aa75a8ca 000e42ec 00000130 c0f8bd0743d91dcdbe5498e965a76ebf 000e441c 00000094 e0d8bd004cdc169d8a7c9afc48ad7ba5c7540d109e4cdd 000e44b0 00000134 c0f8bd054ed42ddcb4628cb8 000e45e4 00000058 e0d8bd054ed42ddce5548ce779ab 000e463c 0000008c e0d8bd054ed42ddce4548ce779ab 000e46c8 0000007c e0d8bd054ed42ddce4549fec78a07f 000e4744 000000a4 e0d8bd055fc62ddeb17e 000e47e8 000001cc c0f8bd054ed42ddcb4628cb9 000e49b4 00000034 c0f8bd054ed42ddcb4628cbd 000e49e8 0000006c e0d8bd054ed42ddce05480e9649176a9cc5a 000e4a54 00000204 e0d8bd054ed42ddce0548ce748bc7fa7cb42 000e4c58 00000128 e0d8bd054ed42ddce0548fed639168a3dc5e27069247cb 000e4d80 000000d0 e0d8bd054ed42ddce0549aed76aa45a2c05f37 000e4e50 00000034 e0d8bd054ed42ddce05490e765917ea9c154 000e4e84 00000110 e0d8bd054ed42ddce0549aed76aa6399db5e0d03834bcced 000e4f94 0000013c e0d8bd054ed42ddce0548efa72ab45b4ca423d018341ddfb 000e50d0 000000a4 e0d8bd054ed42ddce0549ffa7eba7f99cb5e3c11 000e5174 0000031c e0d8bd054ed42ddce05498e965a76ebff0523a119249 000e5490 00000048 e0d8bd054ed42ddce05498e965a76ebff0523a119249e7f0774c78664b3170 000e54d8 000000e4 e0d8bd054ed42ddce05498e965a76ebff0523a119249e7ec775042 000e55bc 00000330 e0d8bd054ed42ddce05498e965a76ebff0523a119249e7eb77535763563a4a7f7614e3 000e58ec 000000b4 e0d8bd054ed42ddce05498e965a76ebff0523a119249e7fa7d5f43717b3b7a757c 000e59a0 000002c0 e0d8bd054ed42ddce65498e965a76ebff0523a119249 000e5c60 00000048 e0d8bd054ed42ddce65498e965a76ebff0523a119249e7f0774c78664b3170 000e5ca8 000000d8 e0d8bd054ed42ddce65498e965a76ebff0523a119249e7ec775042 000e5d80 000002e0 e0d8bd054ed42ddce65498e965a76ebff0523a119249e7eb77535763563a4a7f7614e3 000e6060 000000b4 e0d8bd054ed42ddce65498e965a76ebff0523a119249e7fa7d5f43717b3b7a757c 000e6300 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000e6308 0000008c e0d8bd104fc72dddac658be048a775 000e6394 0000003c e0d8bd104fc72dddac658be048a77599cb5e3c11 000e63d0 00000078 e0d8bd104fc72dcdbd60b7ee729169bfc1523a2b984d 000e6448 00000068 e0d8bd104fc72dd9a7629ced48ac7ba2f0422b1a924ae7e177 000e64b0 00000028 c0f8bd104fc72ddda16a9afc 000e64d8 00000098 e0d8bd104fc72dcdba7b91d763a145a4cd430d168444de 000e6570 0000009c e0d8bd104fc72ddcb06a8c 000e660c 00000198 e0d8bd104fc72dcab07f8dfa7aa774a3f0563d1b957ddce96c5f 000e67a4 00000118 e0d8bd104fc72ddcb0649aec72bc45a2ca573717857dd4e16b4a 000e68bc 000000ac e0d8bd104fc72dd9a7629ced 000e6968 0000019c e0d8bd104fc72ddcb0788dfc48aa7fa0ca52262b9d4bcbfc 000e6b04 00000350 e0d8bd104fc72ddcb06a9bfb7ea97499cd5d3d179a51 000e6e54 00000080 e0d8bd104fc72dcdb96e89e662be 000e6ed4 000004e4 e0d8bd104fc7 000e73b8 000000c4 c0f8bd1145d011c58a6d87fa48ac78b4 000e747c 00000060 e0d8bd104fc72dd9ba7983d771a774afdc59 000e74dc 00000434 e0d8bd104fc72dcdbd6e8be348a875b4f0463d069a 000e7910 000000f0 c0f8bd104fc72dc3b46286 000e7a00 000001c0 e0d8bd1548c12ddcb07b89e165917eb4c6473707ae4bd6ee77 000e7bc0 00000018 c0f8bd0048c200c7a16eb7fb63af68b2 000e7bd8 0000008c e0d8bd175fc72ddcb06887fe48bd63a8cc590d1d9e 000e7c64 00000230 e0d8bd0048c513c7a7549aeb769168a7c65563 000e7e94 0000022c e0d8bd0048c513c7a7549aea719168a7c65563 000e80c0 00000100 c0f8bd0048d61dd88a6689e179 000e81c0 0000003c e0d8bd175fc72ddcb06887fe48bd63a8cc590d1d9e7ddce7765b 000e81fc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000e8204 000001c8 e0d8bd1142db06c7bb7e8dd765af73a29e 000e83cc 000003c4 e0d8bd1142c50bf1a7788def48bc2b99ce533c2b8347d9ec 000e8790 00000568 e0d8bd1142c50bf1a7788def48bc2b99ce533c2b8650d1fc7d 000e8cf8 0000028c e0d8bd175fc62ddce454dae975a0 000e8f84 00000618 e0d8bd175fc62ddce45489ea79 000e959c 000000f0 e0d8bd175fc62ddce454dae975a045a2c05f37 000e968c 000001c8 e0d8bd004ed42ddce454dae975a0 000e9854 000004a4 e0d8bd004ed42ddce45489ea79 000e9cf8 000001a0 e0d8bd004ed42ddce454dae975a045a2c05f37 000e9e98 0000017c e0d8bd004fd32ddce454dae975a0 000ea014 0000015c e0d8bd004fd32ddce454dae673917ba4c1 000ea170 00000178 e0d8bd004fd32dccac7b89fb649168f7f00333169f 000ea2e8 00000158 e0d8bd004fd32dccac7b89fb649168f7f0033c10ae43dae6 000ea440 000002e0 e0d8bd0040ea13ccbb54dae572a345b4 000ea720 00000278 e0d8bd0040ea13ccbb54dae572a345a4ce550d179e4fc8e96a5b 000ea998 000001e8 e0d8bd0040ea40cfb765b7fa 000eab80 00000224 e0d8bd0040ea13ccbb549a 000eada4 00000290 e0d8bd054fd32ddce454dae975a0 000eb034 00000508 e0d8bd054fd32ddce45489ea79 000eb53c 000000f0 e0d8bd054fd32ddce454dae975a045a2c05f37 000eb62c 0000028c e0d8bd054fd32dccac7b89fb649168f7f00333169f 000eb8b8 000004fc e0d8bd054fd32dccac7b89fb649168f7f050301a 000ebdb4 000000f0 e0d8bd054fd32dccac7b89fb649168f7f00333169f7ddce7765b 000ebea4 000000a4 e0d8bd1542c11df1a26889d765af73a29e 000ebf48 00000294 e0d8bd054ed42ddce454dae975a0 000ec1dc 0000059c e0d8bd054ed42ddce45489ea79 000ec778 000000a4 e0d8bd1542c11df1a26889d765ff45a7cd5f 000ec81c 000000f0 e0d8bd054ed42ddce454dae975a045a2c05f37 000ec90c 000000a4 e0d8bd1542c11df1a26889d765ff45f4ce533c 000ec9b0 00000294 e0d8bd055fc62ddce454dae975a0 000ecc44 0000061c e0d8bd055fc62ddce45489ea79 000ed260 000000f0 e0d8bd055fc62ddce454dae975a045a2c05f37 000ed350 00000254 e0d8bd0448c71bc8ac549ab948fc7ba4c1 000ed5a4 000000d4 e0d8bd0448c71bc8ac549ab948fc7ba4c16e361b9f47 000ed678 000000e4 e0d8bd1a4cc716f1b66498f148a37fb4c8540d069443dc 000ed75c 0000010c e0d8bd1a4cc716f1b66498f148a37fb4c8540d139456e7fa7d4d4877563c7068 000ed868 0000024c c0f8bd004cdc169f8a668dfa70ab 000edab4 00000098 e0d8bd001cea1fcba76c8dd773a174a3 000edb4c 000000d4 e0d8bd1a4cc716f1b66498f148a37fb4c8540d109e4cdd 000edc20 000000c0 e0d8bd1a4cc716f1b66498f148a37fb4c8540d03834bcced475a486c41 000edce0 00000168 e0d8bd1a4cc716f1b66498f148a37fb4c8540d069443dcd77c514967 000ede48 00000194 e0d8bd005fea009f8a798dea62a776a2 000edfdc 00000088 e0d8bd001cea02dcba6687 000ee064 0000014c e0d8bd005fea009f8a6781e67cab7e99dc563e07ae46d7e67d 000ee1b0 00000020 e0d8bd005fea009f8a6389fa739179a9df480d109e4cdd 000ee1d0 00000110 e0d8bd005fea009f8a6389fa739179a9df480d069443dc 000ee2e0 00000140 e0d8bd005fea009f8a6389fa739179a9df480d03834bcced475a486c41 000ee420 000000b8 e0d8bd005fea009f8a6389fa739179a9df480d109e7dcffa714a42 000ee4d8 00000184 e0d8bd005fea009f8a6389fa739179a9df480d069443dcd77c514967 000ee65c 000000e8 e0d8bd005fea009f8a6389fa739179a9df48 000ee744 000001b0 c0f8bd004cdc169f8a798de964bd73a1c16e20119647d6 000ee8f4 000000d8 e0d8bd005fea009f8a798dea62a776a2f0553d1a94 000ee9cc 0000013c e0d8bd001cea02dcba6687d760bc73b2ca6e2811834dddfb 000eeb08 00000080 e0d8bd001cea02dcba6687d773a174a3 000eeb88 00000048 e0d8bd001cea02dcba6687d760bc73b2ca6e361b9f47 000eebd0 00000648 e0d8bd004cdc169fa65489ea79916db4db 000ef218 00000080 e0d8bd004cdc169fa65489ea79916db4db6e361b9f47 000ef298 000000b0 e0d8bd1542c11df1a76a81ec26bd45b1dd450d048347c8e96a5b43 000ef348 00000050 e0d8bd1542c11df1a76a81ec26bd45a7cd5f0d038356 000ef398 000001d0 e0d8bd0448c71bc8ac549ab948ab68b4c043 000ef568 00000774 e0d8bd0448c71bc8ac549ab948af78a8 000efcdc 0000014c e0d8bd0448c71bc8ac549ab948ab68b4c0430d069443dcd77c514967 000efe28 000000b8 e0d8bd0448c71bc8ac549ab948bd7daaf0433704904bcad77c514967 000efee0 00000074 e0d8bd0448c71bc8ac549ab948bc7fb6ce58202b954dd6ed 000eff54 000001e8 e0d8bd175fc62ddce55489ea79 000f013c 000001f4 e0d8bd004ed42ddce55489ea79 000f0330 000002c0 e0d8bd0448c71bc8ac549ab848af78a8 000f05f0 00000238 e0d8bd054ed42ddce55489ea79 000f0828 000001cc e0d8bd004cdc169ea65489ea79916db4db 000f09f4 000001f0 e0d8bd055fc62ddce55489ea79 000f0d08 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000f0d10 00000004 e0d8bd1c54dc 000f0d14 000002a4 e0d8bd115fc617c98a79ddd776ac7499dd543310ae41d7e56852 000f0fb8 000000cc e0d8bd1142c50bf1a7788def48bc2f99dd016310ae50dde97c4e78664b3170 000f1084 00000054 e0d8bd115fea02dcba6687d773a174a3 000f10d8 0000027c e0d8bd115fea02dcba6687fc729168a3cd443b18957dc8e96a57537b 000f1354 00000134 e0d8bd115fea02dcba6687fc72916db4c645372b8143cae16c47 000f1488 00000044 e0d8bd115fea02dcba6687fc72916db4c645372b8143cae16c4778664b3170 000f14cc 000000a0 e0d8bd1142db06c7bb7e8dd765fb 000f156c 0000013c e0d8bd1142db06c7bb7e8dd760a76eaef00333169f 000f16a8 00000440 e0d8bd115fc617c98a79ddd776ac7499dd543310 000f1ae8 00000124 e0d8bd1b43d61dc3a5678dfc729168a7c655672b8650d1fc7d 000f1c0c 000000a0 e0d8bd1642ea1bc18a7b9ae17aaf68bf 000f1cac 000000a8 e0d8bd054ed42ddce65489ea79917ea9c154 000f1d54 0000005c e0d8bd054ed42ddce65489ea799173a9f0433700835b 000f1db0 000002a0 e0d8bd004ed42ddce05489ea799177b5f0553d2b8347d9ec6b 000f2050 00000064 e0d8bd004ed42ddce05489ea799177b5f0593307ae4ed7eb73 000f20b4 0000018c e0d8bd004ed42ddce05489ea799177b5f0433715957ddce7765b 000f2240 00000210 e0d8bd004ed42ddce05489ea799177b5f0493d06ae46d7e67d 000f2450 00000110 e0d8bd004ed42ddce05489ea799177b5f0433704904bcad77c514967 000f2560 000001a0 e0d8bd004ed42ddce054dae975a0 000f2700 00000354 e0d8bd004ed42ddce05489ea79 000f2a54 00000080 e0d8bd004ed42ddce054dae975a045b4ca50362b954fe7ec775042 000f2ad4 00000214 e0d8bd004ed42ddce054dae975a045a2c06e20119046cb 000f2ce8 00000064 e0d8bd004ed42ddce054dae975a045aece420d189e41d3 000f2d4c 000000f4 e0d8bd004ed42ddce054dae975a045a2c05f37 000f2e40 00000024 e0d8bd004ed42ddce054dae975a045bec0430d109e4cdd 000f2e64 000000d0 e0d8bd004ed42ddce054dae975a045b4ca50362b954dd6ed 000f2f34 000000a4 e0d8bd0642da2dc3b46591d774ac73b2dc 000f2fd8 00000598 e0d8bd054ed42ddce654dae975a0 000f3570 000006e4 e0d8bd054ed42ddce65489ea79 000f3c54 000001e0 e0d8bd115fea02dcba6687fc729169a3db6e2a169856 000f3e34 00000144 e0d8bd115fea02dcba6687fc729168a3ce550d109e4cdd 000f3f78 00000050 e0d8bd115fea02dcba6687fc72916db4c645372b954dd6ed 000f3fc8 0000017c e0d8bd115fea02dcba6687fc72916db4c645372b8b47cae77d4d 000f4144 00000160 e0d8bd115fea02dcba6687 000f42a4 000000f8 e0d8bd115fc617c98a79ddd776ac7499dd016310ae4fdcd76a61436d4a3a 000f439c 000000e8 e0d8bd115fc617c98a79ddd776ac7499dd04362b9c46e7fa475a486c41 000f4484 000000c8 e0d8bd115fc617c98a79ddd776ac7499c2410d06ae46d7e67d 000f454c 00000310 e0d8bd115fc617c98a79ddd776ac7499d8433b0094 000f485c 0000012c e0d8bd054ed42ddce05489ea79917ea9c154 000f4988 00000074 e0d8bd054ed42ddce05489ea79917ea7db500d109e4cdd 000f49fc 000000bc e0d8bd054ed42ddce054dae975a045b4ca50362b954dd6ed 000f4ab8 00000038 e0d8bd054ed42ddce054dae975a045bec0430d109e4cdd 000f4af0 000000ec e0d8bd054ed42ddce054dae975a045b4ca50360dae56d7d76f4c4e7641 000f4bdc 000000a8 e0d8bd054ed42ddce054dae975a045b1dd582611ae46d7e67d 000f4c84 000000c0 e0d8bd054ed42ddce054dae975a045b4d86e20119046e7ec775042 000f4d44 00000038 e0d8bd054ed42ddce054dae975a045b4d86e2a1b837ddce7765b 000f4d7c 00000110 e0d8bd054ed42ddce054dae975a045b6ce433b00887dcaed795a5e 000f4e8c 000002dc e0d8bd054ed42ddce054dae975a045abcb 000f5168 00000038 e0d8bd054ed42ddce05489ea799168b1f0493d06ae46d7e67d 000f51a0 0000003c e0d8bd054ed42ddce05489ea79916db4c645372b8143cae16c4778664b3170 000f51dc 00000034 e0d8bd005aea0ac1a7548ce779ab 000f5210 0000036c e0d8bd025fda1fc1a16eb7fa72ac6fafc3550d049050d1fc61 000f557c 00000030 e0d8bd1542c11df1a26889d765fb45a7cd5f 000f55ac 0000064c e0d8bd054ed42ddce054dae975a0 000f5bf8 000002c8 e0d8bd014fc72ddce0 000f5ec0 00000190 e0d8bd014fc72dd6ba79b7ec78a07f 000f6050 0000006c e0d8bd014fc72dd9a7629ced48aa75a8ca 000f60bc 00000ce8 e0d8bd054ed42ddce05489ea79 000f6da4 00000030 e0d8bd054ed42ddce05489ea79917ea7db500d118350d7fa 000f6dd4 00000288 e0d8bd025fda1fc1a16eb7fb72ba45becd5826 000f705c 00000158 e0d8bd025fda1fc1a16eb7ff65a76ea3f04b37069e47cb 000f71b4 00000160 e0d8bd025fda1fc1a16e 000f7314 000001fc e0d8bd005aea00cbb46fb7ec78a07f 000f7510 0000013c e0d8bd014fc72ddcb06a8cd773a174a3 000f764c 0000025c e0d8bd005a 000f78a8 00000080 e0d8bd025fda1fc1a16eb7ff65a76ea3f0553d1a94 000f7928 000001e0 e0d8bd005aea02cfa7629cf148bc7fa7cb48 000f7b08 00000104 e0d8bd054ed42ddce05489ea79916aa7dd58260dae50dde97c47 000f7c0c 000000f4 e0d8bd054ed42ddce05489ea799168b1f0433715957ddce7765b 000f7d00 0000010c e0d8bd025fda1fc1a16eb7ff65a76ea3f04133069856c1 000f7e0c 00000154 e0d8bd025fda1fc1a16eb7fa72af7e99cb5e3c11 000f7f60 000000f4 e0d8bd025fda1fc1a16eb7ec78a07f99cb5e0d109851c8e96c5d4f 000f8054 00000054 e0d8bd025fda1fc1a16eb7ff65a76ea3f04133069856c1d7625b556d7b3b7a757c 000f80a8 00000070 e0d8bd025fda1fc1a16eb7ff65a76ea3f04133069856c1d77c514967 000f8118 00000098 e0d8bd005fea009b8a6f87d765ab7da3c16e2a1b83 000f81b0 00000100 e0d8bd1548c12dcab06d81e672aa45aac65f3911957dcbef744d 000f82b0 00000124 e0d8bd005fea02dcba6687d773a174a3 000f83d4 00000248 e0d8bd005fea02dcba6687fc729168a3cd443b18957dc8e96a57537b 000f861c 0000021c e0d8bd005fea02dcba6687fc729169a3db6e2a169856 000f8838 00000050 e0d8bd005fea02dcba6687fc72916db4c645372b954dd6ed 000f8888 00000148 e0d8bd005fea02dcba6687fc72916db4c645372b8b47cae77d4d 000f89d0 00000214 e0d8bd005fea02dcba6687fc72 000f8be4 00000198 e0d8bd005fea009b8a6781e67cab7e99dc563e07ae46d7e67d 000f8d7c 00000020 e0d8bd005fea009b8a6f87e672 000f8d9c 00000194 e0d8bd005fea009b8a798de973917ea9c154 000f8f30 000001a0 e0d8bd005fea009b8a798de973 000f90d0 000000dc e0d8bd005fea009b8a789ce965ba 000f91ac 00000044 c0f8bd004cdc169b8a798de964bd73a1c16e20119647d6 000f91f0 00000190 e0d8bd005fea009b8a7c9ae163ab45a7c35d0d109e4cdd 000f9380 000002e0 e0d8bd005fea009b8a7c9ae163ab45a7c35d 000f9660 000000e0 e0d8bd005fea009b8a7c9ae163ab45a2c05f37 000f9740 000001c4 e0d8bd005fea009b8a7387fa48aa75a8ca 000f9904 0000010c e0d8bd005fea02dcba6687fc72916db4c645372b8143cae16c47 000f9a10 00000134 e0d8bd005fea02dcba6687fc729168a3ce550d109e4cdd 000f9b44 00000044 e0d8bd005fea02dcba6687fc72916db4c645372b8143cae16c4778664b3170 000f9b88 00000180 e0d8bd0048d707c7b96fb7f848bc2f99dc53202b954de7fa7d5f4371 000f9d08 0000009c e0d8bd0048d707c7b96fb7f876bc73b2d66e2041ae50dde97c614270563067 000f9da4 000000e4 e0d8bd0048d707c7b96fb7f848bc2f99dc53202b8347d9ec475a486c41 000f9e88 00000140 e0d8bd0048d707c7b96fb7f848bc2f99d75e202b954dd6ed 000f9fc8 00000044 e0d8bd0048d707c7b96fb7f848bc2f99dc53202b8650d1fc7d61436d4a3a 000fa00c 00000370 e0d8bd0448c71bc8ac549abd48ab68b4c043 000fa37c 000003f0 e0d8bd0448c71bc8ac549abd48af78a8 000fa76c 00000208 e0d8bd0448c71bc8ac549abd48a67bb5f05d3d179a 000fa974 000001c4 e0d8bd0448c71bc8ac549abd48bc7fa7cb6e361b9f47 000fab38 00000110 e0d8bd0448c71bc8ac549abd48b675b4f0553d1a94 000fac48 00000158 e0d8bd0448c71bc8ac549abd48bd6ab4c645372b924dd5f8794c425d40307b7e 000fada0 0000025c e0d8bd0048c607c3b0549abd48b968afdb540d109e7dcaed795a 000faffc 000000b8 c0f8bd0048c607c3b0549ae97eaa2f99d8433b0094 000fb104 00000028 d7f3a73172f436ea8a58b9 000fb12c 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 000fb170 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fb178 00000174 e0d8bd1e4ed92dcdba6698e965ab45b2d85e0d079e57caeb7d4d 000fb2ec 00000054 c0f8bd1142d802cfa76eb7fc60a145b5c04420179451 000fb340 000001c0 e0d8bd1e4ed92dcdba6698e965ab45b2c06e2811834d 000fb500 00000050 c0f8bd1142d802cfa76eb7fc789160a3dd5e 000fb550 00000188 e0d8bd0a42c740 000fb6d8 00000030 e0d8bd1642ea0ac1a739 000fb708 000001a0 e0d8bd0a42c741 000fb8a8 00000034 e0d8bd1642ea0ac1a738 000fb8dc 000001f0 e0d8bd0a42c746 000fbacc 00000038 c0f8bd1642ea0ac1a73f 000fbb04 000001c8 e0d8bd1e44db19cbb1549bef7b9162a9dd05 000fbccc 0000020c e0d8bd1044d22dc2bc6583ed739169a1c36e2a1b8316 000fbed8 00000034 c0f8bd1642ea10c7b25484e179a57fa2f0493d06c5 000fbf0c 0000000c d7f3a73172fc3ce78154acd9 000fbf18 00000038 d7f3a73172f137ff804eb7cc46 000fbf50 0000001c d7f3a73172f03cff804eb7cc46 000fbf6c 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 000fbf84 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fbf8c 00000048 d7f3a73172dc1cc7a1548af962ab 000fbfd4 00000040 d7f3a73172c717cdb0629eed48ac6bb3ca 000fc014 00000060 d7f3a73172c717cdb0629eed48ac6bb3ca6e261d9c47dc 000fc074 00000020 d7f3a73172c717c3ba7d8dd775bf6fa3 000fc094 00000130 d7f3a73172c617c0b1548af962ab 000fc1c4 00000090 d7f3a73172c617c0b15480ed76aa45a4de4437 000fc254 0000000c d7f3a73172fc3ce78154acd9 000fc260 00000038 d7f3a73172f137ff804eb7cc46 000fc298 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fc2a0 00000048 d7f3a73172dc1cc7a1548fe963ab 000fc2e8 0000000c d7f3a73172d61ec1a66eb7ef76ba7f 000fc2f4 00000080 d7f3a73172da02cbbb548fe963ab 000fc374 00000050 d7f3a73172c213c7a1548fe963ab 000fc3c4 0000005c d7f3a73172c213c7a1548fe963ab45b2c65c3710 000fc420 0000002c d7f3a73172d213dab0549fe97eba 000fc44c 00000030 d7f3a73172d615cfa16eb7e179a76e 000fc47c 0000002c d7f3a73172d615cfa16eb7eb7ba169a3 000fc4a8 00000040 d7f3a73172d615cfa16eb7e767ab74 000fc4e8 00000020 d7f3a73172d615cfa16eb7ff76a76e 000fc508 0000001c d7f3a73172d615cfa16eb7e076bd45b1ce5826118351 000fc524 0000000c d7f3a73172fc3ce78154acd9 000fc530 0000001c d7f3a73172f03cff804eb7cc46 000fc54c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fc554 00000210 f7d3871172d41ec2ba68b7f865a179a3dc420d078543dbe36b 000fc764 00000070 f7d3871172d606d68a6286e163 000fc7d4 00000128 f7d3871172dc1cc7a15498fb74ac 000fc8fc 000002c8 f7d3871172d600cbb47f8dd767bc75a5ca42211182 000fcbc4 00000278 f7d3871172c617da8a7f81e572 000fce3c 000005a8 d7f3a73172d01cdaa772 000fd3e4 0000039c d7f3a73172c51ddda15485e164ba 000fd8e8 00000024 d7f3a73172f137e29c45a3d7539f 000fd90c 0000001c d7f3a73172f03cff804eb7cc46 000fd928 0000001c d7f3a73172f93be09e54acd9 000fd944 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fd94c 00000120 f7d3871172c117c3a5649ae965b745a7c35d3d17 000fda6c 0000014c d7f3a73172d41ec2ba6889fc72917baac6563c1195 000fdbb8 000000d0 d7f3a73172d41ec2ba6889fc72 000fdc88 00000124 d7f3a73172d117cfb96787eb76ba7f99c2543f 000fddac 00000078 d7f3a73172d613dca36eb7e572a375b4d6 000fde24 00000070 d7f3a73172d41ec2ba68b7e964ab77 000fde94 00000060 d7f3a73172d41ec2ba68b7e966bb7f 000fdef4 00000050 d7f3a73172d41ec2ba68b7ea66bb7f 000fdf44 00000060 d7f3a73172d41ec2ba68b7fb72a3 000fdfa4 00000070 d7f3a73172d41ec2ba68b7fc7ea37fb4 000fe014 0000013c d7f3a73172c21ddcb15492ed65a145b1c6453a2b9541daf2 000fe150 0000000c d7f3a73172fc3ce78154acd9 000fe15c 00000038 d7f3a73172f137ff804eb7cc46 000fe194 0000001c d7f3a73172f03cff804eb7cc46 000fe1b0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fe1b8 000000c0 d7f3a73172c517dcbc648ce1749169a5c75436019d47 000fe278 00000078 d7f3a73172c517dcbc648ce1749173a8c645 000fe2f0 00000108 d7f3a73172c517dcbc648ce174916ab4c052370782 000fe3f8 00000000 d7f3a73172c500c1b66e9bfb48ab74b2dd48 000fe45c 00000000 d7f3a73172d61dc0a16e90fc48bd6dafdb523a 000fe4e4 00000000 d7f3a73172d91dcfb1548be779ba7fbedb 000fe58c 00000000 d7f3a73172db07c2b9549aed63bb68a8 000fe590 00000000 d7f3a73172c602c7bb549fe97eba 000fe5dc 00000000 cdf49017408346 000fe604 00000000 cdf4970048d8449a 000fe62c 00000000 cdf4861b5b8346 000fe6d0 00000000 cdf4971644c3449a 000fe794 00000000 f1ca920658c717f1a06581fc64ba7bb2 000fe7e0 00000000 fcce9a06728640 000fe7fc 00000000 fcce9a0672c01cc7a1 000fe8e8 00000000 e7c58b0672db1dda8a6486e47ea07f 000fe914 00000000 f1ca920658c717f1a36484fb63af6e 000fe920 00000000 fcce9a0672c31dc2 000fe9d0 00000000 fcc4962d5bda1e 000fe9f8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 000fea00 00000478 f7d3871172c200c7a16eb7ea76ba 000fee78 0000007c f7d3871172c617daa07bb7ea76ba 000feef4 000000c0 f7d3871172c506cbb25489ec73bc7fb5dc 000fefb4 00000174 d7f3a73172d61ecbb479b7f863ab69 000ff128 0000026c d7f3a73172d707c7b96fb7f863ab69 000ff394 00000208 f7d3871172dc1cc7a16289e47eb47f99cd502607 000ff59c 0000012c d7f3a73172d416c4a0789cd764be68afdb540d03984cdce76f4d 000ff6c8 000000dc d7f3a73172c617da8a6a8beb72bd6999c65f0d048547 000ff7a4 0000021c f7d3871172c617daa07bb7fb76ba 000ff9c0 0000036c d7f3a73172d61acbb660b7e576be6aafc156 000ffd2c 00000178 d7f3a73172d110c98a6a8bfc7eb87f 000ffea4 000001e0 d7f3a73172d110c98a6286e974ba73b0ca 00100084 00000148 d7f3a73172c502cd8a6685fd48a774afdb 00100214 00000024 d7f3a73172f137e29c45a3d7539f 00100238 00000038 d7f3a73172f137ff804eb7cc46 00100270 0000001c d7f3a73172f03cff804eb7cc46 0010028c 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001002a4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001002ac 00000080 d7f3a73172c611c68a798dfb62a37f 0010032c 000000cc d7f3a73172c611c68a798dfb62a37f99dd443c2b9f47c0fc 001003f8 000000cc d7f3a73172c611c68a6984e774a5 001004c4 00000090 d7f3a73172c611c68a7f81e572aa45a4c35e311f 00100554 00000074 d7f3a73172d11df1a5798ded7abe6e99c758351c 001005c8 000000f0 d7f3a73172d11df1a5798ded7abe6e99c35e25 001006b8 0000000c d7f3a73172fc3ce78154acd9 001006c4 00000024 d7f3a73172f137e29c45a3d7539f 001006e8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001006f0 00000044 d7f3a73172dc1cc7a1549bed7a 00100734 00000024 d7f3a73172c717ddb07fb7fb72a3 00100758 000000e8 d7f3a73172c61bc9bb6a84d764ab77 00100840 00000024 d7f3a73172c117dda1549bed7a 00100864 00000038 d7f3a73172c213c7a1549bed7a 0010089c 00000038 d7f3a73172c213c7a1549aed64ab6e99dc543f 001008d4 0000003c d7f3a73172c213c7a1549aed64ab6e99dc543f2b854bd5ed7c 00100910 0000003c d7f3a73172c213c7a1549bed7a916eafc25436 0010094c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00100954 00000060 fcdd8f1740d602d7 001009b4 00000004 f7d3871172c60bc0b663b7ee62a07999ce52392b9243d4e47a5f4469 001009b8 0000007c d7f3a73172c11bc3b0549bf179ad45afc15826 00100a34 00000088 d7f3a73172dc1cc7a1549ce76e9179aac05239 00100abc 00000114 d7f3a73172d61dc0a36e9afc48ba7599df41312b854bd5ed 00100bd0 000003fc d7f3a73172d61dc0a36e9afc48af69a5c6580d009e7ddae1764a4e6f 00100fcc 0000017c d7f3a73172c717cfb1549ce76e9179aac05239 00101148 000001cc d7f3a73172d61dc0a36e9afc48a868a9c26e2204927dcce1755b 00101314 00000210 d7f3a73172d61dc0a36e9afc48ac73a8db583f2b854de7e96b5d4e6b 00101524 00000340 d7f3a73172c002cab47f8dd763a16399cc5d3d179a 00101864 00000354 d7f3a73172c617da8a7f81e572 00101bb8 00000160 f7d3871172c11bc3b0549bf179ad7299c9443c17 00101d18 000000ac d7f3a73172d217da8a7f81e572 00101dc4 0000017c d7f3a73172c60bdda16e85d763a779ad 00101fa4 00000024 d7f3a73172f137e29c45a3d7539f 00101fc8 00000038 d7f3a73172f137ff804eb7cc46 00102000 0000001c d7f3a73172f03cff804eb7cc46 0010201c 0000001c d7f3a73172f93be09e54acd9 00102038 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00102040 00000150 d7f3a73172d61acbb660b7fc7ea37fb4f04027118447 00102190 00000014 d7f3a73172dc1ccfb67f81fe76ba7f99db583f1183 001021a4 00000034 d7f3a73172dc1cc7a1549ce17aab68 001021d8 000000dc d7f3a73172c606c1a5549ce17aab68 001022b4 00000128 d7f3a73172c606cfa77fb7fc7ea37fb4 001023dc 000000e4 d7f3a73172d11bddb46984ed48b97bb2cc59361b96 001024c0 00000024 d7f3a73172c213dab6638ce7709169b2ce4537 001024e4 00000138 d7f3a73172c717cbbb6a8ae472916da7db523a109e45 0010261c 0000003c d7f3a73172c717ddb07fb7ff76ba79aecb5e35 00102658 00000134 d7f3a73172c606cfa77fb7ff76ba79aecb5e35 0010278c 0000000c d7f3a73172fc3ce78154acd9 00102798 0000001c d7f3a73172f03cff804eb7cc46 001027b4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001027bc 00000060 fcdd8f1740d602d7 0010281c 00000208 d7f3a73172c717cfb15485e979bb7c99ca5422069e4fe7ec794a46 00102a24 0000016c f1c48c0142d917f1a76e89ec48be68afc1450d129d43dffb 00102b90 00000208 f1c48c0142d917f1a76e89ec48aa7fa4da560d129d43dffb 00102d98 00000248 f1c48c0142d917f1a76e89ec48b96da8 00102fe0 000000ac f1c48c1444c71ff1a57987ec62ad6e99dc52200193 0010308c 000000c4 f1c48c1444c71ff1b66a8be0729169a5dd4430 00103150 00000300 f1c48c0142d917f1a47e8dfa6e 00103450 0000020c f5ce962d42c506c7ba659b 0010365c 000000f0 e2d98b1c59ea10c28a6286ee78 0010374c 0000007c f0de8b1e49ea1ec1b66a84d767a175aa 001037c8 00000664 d7f3a73172dc1cc7a15498f874 00103e2c 0000000b d1e4ac3464e73ff19c45b8dd439d 00104b20 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00104b28 00000024 d7f3a73172dc1cc7a15489fb72a3 00104b4c 0000003c d7f3a73172c61bc9bb6a84d776bd7fab 00104b88 00000024 d7f3a73172c117dda15489fb72a3 00104bac 0000000c d7f3a73172fc3ce78154acd9 00104bb8 00000038 d7f3a73172f137ff804eb7cc46 00104bf0 0000001c d7f3a73172f03cff804eb7cc46 00104c0c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00104c14 00000044 d7f3a73172dc1cc7a15489f9 00104c58 00000020 d7f3a73172c717cdb0629eed48af6b 00104c78 00000044 d7f3a73172c617c0b15489f9 00104cbc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00104cc4 00000098 f7d3871172c013dca15481fb65 00104d5c 00000084 f7d3871172d117c8b47e84fc48bd79aff059331a954eddfa 00104de0 00000230 f7d3871172d11bdda56a9ceb7f9169abc6 00105010 000000c0 f7d3871172c61fc78a689ae964a645aece5f36189450 001050d0 00000248 f7d3871172dd13c0b1678dd77aaf79aec65f372b924addeb73 00105318 00000078 f7d3871172d117c8b47e84fc48ab62b2ca433c159d7dd1e66c5b5570512f61 00105390 00000088 d7f3a73172dd13c0b1678dd772b66ea3dd5f3318ae4bd6fc7d4c5577542b 00105418 00000338 d7f3a73172d600cfa663b7ec7ebc7fa5db5e20 00105750 000001b8 f7d3871172dd13c0b1678dd767bc75a1dd503f 00105908 00000068 d7f3a73172c500c1b66e9bfb48ab62a5ca41261d9e4c 00105970 00000060 f7d3871172d811de8a689ae964a645aece5f36189450 001059d0 00000044 f7d3871172c602dcbc7f8dd77aad6a99c7503c109d47ca 00106734 000004dc f5ce9601 00106c14 0000006c e1c88c1b43d117d6 00106c80 00000788 f6c4bd014ed41cc8 00107408 00000080 e1c8831c4b 00107488 00000064 e1d8811343d3 001074ec 00000040 e1df90114cc1 0010752c 000000a8 e1df901c4ed802 001075d4 0000000c d7f3a73172fc3ce78154acd9 001075e0 00000038 d7f3a73172f137ff804eb7cc46 00107618 0000001c d7f3a73172f03cff804eb7cc46 00107634 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0010764c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00107654 00000c40 f6c4852d40dc01da8a6885ec 00108294 00000268 f6c4852d49dc13c98a788dfa61a779a3dc 001084fc 00000078 f6c4852d1cc606f1b16e8bd77ea06e99c7503c109d47ca 00108574 00000120 d6e2a33572f931ea8a4caddc489e2896f0631727a16df6db5d 00108694 0000142c d6e4a52d40dc01daad67 0010a5ac 00000038 d7f3a73172f137ff804eb7cc46 0010a5e4 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0010a5fc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0010a604 00000060 fcdd8f1740d602d7 0010a664 00000048 fcdd8f1740c617da 0010a6ac 0000009c d6e4a52d5ec11ddcb0548ce164be7bb2cc59 0010a748 0000009c d6e4a52d5fd001daba798dd773a769b6ce45311c 0010a7e4 000000a8 d6e4a52d5ec11ddcb05498f874916ca3cc45 0010a88c 000000e8 d6e4a52d5fd001daba798dd767be7999d9543100 0010a974 00000028 d6e4a52d5edb13dab663b7e574be45a2c64222158541d0 0010a99c 0000003c d6e4a52d5fd001daba798dd773a17d99da5f370c817dd5eb6861436b572f746f7a12 0010a9d8 00000028 d6e4a52d5edb13dab663b7ed6fba45a2c64222158541d0 0010aa00 0000003c d6e4a52d5fd001daba798dd773a17d99da5f370c817dddf06c61436b572f746f7a12 0010aa3c 00000028 d6e4a52d5edb13dab663b7fb7aa745a2c64222158541d0 0010aa64 0000003c d6e4a52d5fd001daba798dd773a17d99da5f370c817dcbe57161436b572f746f7a12 0010aaa0 00000064 d6e4a52d5fd001daba798dd773a17d99da5f370c817ddce16b4e46764737 0010ab04 0000011c d6e4a52d5edb13dab663b7f867ad45b0ca5226 0010ac20 0000007c d6e4a52d5fd001daba798dd773a17d99da5f370c817dc8f87b615167472b 0010ac9c 000004bc f4c4901f4cc12dcca06fb7ec7ebd6aaace48 0010b158 00000054 f6c4852d4bd92dddb6798ded799178bfdb54212b9f47ddec7d5a 0010b1ac 0000002c d6e4a52d55c100f1b8788fd775b76ea3dc6e3c119446ddec 0010b1d8 000004ec d6e4a52d4bd92dddb6798ded79916ab4ca41 0010b6c4 0000019c f6c4852d4ad006f1b2679ded48bc7fb5ca450d1d9f 0010b860 0000003c d6e4a52d5dc71bc0a1549ced64ba45abca4221159647 0010b89c 00000074 d6e4a52d59c113f1a57981e663 0010b910 00000058 f6ccbd025fdc1cda 0010b968 0000009c d6e4a52d5ed404cb8a689dfa65ab74b2f0453707857dcbfc794a5271 0010ba04 00000024 d6e4a52d5fd001daba798dd767bc7fb0c65e2707ae56ddfb6c615476452b6068 0010ba28 00000078 d6e4a52d5ec216f1a76e8ae778ba45b2c758212b8547cbfc4750526f 0010baa0 00000028 d6e4a52d4bc717cb8a699dec 0010bac8 00000050 d6e4a52d4ad006f1b77e8c 0010bb18 00000430 d6e4a52d48c700f1a77b9c 0010bf48 0000150c f6c4852d58db17d6a5548dfa65a16899c7503c109d47ca 0010d454 00000058 f6c4852d58db17d6a55485eb679173b5dd 0010d4ac 00000058 f6c4852d58db17d6a5548df063916aa3dd570d1d8250 0010d504 00000110 f6c4852d58db17d6a5548ced749173b5dd 0010d614 00000058 f6c4852d58db17d6a5549be57e9173b5dd 0010d66c 000000a0 f6ce841358d906f1b7629bfc48be7bb5dc 0010d70c 00000754 d6e4a52d49dc13c98a7f8dfb63917fbeca52 0010de60 000000ac f6ce841358d906f1b7629bfc48ad6eaadd 0010df0c 00000040 d6e4a52d4edd17cdbe548ee765916aa9d854202b8452e7fa7d4d4276 0010df4c 0000001c d6e4a52d44c62dccb47f9ced65b745a2c64233169d47dc 0010df68 00000050 d6e4a52d5ed404cb8a7881f848a77499c14720159c 0010dfb8 0000005c d6e4a52d5fd001daba798dd764a76a99c9433d19ae4ccefa7953 0010e014 00000164 f6c4852d5ec713c38a6d87fa74ab45b6ce433b00887dd1e66c 0010e178 00000030 f6c4852d48c317c08a7b89fa7eba63 0010e1a8 000001d8 f6c4852d5ec713c38a7c9ae163ab45b4ca50362b8547cbfc 0010e380 000000a8 d6e4a52d5ec713c38a7f8dfb63 0010eebc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0010eec4 000000b0 f6c2831555d92dc7bb629cd763af79aedc 0010ef74 000000b4 e0db962d4ed315f1a76fb7ed65bc 0010f028 000000b4 e0db962d4ed315f1b0799a 0010f0dc 00000824 f6c2831572dc1cc7a1549ce974a6 0010f900 0000002c f6c2831572dc1cc7a1549ce974a645f6 0010f92c 0000002c f6c2831572dc1cc7a1549ce974a645f7 0010f958 0000002c f6c2831572dc1cc7a1549ce974a645f4 0010f984 0000002c f6c2831572dc1cc7a1549ce974a645f5 0010f9b0 0000002c f6c2831572dc1cc7a1549ce974a645f2 0010f9dc 0000002c f6c2831572dc1cc7a1549ce974a645f3 0010fa08 0000002c f6c2831572dc1cc7a1549ce974a645f0 0010fa34 0000002c f6c2831572dc1cc7a1549ce974a645f1 0010fa60 0000002c f6c2831572dc1cc7a1549ce974a645fe 0010fa8c 0000002c f6c2831572dc1cc7a1549ce974a645ff 0010fbb4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0010fbbc 00000148 e6ca811a72c602dcbc7f8dd767ab68a0f0582106 0010fd04 00000038 c6eaa13a72c213c7a1548ee7659168a3c85821009450e7fe79525267 0010fd3c 00000084 c6eaa13a72dc06dc8a798dfb72ba 0010fdc0 000000e0 c6eaa13a72c61dc8a1549aed64ab6e 0010fea0 00000194 e6ca811a72d113dab45484e179ab6999db542100 00110034 000000e8 c6eaa13a72d61edc8a6c84fd729168a3dc54262b934bcc 0011011c 000000e8 c6eaa13a72c617da8a6c84fd729168a3dc54262b934bcc 00110204 0000026c c6eaa13a72dd13dcb1549aed64ab6e99cc5e3c129845cdfa7d 00110470 000002b8 c6eaa13a72d61edc8a6c8ae174917babcd54202b9d47dcd77a5753 00110728 000002b8 c6eaa13a72c617da8a6c8ae174917babcd54202b9d47dcd77a5753 001109e0 000002dc c6eaa13a72d61edc8a788ef848a27bb5ca430d169856 00110cbc 000002dc c6eaa13a72c617da8a788ef848a27bb5ca430d169856 00110f98 000001a8 c6eaa13a72d217da8a788ef848a27bb5ca430d078543ccfd6b 00111140 00000160 c6eaa13a72d01ccf8a6c84fd729169abc66e301d85 001112a0 00000160 c6eaa13a72d11bdd8a6c84fd729169abc66e301d85 00111400 00000160 c6eaa13a72c243cd8a6c84fd729169abc66e301d85 00111560 00000d48 e6ca811a72dc1cdab0799afd67ba45aece5f36189450 001122a8 00000160 c6eaa13a72d01ccf8a6c84fd729177a5df6e301d85 00112408 00000160 c6eaa13a72d11bdd8a6c84fd729177a5df6e301d85 00112568 000000c4 c6eaa13a72d61acbb660b7fa72a945b5db50260182 0011262c 00000090 c6eaa13a72d61acbb660b7f272bc7599c95c0d18984cd3d76b4a4676512c 001126bc 0000005c c6eaa13a72dc1cc7a1549bee64917ca5f05937159547cad76b4a5577472b 00112718 00000498 e6ca811a72c614dd8a6887e567af68a3f05327129747cafb 00112bb0 0000006c c6eaa13a72c200c7a16eb7e572a345b7da5036 00112c1c 00000060 e6ca811a72d31bc2b9548dfa66917fa8db432b 00112c7c 00000060 e6ca811a72d31bc2b9549bee66917fa8db432b 00112cdc 00000060 e6ca811a72d31bc2b95481e566917fa8db432b 00112d3c 000000c0 e6ca811a72d707c7b96fb7fb72a07e99dd54232b907dcbee6b614e7046 00112dfc 00000198 c6eaa13a72dc1cc7a15487fd63ac45a2ce45332b9357deee7d4c 00112f94 00000658 e6ca811a72c61fcd8a648eee7ba774a3f0523d199c43d6ec 001135ec 000006b4 c6eaa13a72c716f1a66d8ed764ab68afce5d0d1d957ddce96c5f 00113ca0 0000061c c6eaa13a72c500c7bb7fb7fb71a845b5ca433b159d7dd1ec475a467645 001142bc 00000e14 e6ca811a72c717c9bc789ced659168a3ce550d03834bcced4757496b5000617e6a0e 001150d0 00000308 c6eaa13a72dc1cc7a1549aed70bd 001153d8 00000144 e6ca811a72d117c8b47e84fc48ba7ba5c7483d1aae50ddef474d4276512f 0011551c 0000056c e6ca811a72db02f1b96487f875af79adf045370785 00115a88 00000034 e6ca811a72dc1ecc8a6598d77ea073b2c6503e1d8b43cce177507876412c61 00115abc 00000800 e6ca811a72c61fcd8a6286e163a77baac64b3300984dd6d77b514a6f453171 001162bc 000000a8 e6ca811a72dc1ecc8a6a84d77ea073b2c6503e1d8b43cce177507876412c61 00116364 0000004c e6ca811a72d01ecc8a6a84d77ea073b2c6503e1d8b43cce177507876412c61 001163b0 0000063c e6ca811a72dd1ecc8a6a84d77ea073b2c6503e1d8b43cce177507876412c61 001169ec 000009c8 e6ca811a72c614dd8a6a84d77ba175b6cd50311fae56ddfb6c 001173b4 00000088 e6ca811a72c614dd8a6a84d772b66eb4c16e3e1b9e52dae97b557876412c61442b11 0011743c 00000054 e6ca811a72c614dd8a6a84d772b66eb4c16e3e1b9e52dae97b557876412c61442811 00117490 00000068 e6ca811a72c614dd8a6a84d77ea06eb4c16e3e1b9e52dae97b557876412c61 001174f8 00000520 e6ca811a72d11fcf8a798cd760ba45b2ca4226 00117a18 00000cd8 e6ca811a72dc1cdab0799afd67ba45b2ca4226 001186f0 00000128 e6ca811a72dc1cdab07986e97b9178a3dd450d009451cc 00118818 00000144 e6ca811a72d00adab07986e97b9178a3dd450d009451cc 0011895c 0000035c e6ca811a72dc26fc8a6781e67c9177a9cb540d009451cc 00118cb8 0000006c e6ca811a72d717dca1548ae164ba45b2ca42262bc0 00118d24 00000388 e6ca811a72dc26fc8a7c9ae9679177a9cb540d009451cc 001190ac 0000006c e6ca811a72d717dca1548ae164ba45b2ca42262bc3 00119118 000002a8 e6ca811a72c617daa07b 001193c0 000006e8 f6c2831555d92ddab46880f178a045b2ca422607 00119aa8 000000b0 c6eaa13a72c707c0a16285ed 0011a920 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0011a928 00000244 f6c2831572d01bde8a6286e163 0011abac 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0011abb4 00000290 f6c2831555d92dcfb967b7fc76ad72bfc05f212b8547cbfc 0011ae44 000006fc c6eaa13a72d31ddcb86a9cd771ad45afdd400d0c8550e7fb6c5f537757 0011b540 00000048 c6eaa13a72dc1cc7a1549bed64ba45a0cc6e3a119046ddfa474d5370513c61 0011b588 000000e4 c6eaa13a72dc1cc7a1549bed64ba45a9da45302b9543cce9475c5264423a6744690ae5 0011b66c 00000524 c6eaa13a72c614dd8a6887e567af68a3f05327129747cafb 0011bb90 000002e0 c6eaa13a72c617dda1548be77abe7bb4ca6e30019744ddfa6b 0011be70 000000e0 c6eaa13a72d707c7b96fb7fa72bf45a7f0423407ae4bcaea 0011bf50 000000a8 c6eaa13a72d707c7b96fb7fa72bf45b5ca42262b9850da 0011bff8 000000c8 c6eaa13a72d707c7b96fb7fb72bd6e 0011c0c0 00000090 c6eaa13a72d31bc2b95481e566917fa8db432b 0011c150 00000238 c6eaa13a72d117c8b47e84fc48ba7ba5c7483d1aae50ddef474d4276512f 0011c388 00000080 c6eaa13a72d31bc2b9549bee66917fa8db432b 0011c408 00000090 c6eaa13a72d31bc2b9548dfa66917fa8db432b 0011c498 000007d0 c6eaa13a72c61fcd8a6286e163a77baac64b3300984dd6d77b514a6f453171 0011cc68 0000071c c6eaa13a72c61fcd8a648eee7ba774a3f0523d199c43d6ec 0011d384 0000004c c6eaa13a72c717deba799cd771af73aaca550d049e50cc 0011d3d0 00000e90 e6ca811a72ea2dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e260 00000024 e6ca811a72852dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e284 00000024 e6ca811a72842dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e2a8 00000024 e6ca811a72872dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e2cc 00000024 e6ca811a72862dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e2f0 00000024 e6ca811a72812dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e314 00000024 e6ca811a72802dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e338 00000024 e6ca811a72832dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e35c 00000024 e6ca811a72822dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e380 00000024 e6ca811a728d2dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e3a4 00000024 e6ca811a728c2dc7bb7f8dfa65bb6ab2f059331a954eddfa 0011e3c8 00000cd4 e6ca811a72c617dda15489e448a275a9df5333179a7dcced6b4a 0011f09c 0000006c e6ca811a72c617dda15489e448a774b2dd5f0d189e4dc8ea795d4c5d503a666f464bb00e 0011f108 000000ac e6ca811a72c617dda15489e448ab62b2dd5f0d189e4dc8ea795d4c5d503a666f464bb00e 0011f1b4 000000ac e6ca811a72c617dda15489e448ab62b2dd5f0d189e4dc8ea795d4c5d503a666f464bb00ee3c51b 0011f260 00000ca4 e6ca811a72c614dd8a6a84d77ba175b6cd50311fae56ddfb6c 0011ff04 00000068 e6ca811a72c614dd8a6a84d77ea06eb4c16e3e1b9e52dae97b557876412c61 0011ff6c 00000054 e6ca811a72c614dd8a6a84d77ea06eb4c16e3e1b9e52dae97b557876412c61442811 0011ffc0 0000009c e6ca811a72c614dd8a6a84d772b66eb4c16e3e1b9e52dae97b557876412c61442b11 00120514 00000028 d7f3a73172e233e78154bcc15a8b5e 0012053c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00120544 00000040 f5ce962d40dc00dcba79b7ea7aaf7f 00120584 00000034 f5ce962d5dc71bc3b47991d775a37ba3 001205b8 00000008 f5ce963b63e331ef 001205c0 00000008 f5ce963f44c700c1a742a6de548f 001205c8 00000084 dbe2a12d6ef43eed8a4fa1c55a91498ff574 0012064c 00000060 dbe2a12d7bf020e79352b7cc5e835799ec791737ba71edc5 001206ac 000001f0 e2d98b1c59ea01cfa36e8cd77ebd6899dc4533008451 0012089c 0000019c e2d98b1c59ea0af1a67b9aeb73ac45b4ca5621 00120a38 00000018 f6c2912d5ec216 00120a50 0000020c f6c2831572c602dc8a7891fb48bd7bb0ca6e3b1a9856 00120c5c 000000bc f6c2831572c602dc8a7891fb48bc7fb5db5e2011 00120d18 00000130 f6c2831572c602dcbc7f8dd77ea073b2c6503e1d8b43cce17750 00120e48 00000264 d6e2a33572c602dcbc7f8dd764ab6e99c755252b9c43c8d76e5f4b77412c 001210ac 00000140 f6c2831572c602dcbc7f8dd77aad6a99c7503c109d47ca 001211ec 000001b4 f6c2831572c602dcbc7f8dd767a774b2f059331a954eddfa 001213a0 000000b8 f6c2831572c602dcbc7f8dd767ab68a0f059331a954eddfa 00121458 00000134 d6e2a33572c602dcbc7f8dd774a27fa7dd6e3a159d56e7eb7750436b50367a75 0012158c 000007a8 d6e2a33572c602dcbc7f8dd772bc6899c7503c109d47ca 00121d34 000000ec f6c2831572c602dcbc7f8dd764a37399c7503c109d47ca 00121e20 00000218 d6e2a33572c617c28a7898fa7eba7f99c65f262b9e57cc 00122038 00000170 e1db902d49dc01cfb7678dd775af68b5 001221a8 00000104 e1db902d5fd001daba798dd775af68b5 001222ac 000001b4 f6c2831572c617da8a6f8ae963bd45f3f05f0d42 00122460 0000012c f6c2831572c717dda1649aed48aa78a7db420d41ae4ce7be 0012258c 00000068 f6c2831572c613d8b0548ce164af78aaca6e2204927ddbe97b564e6c43007179780eb3 001225f4 00000054 f6c2831572c717dda1649aed48aa78a7db04 00122648 00000130 f6c2831572c617da8a6f8ae963fb45a0c0430d038246d9 00122778 000000bc f6c2831572c717dda1649aed48aa78a7db040d159756ddfa474954664500617e6a0e 00122834 000000dc e1db902d48c700f1a77b9c 00122910 000002f4 f6c2831572d21edbb0548de676ac76a3f05c3104 00122c04 000003f8 d6e2a33572d217c0b07989fc729169b6dd582611ae47dbeb475b55704b2d 00122ffc 00000060 f1ca8e1172d61acbb6608ae163 0012305c 00000058 f1ca8e1172d610 001230b4 00000030 f1c3871146d71bdaa6 001230e4 0000009c e6d9831c5ed913dab05489ec73bc45a5c203220492 00123180 00000090 e6d9831c5ed913dab05489ec73bc45b6df5260179c 00123210 00000054 f5ce962d5ed404cbb15489e772 00123264 00000074 e5d98b0648ea02cfa17f8dfa79 001232d8 00000118 e0ce831672d61dc3a56a9aed48be7bb2db54201a 001233f0 00000048 f6c2831572c500c1a16e8bfc48ad7799dc5822 00123438 0000006c d6e2a33572c313c2bc6fb7eb7a9169afdf 001234a4 000001f0 d6e2a33572c602dc8a6f85e948ad77a2 00123694 00000144 d6e2a33572c213c7a1548ee7659169b6dd582611 001237d8 00000050 d6e2a33572dc01f1b666b7e1799169a3c3570d069444caed6b56 00123828 000000c4 d6e2a33572c617da8a6885d77ea045b5ca5d342b8347defa7d4d4f 001238ec 00000450 d6e2a33572c717ddb07fb7fb67bc73b2ca 00123d3c 00000104 d6e2a33572d217da8a6a8cec659174a3d7450d0e9450d7ed7c615461403d 00123e40 00000444 d6e2a33572d217c0b07989fc729169b6dd582611ae47cafa774c 00124284 000003c0 d6e2a33572d61ff1b66698d767ac6fa0f05e202b8241cafd7a 00124644 00000140 d6e2a33572d61ff1a27981fc72916aa7db4537069f 00124784 00000158 d6e2a33572d61ff1a66e9cd767ac6fa0f04133008547cae6 001248dc 00000150 f6c2831572c602dc8a789cfd74a545a3dd433d06ae41d0ed7b55 00124a2c 000005f0 f6c2831572c602dc8a7b98eb48ac6fb5f0433713ae56ddfb6c 0012501c 000002f8 f6c2831572c602dc8a7cb7fa48bc7fa1f045370785 00125314 00000130 f6c2831572c502cd8a6e86e948822b99e3030d049050d1fc61 00125444 00000a80 f6c2831572c602dc8a6e90fc65af79b2f0553606ae52d9fa79534276412d66 00125ec4 0000043c f6c2831572d61ff1b66383d774a174a0c656 00126300 00000138 f6c2831572d61dcab06787e9739168a3dc483c17ae4bd6e16c 00126438 000003d8 f6c2831572c602dc8a6a8beb72bd6999cb583f1982 00126810 00000e98 d6e2a33572d61dc0b3628ffd65ab45b5df433b0094 001276a8 0000051c f6c2831555d92dcdb8549bf865a76ea3f04537078551 00127bc4 00000070 f6c2831572c602dc8a688eef48ad72afdf 00127c34 00000328 d6e2a33572c317dcbc6d91d764be68afdb540d179e4cdee17f4b556350367a75 00127f5c 00000154 d6e2a33572c717ddb07fb7eb78a07cafc86e2104834bcced 001280b0 000000c4 f6c2831572c602dc8a7d8dfa7ea86399cc5735 00128174 00000e44 f6c2831572d61ff1b4688bed64bd45b5d56e26118256 00128fb8 000000bc f6c2831572d61ff1ba60b7fc78916db4c64537 00129074 000004c0 f6c2831572d61ff1a66286ef7bab45a4c6450d119241e7fc7d4d53 00129534 00000518 f6c2831572d61ff1b1649dea7bab45a4c6450d119241e7fc7d4d53 00129a4c 0000048c f6c2831572d61ff1b3649dfa48ac73b2f0543117ae56ddfb6c 00129ed8 000000ac f6c2831572d61ff1a57b8bd760bc73b2ca6e20119046e7fc7d4d53 00129f84 00000168 f6c2831572d61ff1b16285e548ab79a5f04537078551 0012a0ec 00000304 f6c2831572c602dc8a7b8dfa71a168abf0583c00ae56ddfb6c4d 0012a3f0 00000a78 f6c2831572c602dc8a6286fc72bc68b3df450d009451ccfb 0012ae68 00001ff8 f6c2831572c602dc8a6f85e948ab74a1c65f372b8547cbfc6b 0012ce60 00000800 f6c2831572c602dc8a788bfa62ac78afc1560d009451ccfb 0012d660 000001b4 d6e2a33572d61ff1a27981fc729168a3ce550d009451cc 0012d814 000000d8 f6c2831572d61ff1a66889e648ab79a5 0012d8ec 000003dc f6c2831572d61ff1a16e9bfc489857a8f07f04399f7ddbe97b5642 0012dcc8 000001d0 f6c2831572d61ff1b27987fd67917ba8cb6e26118256 0012de98 00000928 f6c2831572d61ff1b66a8be0729177a3c25e200dae56ddfb6c 0012e7c0 00000344 f6c2831572d61ff1a66e84ee48bc7fa0dd54211cae5acced6b4a 0012eb04 000005d0 f6c2831572d406c2b4659ce164917fa8ce533e11ae4fdbf8 0012f0d4 000000c8 d6e2a33572c617da8a7b98eb25ad7799dc5d3b10984cdfd76f5749664b28 0012f19c 00000124 f6c2831572d61ff1b0688bd763ab69b2dc 0012f2c0 00000438 f6c2831572d61ff1b16285e548af7ea2dd542107ae56ddfb6c 0012f6f8 000001bc e2d98b1c59ea17cdb6548ce963af 0012f8b4 0000009c e5ce842d4fd406da 0012f950 000000cc e5ce842d5dc62dcf 0012fa1c 000000cc e5ce842d5dc62dcc 0012fae8 000001d4 e5ce842d5dc62dcfb7 0012fcbc 0000014c e5ce842d4edd17cdbe548be5 0012fe08 0000001a f7d9902d40c615f1b2679ded48ad7bb3dc540d0793 0012fe24 0000001e f7d9902d40c615f1b47f84e979ba73b5f05233018247e7fb7a 0012fe44 00000026 f7d9902d40c615f1a5649fed65be7999cc502707947dd5eb 0012fe6c 00000017 f7d9902d40c615f1a57b8bd776aa78a3 0012fe84 0000001c f7d9902d40c615f1a7549fd765ab7d 0012fea0 00000018 f7d9902d40c615f1bc6784d773a777ab 0012feb8 0000001d f7d9902d40c615f1b66a86fc48ad7ca1 0012fed8 00000012 f7d9902d40c615f1b4788d 0012feec 00000023 f7d9902d40c615f1a66e8bd775af7e 0012ff10 00000022 f7d9902d40c615f1b778b7eb62aa7f 0012ff34 00000026 f7d9902d40c615f1b66e8bd775af7e 0012ff5c 0000001d f7d9902d40c615f1b46e84d775af7e 0012ff7c 0000002c f7d9902d40c615f1a0688dd779a145afc145 0012ffa8 00000021 f7d9902d40c615f1bc659cd779a145a2c642 0012ffcc 00000019 f7d9902d40c615f1bc659cd779a16e 0012ffe8 00000022 f7d9902d40c615f1b8629beb78a36aa7dd54 0013000c 00000026 f7d9902d40c615f1b16689d772bf45a3dd43 00130034 0000002a f7d9902d40c615f1b16689d779ab45a3dd43 00130060 00000022 f7d9902d40c615f1b16689d778be45a3dd43 00130084 00000024 f7d9902d40c615f1b16689d774ac45a3dd43 001300a8 0000002a f7d9902d40c615f1b16689d779a145aec345 001300d4 00000025 f7d9902d40c615f1a6689afd759179a2ca6e3415984e 001300fc 00000035 f7d9902d40c615f1a6689afd75916fa2ca6e3415984e 00130134 00000024 f7d9902d40c615f1a164b7e179917eb1c942 00130158 00000029 f7d9902d40c615f1b16689d775ad74b2f0533310 00130184 0000001c f7d9902d40c615f1b16285e548ac7ba2 001301a0 0000002a f7d9902d40c615f1a67c8cd778a045b5df43 001301cc 00000035 f7d9902d40c615f1a67c8cd77ea045b1dd6e20119651 00130204 00000029 f7d9902d40c615f1a67c8cd778a045a7cc52 00130230 00000022 f7d9902d40c615f1a67f9deb7c9173a8db42 00130252 000000c8 f7d9902d40c615f1b666b7fc72bd6e99dc453300 0013031c 0000001f f7d9902d40c615f1b666b7e973aa6899db542100 0013033c 00000017 f7d9902d40c615f1bb64b7ec7ea377b5 00130354 0000002b f7d9902d40c615f1b16285e5649174a3 00130380 00000020 f7d9902d40c615f1a66081f867ab7e99cc5e3c1a 001303a0 00000026 f7d9902d40c615f1e6548ce17aa36999c142 001303c8 00000021 f7d9902d40c615f1a0659bfd67be75b4db54362b9243dbe07d615478 001303ec 00000026 f7d9902d40c615f1b76a8cd764be7e99cc593907844f 00130414 00000027 f7d9902d40c615f1b76a8cd77ea77999dc4533008451 0013043b 000000d2 f7d9902d40c615f1b666b7fb72a27c99dd5434 00130510 00000190 e2d9872d5ec500c7a16edbd760bc73b2ca6e3f158249 001306a0 00000190 e1db901b59d041f1a27981fc729177a7dc5a 00130830 00000048 e1d28c165fda1fcba6549be179a976a3f0533b00ae47cafa6b 00130878 00000100 f1c9bd0a42c7 00130fb4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00130fbc 00000060 fcdd8f1740d602d7 0013101c 00000004 e1ce962d59dd17f1b66787eb7c 00131020 000000b4 f6c2831572c616cd8a6286e163a77baac64b3300984dd6 001310d4 0000027c f6c2831572c616cd8a6286fc48a67ba8cb5d3706 00131350 000000c4 e1cf812d48c700f1a77b9c 00131414 000000a4 f6c2831572dc1cdab0799afd67ba45b2c7540d079541 001314b8 00000164 f6c2831572c213c7a1548ee7659169a2cc 0013161c 000000a0 d6e2a33572c607cca17989eb639178afc1453b19 001316bc 00000060 d6e2a33572c616cd8a7889fe72916ea9d6 0013171c 00000060 d6e2a33572c616cd8a7889fe72916aa9d8542001817dcce761 0013177c 000000c4 d6e2a33572c616cd8a7889fe729178a7db450d078543cced 00131840 000001dc f6c2831572c616cd8a6889e474917ea9d85f0d00984fdd 00131a1c 00000144 f6c2831555d92dddb168b7fc72bd6eb5 00131b60 0000002c d6e2a33572c616cde77b80f164a779a7c36e30189e55ddfa4750526f 00131b8c 0000002c d6e2a33572c51ad7a6628be97bfc69a2cc6e30189e55ddfa4750526f 00131bb8 0000004c d6e2a33572c616cde77b80f164a779a7c36e30158556e7e66d53 00131c04 0000004c d6e2a33572c51ad7a6628be97bfc69a2cc6e30158556e7e66d53 00131c50 00000634 f6c2831572c616cd8a6887e57abb74afcc50261d9e4ce7fc7d4d53 00132284 00000258 f6c2831572c616cd8a7f8de567ab68a7db442011ae56ddfb6c 001324dc 00000134 f6c2831572c616cd8a798cd775a275b1ca430d049841 00132610 00000304 f6c2831572c616cd8a6984e760ab6899cc5937179a 00132914 000001f8 f6c2831572c616cd8a6984e760ab6899dc4533008451e7eb705b4469 00132b0c 00000120 f6c2831572c616cd8a6984e760ab6899db542100 00132c2c 0000026c f6c2831572c616cd8a798cd760bc6e99cd502600ae47ddf86a514a 00132e98 00000798 f6c2831572c616cd8a6989fc63917eafdc503018947ddde6795c4b677b2b70686d 00133630 00000154 f6c2831572c616cd8a6989fc639177a0c86e311c9441d3 00133784 00000158 f6c2831572c616cd8a6989fc639169b2ce452707ae41d0ed7b55 001338dc 000001a8 f6c2831572c616cd8a6989fc63916ea3dc45 00133a84 00000168 f6c2831572c616cd8a3adafe48be6999db542100 00133bec 0000000c f7d9902d40c615f1a66f8bd77ebd45b2c0502100 00133bf8 00000016 f7d9902d40c615f1a66f8bd77ea079a9c1423b078547d6fc 00133c10 00000016 f7d9902d40c615f1a66f8bd779a145afc14537068357c8fc 00133c28 00000025 f7d9902d40c615f1a66f8bd77ea06ea3dd432704857dd6e7475d4677573a 00133c50 0000001f f7d9902d40c615f1a66f8bd775af7e99db543f04 00133c70 00000023 f7d9902d40c615f1a66f8bd775af7e99ce47352b8547d5f8 00133c94 00000021 f7d9902d40c615f1a164b7e179916da0dc5531 00133cb8 00000019 f7d9902d40c615f1b77981eb7c917ca7c65d3710ae51dceb474a427150367b7c 00133cd4 0000001e f7d9902d40c615f1a66f8bd775af7e99dd413f 00133cf4 0000002b f7d9902d40c615f1a76e89ec7ea07d99cd5d3d039450e7fa7d4878744d3b 00133d20 00000019 f7d9902d40c615f1a66f8bd775af7e999e03041092 00133d3c 00000015 f7d9902d40c615f1a66f8bd760aa6ea9 00133d54 00000021 f7d9902d40c615f1b76a8cd775a275b1ca430d1d9841 00133d78 0000001e f7d9902d40c615f1b76a9cfc48ab74a7f04337079456e7ee79574b77563a 00133d98 00000024 f7d9902d40c615f1b76a9cfc48aa73b5f0533001877ddee97152527041 00133dbc 00000023 f7d9902d40c615f1b76a9cfc48aa73b5f0543117ae44d9e1744b5567 00133de0 00000027 f7d9902d40c615f1b76a9cfc48ab74a7f0533001877ddee97152527041 00133e08 00000026 f7d9902d40c615f1b76a9cfc48ab74a7f0543117ae44d9e1744b5567 00133e30 0000001f f7d9902d40c615f1b76a9cfc48bd6ea7c155300dae40dafd6e6141634d3360697c 00133e50 00000023 f7d9902d40c615f1b76a9cfc48bd6ea7c155300dae47dbeb4758466b482a677e 001343e8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001343f0 00000414 d6e2a33572c517dcbc648ce174916ea3dc4521 001349dc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001349e4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001349ec 000000b0 f6c2831555d92ddab03b 00134a9c 00000020 f6c2831555d92ddab0789cd726 00134abc 000001c4 f6c2831555d92ddcb07b87fa639169b4ce5c0d12904bd4fd6a5b 00134c80 0000001c f7d9902d40c615f1a67989e548ba7fb5db6e3415984eddec 00134c9c 00000024 f7d9902d40c615f1a67989e548be7bb4c6452b2b9647d6d77e5f4e6e413b 00134cf4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00134cfc 000002a0 f6c2831555d92ddee77bb7fc72bd6eb5 00134f9c 000010f8 e6ca811a72ea2dc7bb7f8dfa65bb6ab2f059331a954eddfa 00136094 00000024 e6ca811a728c2dc7bb7f8dfa65bb6ab2f059331a954eddfa 001360b8 00000024 e6ca811a728d2dc7bb7f8dfa65bb6ab2f059331a954eddfa 001360dc 00000024 e6ca811a72822dc7bb7f8dfa65bb6ab2f059331a954eddfa 00136100 00000024 e6ca811a72832dc7bb7f8dfa65bb6ab2f059331a954eddfa 00136124 00000024 e6ca811a72802dc7bb7f8dfa65bb6ab2f059331a954eddfa 00136148 00000024 e6ca811a72812dc7bb7f8dfa65bb6ab2f059331a954eddfa 0013616c 00000024 e6ca811a72862dc7bb7f8dfa65bb6ab2f059331a954eddfa 00136190 00000024 e6ca811a72872dc7bb7f8dfa65bb6ab2f059331a954eddfa 001361b4 00000024 e6ca811a72842dc7bb7f8dfa65bb6ab2f059331a954eddfa 001361d8 00000024 e6ca811a72852dc7bb7f8dfa65bb6ab2f059331a954eddfa 001361fc 00000040 e6ca811a72d61acbb660b7ee7a9176afc15a0d078543ccfd6b 0013623c 00000ab8 e6ca811a72c61fcd8a6286e163a77baac64b3300984dd6d77b514a6f453171446948f6 00136cf4 000012d4 e6ca811a72c540de8a6a84d77ba175b6cd50311fae4fd7e6714a4870 00137fc8 00000068 e6ca811a72c540de8a6a84d77ba175b6cd50311fae4fd7e6714a48707b2b70686d 00138030 00000e8c e6ca811a72c540de8a7f8dfa7aa774a7db54 00138ebc 000000c0 e6ca811a72c540de8a7f8dfa7aa774a7db540d009451cc 00138f7c 00001194 e6ca811a72c540de8a788dfb63917baaf05d3d1b8140d9eb73615367572b 0013a110 000000b4 e6ca811a72c540de8a788dfb63917baaf05d3d1b8140d9eb73615367572b4a2a2f11 0013a1c4 00000114 e6ca811a72c540de8a788dfb63917baaf05d3d1b8140d9eb73615367572b4a2a2f11d90bcf 0013a2d8 000010ac e6ca811a72c540de8a788efb48af7699c35e3d049343dbe3474a427150 0013b384 0000009c e6ca811a72c540de8a788efb48af7699c35e3d049343dbe3474a427150002770 0013baa0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0013baa8 000000b8 f6c2831555d92ddcb07db7fc72bd6e 0013bb60 00000110 d6e2a33572c717f1b6648ced7ba17ba2f0433702ae57c8ec794a42 0013bc70 000001fc d6e2a33572d61dcab06787e9739168a3d96e27049543cced 0013be6c 00000744 d6e2a33572d11bdda56789f148a67bb4cb463306947dcaed6e57546b4b314a72771ce9 0013c5b0 000002cc d6e2a33572d61dc0b3628ffd65ab45a5c754311f814dd1e66c614a6d402a797e 0013cf14 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0013cf1c 00000070 fdde960258c12dcdbd6a9ad77aaf74b3c95031008450d1e67f 0013cf8c 000000bc f3d8892d40d41cdbb36a8bfc62bc73a8c86e3511857dcce07d53 0013d048 0000018c f3d8892d40d41cdbb36a8bfc62bc73a8c86e3f1b9547 0013d1d4 000000bc f6c2831555d92dc6a2548be072ad71 0013d290 00000040 e2d98b1c59ea02dcb0788de6639177afdc423b1a96 0013d2d0 00000080 e2d8bd1145de 0013d350 00000168 fdc8922d4edd19 0013d4b8 00000354 f1c98b1172d017dea76485d774a671 0013d80c 00000498 e1cf812d48d002dcba66b7eb7fa5 0013dca4 000003dc fdc8922d48d002dcba66b7eb7fa5 0013e080 0000061c f5c7971772d017dea76485d774a671 0013f0b4 0000007c f5ce961145d400 0013f130 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0013f138 00000110 c2ecaf2d5ec113dca15481eb64be45abc05537 0013f248 000000fc c2ecaf2d5ec11dde8a628bfb679177a9cb54 0013f344 000000b4 c2ecaf2d5ed01cca8a6f89fc76 0013f3f8 00000050 c2ecaf2d5ed01cca8a6887fa729179abcb 0013f448 00000130 c2ecaf2d5ed01cca8a798de9739179abcb 0013f578 00000070 c2ecaf2d41da13ca8a7f89ea7bab45b6c0583c009450 0013f5e8 000000b8 c5d98b0648ea11c1bb6d81ef48bc7fa1 0013f6a0 00000080 c2ecaf2d4fc01ec58a6e9ae964ab 0013f720 000000ec c2ecaf2d5fd013ca 0013f80c 000000e8 c0ce831672d61dc0b3628fd765ab7d 0013f8f4 000003bc c2ecaf2d5ac71bdab05498fa78a968a7c2 0013fcb0 00000040 c2ecaf2d4ad006f1a5628bd773ab6cafcc540d1d95 0013fcf0 00000040 c2ecaf2d4ad006f1a5628bd760be 0013fd30 00000108 c2ecaf2d5ddc11f1b6648ced7ba17ba2 0013fe38 000001b4 c2ecaf2d59d001da8a6f8dfe7ead7f 0013ffec 000019e4 d6e2a33509f630e79654aadd5b854583fd700131 001419d0 00001c80 d6e2a33509f630e79654b8dd43914a94e0760035bc7dfad14c7b74 00143650 000014bc d6e2a33509f630e79654afcd43914a94e0760035bc7dfad14c7b74 00144b0c 000001bc c4ce901b4bcc2dedba6f8de478af7e 00144cc8 0000033c d1e9ab3172d61dcab06787e973 00145004 00000098 d1c4861772f91dcfb154bced64ba 00145744 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014574c 00000060 fcdd8f1740d602d7 001457ac 000000f0 c2ecaf2d4ad907cb8a7f89f848bc7fb5ca45 0014589c 00000104 c2ecaf2d49d01ecfac5484e778be 001459a0 000001a8 c2ecaf2d4ad907cb8a788de6739178bfdb5421 00145b48 000000fc c2ecaf2d4ad907cb8a619ce9709173a9 00145c44 0000006c c2ecaf2d4ad907cb8a619ce9709168a3dc54262b9846d4ed 00145cb0 00000158 c2ecaf2d4ad907cb8a6c87fc789170b2ce560d078543cced 00145e08 000000f0 c2ecaf2d4ad907cb8a788de6739179abcb6e251b8346 00145ef8 00000088 c2ecaf2d4ad907cb8a788de6739179a9c25c331a95 00145f80 00000074 c2ecaf2d4ad907cb8a788de673917ea7db50 00145ff4 00000178 c2ecaf2d4ad907cb8a798de973917ea7db50 0014616c 0000012c c2ecaf2d4ad907cb8a7c9ae163ab45a2ce4533 00146298 000002f0 c2ecaf2d4ad907cb8a6887e57aaf74a2f04237058447d6eb7d 00146588 00000040 c2ecaf2d4ad907cb8a6887ec72ad72a3cc5a 001465c8 000000c0 c2ecaf2d4ad907cb8a6887ec72a275a7cb 00146688 000000a4 c2ecaf2d4ad907cb8a6389fa73b97bb4ca6e260d8147 0014672c 00000080 c2ecaf2d4ad907cb8a6880ed74a576a9ce55 001467ac 00000444 c2ecaf2d55d92dc9b97e8dd774a67fa5c45d3d1595 00146bf0 000003e4 c2ecaf2d4ad907cb8a6d87fa74ab45b4ca5d3d1595 001475a8 00000028 d7f3a73172e233e78154bcc15a8b5e 001475d0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001475d8 0000008c fbc2812d44db06dcb47880ed7ba845b5db502601827ddced7b514367 00147664 00000184 fbc2812d4ed41ecd8a6880ed74a569b3c26e3b1a8550d9fb705b4b64 001477e8 000002b4 dbe5b6206ce63aeb994db7cf529a458fe1771d 00147a9c 00000288 dbe5b6206ce63aeb994db7d8429a458fe1771d 00147d24 000000e8 e0ce831e72d610c7b6548fed63916aafcc6e300d8547cb 00147e0c 000001f4 d1e9ab3172f237fa8a5ba1cb488c4392ea62 00148000 000000ec e0ce831e72d610c7b65498fd63916aafcc6e300d8547cb 001480ec 000001f4 d1e9ab3172e527fa8a5ba1cb488c4392ea62 001482e0 000000a0 d1e9ab3172e133e29e54bcc7488d5b88f07e1c 00148380 000000a0 d1e9ab3172e133e29e54bcc7488d5b88f07e1432 00148420 00000054 d1e9ab3172f237fa8a58a0cd5b884588fa7c 00148474 00000058 d1e9ab3172f237fa8a48a9ca48804f8b 001484cc 00000054 d1e9ab3172f237fa8a46a7cc42825f99fc651320a471 00148520 00000058 d1e9ab3172f237fa8a58a7ce43995b94ea6e0031a7 00148578 00000060 d1e9ab3172e527fa8a59add8589c4e8fe1760d33a36dedd84b 001485d8 00000030 d1e9ab3172e527fa8a58a0cd5b884596ee63062ba367e9 00148608 00000030 d1e9ab3172f237fa8a58a0cd5b884596ee63062ba163ffcd 00148638 00000030 d1e9ab3172e527fa8a4fbac1418b4584f6611327a2 00148668 00000060 d1e9ab3172f237fa8a4fbac1418b4584f6611327a2 001486c8 00000184 d1e9ab3172f237fa8a58a0cd5b884596ee63063db26be8c94c77684c 0014884c 00000178 d1e9ab3172f72bfe9458bbd7539c5390ea62 001489c4 0000000c d1e9ab3172e03cea9a54a3c658995499ed631d3fb46c 00148a08 00000028 d7f3a73172e233e78154bcc15a8b5e 00148a30 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00148a38 000001a4 c1efa12d44db1bda 00148bdc 00000068 c1efa12d44c600 00148c44 000000c4 c1efa12d79f03ffe8a629bfa 00148d08 000000cc c1efa12d7de642f1bc789a 00148dd4 000000cc c1efa12d7de643f1bc789a 00148ea0 0000024c c1efa12d5ed01cca8a6887e57aaf74a2 001490ec 000000e0 c1efa12d5fc22dcca7628be348a37fabc0432b 001491cc 00000080 e1cf812d4cd619 0014924c 00000314 e1cf812d5ed01cca8a6286fc48ba7599c75f361883 00149560 00000064 e1cf812d5fc22dc3b06687fa6e9179a9c2413e118547 001495c4 00000474 e1cf812d5fc22dc3b06687fa6e9179a7c35d30159249 00149a38 00000778 c1efa12d44db06f1bd658ce465 0014a460 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014a468 00000048 c1efa12d60fa3cf1bc6581fc 0014a4b0 00000190 c1efa12d60fa3cf1b26e9cd77ea07ca9 0014a698 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014a6a0 0000000c c1efa12d60fa3cf1974abcdc48a97fb2f0533300857dcbf16b615476452b70 0014a6ac 00000048 c1efa12d60fa3cf1974abcdc48a97fb2f0533300857dcbf16b615476452b70446a0ef40cd2cc 0014a6f4 000000d0 c1efa12d60fa3cf1974abcdc48a97fb2f05233179947e7f877524e615d00666f780ee3 0014a7c4 00000048 c1efa12d60fa3cf1974abcdc48a97fb2f05233179947e7f877524e615d00666f780ee33acfdf1a2df640 0014a80c 00000054 e1cf812d40da1cf1b76a9cfc48bb6aa2ce45372b9350d1eb73615476452b6068 0014a860 00000070 e1cf812d40da1cf1b76a9cfc48ad7baacc443e158547e7e06d4a 0014a8d0 0000007c e1cf812d40da1cf1b76a9cfc48bb6aa2ce45372b9957ccd76b4a467641 0014a94c 000000c0 e1cf812d40da1cf1b76a9cfc48a76999df433707944ccc 0014aa0c 000000e0 e1cf812d40da1cf1b76a9cfc48bb6aa2ce45372b9350d1eb73615476452b70 0014aaec 000000bc e1cf812d40da1cf1b76a9cfc48bb6aa2ce45372b9c43c0d7704b53 0014aba8 0000008c e1cf812d40da1cf1b76a9cfc48ad75a8d9542000ae56d7d76b5d4a6b7b2c6c684609f204c8ce 0014ac34 0000008c e1cf812d40da1cf1b76a9cfc48ad75a8d9542000ae56d7d76b5d4a6b7b3d67704609f204c8ce 0014acc0 000000c0 c1efa12d60fa3cf1974abcdc48a97fb2f05333008547caf1475749644b 0014ad80 000001b0 e1cf812d40da1cf1b76a9cfc48a275a1f0422b07ae41d0e9765942 0014af30 000000f4 c1efa12d60fa3cf1974abcdc48a67ba8cb5d372bb977ecd7715053 0014b024 000000c8 c1efa12d60fa3cf1974abcdc48a875b4cc540d3ca476 0014b0ec 0000045c e1cf812d40da1cf1b76a9cfc48a275a1f053201fae41d0e9765942 0014b548 00000090 e1cf812d40da1cf1b76a9cfc489d5e85f0453d2ba761ebd76c4c466c5733746f7015e8 0014b5d8 000001c0 e1cf812d40da1cf1b76a9cfc48bc6d99cd43392b9243d4e47a5f4469 0014b798 000001fc e1cf812d40da1cf1b76a9cfc48bc7fa7cb6e30069a7ddbe9745245634734 0014b994 00000090 e1cf812d40da1cf1b76a9cfc48985995f0453d2ba266fbd76c4c466c5733746f7015e8 0014ba24 000000a0 e1cf812d40da1cf1b76a9cfc48bc7fa7cb6e30069a7dd5ed7551557b 0014bac4 00000250 c1efa12d60fa3cf1974abcdc48a67ba8cb5d372b9350d1eb73614e6c50 0014bd14 0000011c c1efa12d60fa3cf1974abcdc48b968afdb540d16834bdbe34753426f4b2d6c 0014be30 000000f4 c1efa12d60fa3cf1974abcdc48bc7fa7cb6e30069841d3d7755b4a6d5626 0014bf24 00000434 c1efa12d60fa3cf1974abcdc48a774afdb 0014cc4c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014cc54 00000088 e1cf812d40da1cf1b76787ff48a76999df433707944ccc 0014ccdc 00000104 e1cf812d40da1cf1b76787ff48bb6aa2ce45372b934ed7ff7d4c7871503e617e 0014cde0 000000b4 e1cf812d40da1cf1b76787ff48ad75a8d9542000ae56d7d76b5d4a6b7b2c617a6d0ff5 0014ce94 0000007c c1efa12d60fa3cf19747a7df48a97fb2f0533e1b8647cad77150416d 0014cf10 00000300 e1cf812d40da1cf1b76787ff48a275a1f0523a159f45dd 0014d210 00000140 c1efa12d60fa3cf19747a7df48a67ba8cb5d372b934ed7ff7d4c786b4a2b 0014d350 00000208 c1efa12d60fa3cf19747a7df48a774afdb 0014d784 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014d78c 0000008c e1cf812d40da1cf1a16e85f848ad75a8d9542000ae56d7d76b5d4a6b7b2c617a6d1f 0014d818 0000008c c1efa12d60fa3cf1814ea5d848a97fb2f04537198147cae96c4b55677b367b7d76 0014d8a4 00000210 c1efa12d60fa3cf1814ea5d848a774afdb 0014dab4 00000188 e1cf812d40da1cf1a16e85f848a275a1f0523a159f45dd 0014dc3c 000000fc c1efa12d60fa3cf1814ea5d848a67ba8cb5d372b8547d5f87d4c4676512d70447014f2 0014df48 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014df50 0000008c e1cf812d40da1cf1a578b7eb78a06ca3dd450d009e7dcbeb75577871503e617e 0014dfdc 00000298 e1cf812d40da1cf1a578b7e478a945a5c7503c1394 0014e274 0000011c c1efa12d60fa3cf18558b7e076a07eaaca6e2203837dcbfd684e4b7b7b367b6f 0014e390 0000012c e1cf812d40da1cf1a578b7f872bc73a9cb58312b924addeb73 0014e4bc 00000050 c1efa12d60fa3cf18558b7ef72ba45b6d8430d078452c8e461614e6c4230 0014e50c 00000214 c1efa12d60fa3cf18558b7e179a76e 0014e8d8 00000024 d7f3a73172f137e29c45a3d7539f 0014e8fc 00000038 d7f3a73172f137ff804eb7cc46 0014e934 0000001c d7f3a73172f03cff804eb7cc46 0014e950 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0014e968 0000001c d7f3a73172f93be09e54acd9 0014e984 00000028 d7f3a73172f436ea8a58b9 0014e9ac 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0014e9d8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0014e9e0 0000000c f6d88b2d48cd11cba57f81e779 0014e9ec 00000068 d4e8b12d4bc713c3b05484ed799179a9cb54 0014ea54 000000b8 d4e8b12d5dd400ddb05484e770a77499df5020159c51 0014eb0c 00000008 d4e8b12d4ad006f1a66e86fb72916ab2dd 0014eb14 000000b4 d4e8b12d4ed110f1a36e9ae171b7 0014ebc8 00000154 d4e8b12d4ed41ecda06789fc729175a0c9423700 0014ed1c 00000100 d4e8b12d5ed006f1b6668cd774bc7fa2c645 0014ee1c 00000090 f4c8912d4ad406cb8a6884e764ab7e99cc503e189343dbe3 0014eeac 00000730 f4c8912d42c71bc98a6885ec 0014f5dc 00000288 d4e8b12d49da2dcdb86f 0014f864 000000d4 d4e8b12d4bda00cdb06fb7ed65bc75b4f0523a1f 0014f938 000000e4 d4e8b12d5ac71bdab0548ae973 0014fa1c 00000110 f4c8912d5dc71dcdb0789bd762a071a8c0463c2b9750d9e57d 0014fb2c 00000260 f4c8912d48d901f1a76e98e46e9179a9c2413e118547 0014fd8c 00000090 f4c8912d4fc001d78a7ab7e576a07ba1ca43 0014fe1c 00000158 f4c8912d59d101f1a77898d773af6ea7f0523d19814eddfc7d 0014ff74 00000050 f4c8912d49d406cf8a6887fd79ba45abc6423f158541d0d77b514a72483a617e 0014ffc4 00000158 f4c8912d5fc602f1b16a9ce948ad75abdf5d370094 0015011c 000001c4 f4c8912d5dc717de8a669fea749168a5d9 001502e0 00000390 d4e8b12d49da2dc3a2698bd765ad6c 00150670 000000f0 f4c8912d4ad006f1a56e86ec7ea07d 00150760 0000015c f4c8912d40c210cd8a6e90eb7f9174a9dc45330685 001508bc 00000298 f4c8912d5dc717de8a669fea749169a3c155 00150b54 00000114 f4c8912d40c210cd8a6e90eb7f9179a9c2413e118547 00150c68 00000078 d4e8b12d5fd01bdda67e8d 00150ce0 0000025c d4e8b12d4eda1fdeb96e9ced48ac78b4 00150f3c 0000025c d4e8b12d49da2dc3a2698bd764ab74a2 00151198 00000174 f4c8912d4bc717cb8a6d8dec48bc7fb5c04420179451 0015130c 00000420 f4c8912d4fc001d78a6389e673a27fb4 0015172c 00000020 f4c8912d43da06f1a76e89ec6e9172a7c1553e1183 0015174c 0000030c f4c8912d59d101f1b0738be048ad75abdf5d370094 00151a58 000009c0 f4c8912d59d101f1a66e86fb72917ea7db500d179e4fc8e47d4a42 00152418 00000488 f4c8912d59d101f1a67f89fc62bd45a5c05c22189456dd 001528a0 00000dbc f4c8912d59d101f1b16a9ce948ad75b3c1450d199851d5e96c5d4f5d4730786b751ff200 0015365c 000002f4 f4c8912d4edd17cdbe5481e67eba45b4ca45200dae41d7fd764a54 00153950 00000194 f4c8912d5dc71dcdb0789bd775af7e99da5f3307827ddeeb68 00153ae4 000003c4 f4c8912d5ad72ddcb06a8ce478a07d99cb5e3c11 00153ea8 000000e0 f4c8912d5ad72dd9a7629ced7ba174a1f0553d1a94 00153f88 00000150 f4c8912d5ad72ddcb06a8cd773a174a3 001540d8 0000011c f4c8912d49c71bd8b0549be771ba45a3dd433d06 001541f4 000006a0 f4c8912d5dc71dcdb0789bd765ab7bb5dc58351aae40d4e77b5554 00154894 00000534 f4c8912d49d406cf8a6e90eb7f9179a9c2413e118547 00154dc8 000011e4 f4c8912d5ed01cddb0548ce963af45a5c05c22189456dd 00155fac 00000254 f4c8912d5ec113daa078b7eb78a36aaaca4537 00156200 00000008 f4c8912d43c01ec28a6889e47bac7ba5c4 00156208 0000002c f4c8912d40d419cb8a6989ec48ac76a9cc5a212b9243d4e47a5f4469 00156234 00000130 d4e8b12d40d419cb8a6989ec48ac76a9cc5a21 00156fd0 0000000c d7f3a73172fc3ce78154acd9 00156fdc 00000024 d7f3a73172f137e29c45a3d7539f 00157000 00000038 d7f3a73172f137ff804eb7cc46 00157038 0000001c d7f3a73172f03cff804eb7cc46 00157054 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0015706c 00000028 d7f3a73172f436ea8a58b9 00157094 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0015709c 0000016c d4e8b12d49da2dc6ba678ce179a9 00157208 00000268 d4e8b12d4cd71ddca15480e77baa73a8c8 00157470 00000150 d4e8b12d4cd71ddca1548af167af69b5f0593d18954bd6ef 001575c0 000000d0 d4e8b12d5cc01bcba6688dd762a073b2f0433705 00157690 00000118 d4e8b12d44c601dbb05484f875 001577a8 00000160 d4e8b12d44c601dbb05484f875b6 00157908 0000021c f4c8912d5fd901f1b66a84e475af79ad 00157b24 00000024 f4c8912d59d001da8a7984fb 00157b48 00000238 d4e8b12d41dc1cc58a6e9afa78bc6999c2503b1a 00157d80 00000020 e6ce910672d902ccad 00157da0 00000170 d4e8b12d59c713de8a6f9ae161ab69 00157f10 00000110 d4e8b12d44c601dbb05484f872 00158020 0000011c d4e8b12d41da1dde8a7b89e1659168a9c84437 0015813c 000001e4 d4e8b12d49c71bd8b0548de674a275b5da43372b834ddffd7d 00158320 0000008c d4e8b12d5fda15dbb0549de660a774a2 001583ac 0000014c d4e8b12d5fd006dcac548ee97ea27fa2f0553702ae52d7fa6c4d 001584f8 0000001c f4c8912d5fd41bc28a7b87fa63 00158514 00000104 f4c8912d4bdc1ec28a6e81f827f9 00158618 00000310 f4c8912d5fd002c1a77fb7e47ea07199dc4533008451 00158928 000006b8 f4c8912d5fd001cba1548ee675917fb4dd5e202b924dcde66c4d 00158fe0 00000118 f4c8912d5fd001cba1549cfa76a069b6c043262b9450cae76a61446d51316168 001590f8 0000023c f4c8912d41d016f1a16285ed65 00159334 00000078 f4c8912d4b8d2dd9ba799ce048bc7fb6c043261d9f45 001593ac 00000110 f4c8912d48d807f1a56484e448ba73abca43 001594bc 00000180 f4c8912d4fc001d78a7e86ff7ea07e 0015963c 0000016c f4c8912d59d411c68a798dfb62a37f 001597a8 000000d8 f4c8912d4cd71ddca1548efa72ab60a3 00159880 0000007c d4e8b12d4cd71ddca15485ff75ad45b4cc47 001598fc 0000000c f4c8912d44db1bda8a798dfc65b7 00159908 00000160 f4c8912d40c01edabc549cfa76a069b6c043262b9450cad77b564c 00159a68 0000090c f4c8912d5ed01cca8a6a8be4 0015a374 00000168 f4c8912d4cd61ef1b66a84e475af79ad 0015a4dc 000000b0 f4c8912d41da15f1b3649aeb729176afdf6e3702944ccc 0015a58c 00000944 f4c8912d49d004c7b66eb7f878bc6e99c9503b18 0015aed0 000004a4 f4c8912d4bda00cdb05484e167 0015b374 000004c4 f4c8912d59c713c0a67b87fa63917eb4c647372b9450cae76a 0015b838 00000790 f4c8912d41dc1cc58a789ce963ab45b2c65c3706 0015bfc8 00000094 d4e8b12d4bda00cdb05484e167917baad8502b07 0015c05c 0000036c d4e8b12d41da1dde8a789fe163ad7299dd54221b8356 0015c3c8 00000178 f4c8912d5ed601c78a6781e67c9176b5db6e3605 0015c540 000000c0 f4c8912d5ed001da8a6286fe76a273a2ce4537 0015c600 0000041c f4c8912d41d11cf1b6678de979bb6a 0015ca1c 00000278 f4c8912d41dc1cc58a6f87ff79 0015cc94 000000bc f4c8912d44c710f1bc659ee97ba77ea7db54 0015cd50 000008ec f4c8912d41da15c18a6889e47bac7ba5c4 0015d63c 000000c8 f4c8912d4ad006f1b36e8cd7739173a2 0015d704 00000694 f4c8912d48dc029eec548dfe72a06e 0015dd98 00000118 d4e8b12d59c713de8a6d8dec 0015deb0 000009c8 d4e8b12d41da15c18a6884ed76a06fb6 0015e878 0000009c f4c8912d4ad006f1b36e8cd771a078 0015e914 000000b4 f4c8912d4ad006f1b36e8cd767ad78 0015e9c8 00000054 f4c8912d4ad006f1a5649afc48af76b6ce6e341a93 0015ea1c 00000090 f4c8912d4ad006f1b3658ad767a173a2 0015eaac 00000068 f4c8912d4ad006f1a16f9bec48aa6fa4 0015eb14 000000b4 f4c8912d41da15f1b0738be048ba73abca5e2700 0015ebc8 00002184 f4c8912d5dda00da8a7f81e572bc 00160d4c 0000002c f4c8912d41dc02f1b46784 00160d78 0000002c f4c8912d41c517f1b46784 00160da4 0000004c f4c8912d43c01ec28a7987fd63a774a3 00160df0 000001a4 d4e8b12d48db13ccb96eb7ec67 00160f94 0000091c f4c8912d41dc1cc58a6d89e17b 001618b0 0000008c f4c8912d5dd003f1b96db7e473a045a5c75a 0016193c 00000238 f4c8912d41da1dde8a789fe163ad7299cc5939 00161b74 000008e0 f4c8912d41dc1cc58a798dfc65b7 00162454 00000474 f4c8912d48cd11c68a798dfc65b7 001628c8 00000d88 f4c8912d48c700f1b0738be048bc7fb2dd48 00163650 00001068 f4c8912d5dda00da8a6e9eed79ba 001646b8 00000318 f4c8912d5dc71dcdb0789bd775af7e99ce5d2215 001649d0 0000017c f4c8912d4fc001d78a7f81e572bc 00164b4c 00000284 f4c8912d48c700f1a76e8b 00164dd0 00000040 f4c8912d5ed013dcb663b7e478a16a99c25022 00164e10 00000194 d4e8b12d5edd1dd98a6887e671a77d99c15425 00164fa4 00000414 f4c8912d5dc71bc0a1548eed739173a8c95e 001653b8 000001d8 e2d98b1c59ea1ec7bb60b7ed65bc75b4dc 00165590 00000064 f4c8912d5dc71bc0a15498e765ba45b2ca4926 001655f4 0000009c f4c8912d5dc71bc0a15484e778be45b5db502611 00165690 00000524 f4c8912d40d41bc08a6781e67c917fb4dd5e2007 00165bb4 00000024 f4c8912d41dc1cc58a6e9afa78bc69 00165bd8 00000024 f4c8912d49d01edab45484e179a569 00165bfc 00000108 f4c8912d5cd1 00165d04 0000046c d4e8b12d5edd1dd98a6887e671a77d 00166170 00000088 f4c8912d5ed61fc78a6781e67c917fb4dd5e2007 001661f8 00000164 d4e8b12d4ed917cfa75484e179a569 0016635c 00000120 f4c8912d49c42dcdbd60 0016647c 00000034 f4c8912d44c117c38a6f99d774a671 001664b0 00000320 d4e8b12d4cd61ef1b17981fe72bf 001667d0 000000e4 d4e8b12d5dc71bc0a1548ee675917ea7db50 001668b4 0000040c f4c8912d5edd1dd98a668eeb48bd6ea7db54 00166cc0 00000f7c f4c8912d5edd1dd98a6287d772bc68a9dd6e311b844cccfb475d497148 00167c3c 000001f0 d4e8b12d5edd1dd98a6287d772bc68a9dd6e311b844cccfb 00167e2c 0000012c f4c8912d42c317dca27981fc729173a9f0533307947ddbe76d505371 00167f58 00000028 f4c8912d4cdb13c2ac718dd772be78a5f04226158551 00167f80 00000310 d4e8b12d40d41bc0a15481e661a171a3f057331d9d7dc8e76a4a 00168290 00000258 d4e8b12d40d41bc0a15481e661a171a3f0453d13964eddd7745f546756 001684e8 00000020 d4e8b12d4edd17cdbe5484e778be45b4ca523d029450d1ed6b615476452b70 00168508 00000034 d4e8b12d4ad006fda2629ceb7f9a63b6ca 0016ac18 0000000c d7f3a73172fc3ce78154acd9 0016ac24 00000010 d7f3a73172fc3ce78154bbd9 0016ac34 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0016ac3c 000003bc f4c8912d44db1bda8a6689f848bd6eb4da522607 0016aff8 000000e0 d4e8b12d49d61ef1a16285ed48ad72a3cc5a 0016b0d8 00000014 d4e8b12d44db1bda8a6d8dec 0016b0ec 00000240 d4e8b12d44db1bda8a6c89fc729179a9da5f26 0016b32c 00000068 d4e8b12d41d401cba75487ee71 0016b394 0000016c d4e8b12d41d401cba75487e6 0016b500 0000011c d4e8b12d4bda00cdb05484e179a545afc15826 0016b61c 00000084 d4e8b12d41dc1cc58a798dfb72ba 0016b6a0 00000268 d4e8b12d58c516cfa16eb7ed65bc45a5c0443c009450cb 0016b908 0000017c f4c8912d43c51ddca15481e67eba 0016ba84 00000080 d4e8b12d41dc1cc58a6286e163 0016bb04 000001a4 f4c8912d41c51ddca15481e67eba 0016bca8 00000008 f4c8912d43c51ddca1548ce164af78aaca6e300d8143cbfb 0016bcb0 000001c8 f4c8912d43c51ddca15484e179a545afc15826 0016be78 0000006c f4c8912d44db1bda8a659dea 0016bee4 000000d0 f4c8912d44db1bda8a6f9dea 0016bfb4 0000005c f4c8912d44db1bda8a6d86ea 0016c010 00000068 f4c8912d44db1bda8a6d98ea 0016c078 00000204 f4c8912d44db1bda8a7b8bea 0016c27c 00000050 f4c8912d44db1bda8a6e84fb48a168afc86e3a1083 0016c2cc 00000050 f4c8912d44db1bda8a6e84fb48bc7fb5df6e3a1083 0016c31c 00000058 f4c8912d44db1bda8a6885e6739172a2dd 0016c374 00000054 f4c8912d44db1bda8a6f89fc769172a2dd 0016c3c8 00000048 f4c8912d44db1bda8a799bf848a67eb4 0016c410 0000003c f4c8912d44db1bda8a6d8be064fd 0016c44c 0000036c f4c8912d44db1bda8a7b87fa639179aec641 0016c7b8 00000030 d4e8b12d5dda05cba754da 0016c7e8 000002a8 f4c8912d44db1bda8a668eeb48be75b4db 0016ca90 00000500 f4c8912d40d311dd8a6286e163 0016cf90 00000518 f4c8912d49d311dd8a6286e163 0016d4a8 00000a5c d4e8b12d44db1bda 0016df04 00000284 d4e8b12d5edd1dd98a659ed77aab77 0016e188 0000003c d4e8b12d44db04cfb9628ce963ab45a5c343 0016e1c4 00000048 d4e8b12d44db04cfb9628ce963ab45a2dc5d 0016e20c 00000014 d4e8b12d4ad006f1a5649afc48ab7f99cc430d0eae56d5fa474a4f70 0016e220 00000014 d4e8b12d4ad006f1a5649afc48ab68b7f053330794 0016e234 00000014 d4e8b12d4ad006f1a5649afc48ab68b7f0523d1a827dd9ec6a 0016e248 00000014 d4e8b12d4ad006f1a5649afc48ab68b7f05d371a 0016e25c 00000014 d4e8b12d4ad006f1a5649afc48a67399df433b2b8247d6ec29 0016e270 00000014 d4e8b12d4ad006f1a5649afc48a67399df433b2b8247d6ec2a 0016e284 00000014 d4e8b12d4ad006f1a5649afc48a777b7f053330794 0016e298 00000014 d4e8b12d4ad006f1a5649afc48a777b7f05d371a 0016e2ac 00000014 d4e8b12d4ad006f1a5649afc48a777b7f041201b957dd9ec6a 0016e2c0 00000014 d4e8b12d4ad006f1a5649afc48a774b2f0553718905be7fc71534270 0016e2d4 00000014 d4e8b12d4ad006f1a5649afc48a774b2f05c3707827dd9ec6a 0016e2e8 00000014 d4e8b12d4ad006f1a5649afc48a774b2f05c3707827dcee9744b42 0016e2fc 00000014 d4e8b12d4ad006f1a5649afc48bd7fb5db6e30158247 0016e310 00000014 d4e8b12d4ad006f1a5649afc48bd7fb5db6e3e119f 0016e324 00000014 d4e8b12d4ad006f1a5649afc48bd7cb7f053330794 0016e338 00000014 d4e8b12d4ad006f1a5649afc48bd7cb7f05d371a 0016e34c 00000014 d4e8b12d4ad006f1a5649afc48bd7daaf0413313947dd4ed76 0016e360 00000014 d4e8b12d4ad006f1a5649afc48bb6a99cc452018ae43dcec6a 0016e374 00000014 d4e8b12d4ad006f1a5649afc48bb6a99cb502615ae43dcec6a 0016e864 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0016e86c 000000c0 d4e8b12d44c600 0016e92c 00000974 f4c8912d42c006ccba7e86ec48ad77 0016f2a0 00000188 f4c8912d48c700c1a75481ec7bab45a5c2 0016f428 00000240 f4c8912d41c002f1a36e9ae171b7 0016f668 000018dc f4c8912d4bc713c3b05485e979af7da3dd6e3119 00170f44 0000005c f4c8912d4ad006f1b07999d77ea07ea3d7 00170fa0 000000b0 f4c8912d4eda02d78a788ef948ab74b2dd48 00171050 00001280 f4c8912d44db10c1a0658cd774a3 001722d0 00000144 f4c8912d4edd17cdbe548ce963af45b3c15537068357d6 00172414 00000bf0 f4c8912d5dc71dcdb0789bd774a3 00173004 000000f0 f4c8912d5ed006dba5548cfa7eb87f99cb54330099 00173588 00000024 d7f3a73172f137e29c45a3d7539f 001735ac 0000001c d7f3a73172f03cff804eb7cc46 001735c8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001735d0 000000ac f4c8912d5dc71dcdb0789bd778bb6ea4c0443c10ae44dbbc47524e6c4f00717a6d1b 0017367c 00000068 f4c8912d43da06c7b372b7fa67 001736e4 00000058 f4c8912d5fc52ddeba799cd763a145b4da5f361b864ce7fb6c5f5367 0017373c 00000280 f4c8912d5dc71dcdb0789bd778bb6ea4c0443c10ae44dbbc475a42744d3c70447d1bf204 001739bc 000000b8 f4c8912d5dc71dcdb0789bd778bb6ea4c0443c10ae40d4fb 00173a74 00000038 f4c8912d5fd011cbbc7d8dec48ac76b5 00173aac 000000e0 f4c8912d59d101f1bc65b7e179a76e 00173b8c 0000011c f4c8912d59d101f1ba7e9cd77ea073b2 00173ca8 000015b8 f4c8912d42c71bc98a7f8cfb 00175260 0000015c d4e8b12d49da2ddab178 001753bc 00000130 d4e8b12d49c71bd8b05481e67eba 001754ec 0000010c d4e8b12d5ac71bdab0548be974a67f99cb433b0294 001755f8 000000e4 d4e8b12d59d001da8a7e86e1639168a3ce552b 001756dc 0000023c f4c8912d59d001da8a7e86e1639168a2d66e31159d4edae97b55 00175918 00000080 f4c8912d5dda00da8a648eee7ba774a3 00175998 00000030 d4e8b12d49dc01cfb7678dd767a168b2 001759c8 00000254 f4c8912d5fd006dcac549cec64 00175c1c 00001f80 d4e8b12d49c71bd8b05481e67eba45a5ce5d3e169041d3 00177b9c 00000300 f4c8912d4cd706dd 00177e9c 00000064 f4c8912d4cd706dd8a6887e567a27fb2ca 00177f00 00000cdc f4c8912d5fd011cbbc7d8dec48ab76b5 00178bdc 00000120 f4c8912d4cd706dd8a6a8beb48ad75abdf5d370094 00178cfc 00000240 f4c8912d4fd901f1a76e8bed7eb87fa2 00178f3c 00000058 f4c8912d4edd13dc8a7f87d77fab62 00178f94 00000104 f4c8912d48d901f1a76e8bed7eb87fa2 00179098 000006c0 f4c8912d5dc71dcdb0789bd778bb6ea4c0443c10ae47d4fb 00179758 000002cc f4c8912d42c71bc98a6e84fb 00179a24 00000138 d4e8b12d5fdf06f1b0679b 00179b5c 00000128 d4e8b12d4cd611f1b0679b 00179c84 00000124 d4e8b12d49da2dcbb978 0017a838 00000024 d7f3a73172f137e29c45a3d7539f 0017a85c 00000038 d7f3a73172f137ff804eb7cc46 0017a894 0000001c d7f3a73172f03cff804eb7cc46 0017a8b0 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0017a8c8 00000010 d7f3a73172fc3ce78154bbd9 0017a8d8 00000028 d7f3a73172f436ea8a58b9 0017a900 0000002c d7f3a73172f436ea8a58b9d75f8b5b82 0017a92c 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0017a958 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0017a960 00000124 f4c8912d41d401da8a6c89fb67916aa9dd450d018247d9ea745b 0017aa84 000000bc d4e8b12d5ed006dba55485ee74917ea7db50 0017ab40 00000024 d4e8b12d5dc71dcdb0789bd765ab77a9db540d189051ccd77f5f5472 0017ab64 00000090 f4c8912d5dc71dcdb0789bd765ab77a9db540d189051ccd77f5f5472 0017abf4 00000054 f4c8912d5dc71dcdb0789bd77baf69b2f056330781 0017ac48 00000068 f4c8912d40d311f1bc6581fc48be68aac6 0017acb0 00000090 f4c8912d44db1bda8a6286d763bb74a8ca5d 0017ad40 000001a4 f4c8912d49da2ddebc64b7fc62a074a3c3 0017aee4 00000100 d4e8b12d5dda00da8a6081e47b9175b2c75420 0017afe4 000000d4 d4e8b12d46dc1ec28a649ce072bc 0017b0b8 00000138 d4e8b12d49da2dc3b368b7f87ea1 0017b1f0 0000002c f4c8912d40d311f1ba7e9cd774a177b6c3542611 0017b21c 00000060 f4c8912d4bdc1cca8a668eeb48ad75b6d6 0017b27c 0000026c f4c8912d40d311f1a56e86ec7ea07d99cc5d37159f57c8 0017b4e8 000002b8 f4c8912d40d311f1a57987eb72bd6999ce5239 0017b7a0 0000037c d4e8b12d4fdc1cca8a668eeb48be75b4db 0017bb1c 00000094 f4c8912d40d311f1b77e81e4739179a9df48 0017bbb0 0000051c f4c8912d40d311f1b9648fe748ad76a3ce5f2704 0017c0cc 00000090 f4c8912d40c210cd8a798bfe48ab68b4c043 0017c15c 00000154 f4c8912d49da2ddaa06586ed7b 0017c2b0 00000124 f4c8912d40d311f1b46883d763a777a3c04426 0017c3d4 000000a4 f4c8912d42c71bc98a668eeb48af79ad 0017c478 00000234 f4c8912d42c71bc98a668eeb 0017c6ac 00000144 d4e8b12d49da2dc3b368 0017c7f0 00000158 d4e8b12d49da2dc3b368b7ea6ebe7bb5dc 0017c948 000000e8 f4c8912d40d311f1b46883d77ea045a5c05c22189456dd 0017ca30 00000054 f4c8912d40d311f1b46883d778bb6e99cc5e3f049d47cced 0017ca84 000000c4 d4e8b12d49da2dc3b368b7fb74bd45a4d641330782 0017cb48 000002c4 f4c8912d40d311f1bc65b7eb78a36aaaca4537 0017d084 00000024 d7f3a73172f137e29c45a3d7539f 0017d0a8 0000001c d7f3a73172f03cff804eb7cc46 0017d0c4 00000028 d7f3a73172e233e78154bcc15a8b5e 0017d0ec 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0017d0f4 0000011c d4e8b12d5fd003dbb0789cd77ea145a2ce45332b8347defa7d4d4f 0017d210 00000190 d4e8b12d5ed006f1bc64b7e962ba7599cd4822158251 0017d3a0 00000138 d4e8b12d5ed006f1bc64b7e962ba7599cd4822158251e7e97452 0017d4d8 00000080 d4e8b12d4bdc1cca8a7b80f164a779a7c36e341a93 0017d558 000002c0 d4e8b12d4edd13c0b26eb7e472aa 0017d818 00000074 d4e8b12d5edd07dab1649fe648bd72a3c3473707 0017d88c 000000e0 d4e8b12d48d807f1b96298 0017d96c 00000190 d4e8b12d49c71bd8b05484e774af6ea3 0017dafc 00000080 f4c8912d48d807f1b96487e362be45b5c35e262b8256d9fc 0017db7c 00000208 d4e8b12d49c71bd8b0548ee962a26e 0017dd84 00000084 d4e8b12d4ed917cfa7549be072a27c99c3543607 0017de08 00000214 d4e8b12d49c71bd8b0548af167af69b5 0017e01c 0000013c d4e8b12d5edd17c2b3549be478ba45a4d641330782 0017e158 00000288 d4e8b12d49c61ef1b86d8b 0017e3e0 00000510 d4e8b12d5cc017dbb0548cfb7b917eb4c64737 0017e8f0 00000290 d4e8b12d49c71bd8b0548cfb7b 0017eb80 0000014c d4e8b12d48d807f1b16a9ce948bd6ea7db4421 0017eccc 00000034 d4e8b12d4ad006f1a6638de4719179a9da5f26 0017ed00 00000034 d4e8b12d4ad006f1b26e86ed65af6eafc05f 0017ed34 00000154 d4e8b12d5edd17c2b35484e774af6ea3 0017ee88 00000150 d4e8b12d5edd17c2b35489fd73a778aaca 0017efd8 0000000c d4e8b12d48d807f1a56484e448ad75a8dc45331a85 0017efe4 0000015c d4e8b12d4ad006f1b0669dd767af7da3 0017f140 000002fc f4c8912d40dc00dcba79b7e576be45a5c754311fae50ddfe7d4c54677b2c7d7e751c 0017f43c 00000064 f4c8912d40dc00dcba79b7e576be45abc9520d17904ed4ea795d4c 0017f4a0 00000098 f4c8912d40dc00dcba79b7e576be45a4da583e10ae50d7fd6c574967 0017f538 00000084 f4c8912d40dc00dcba79b7e576be45b5c7543e12ae46d9fc79 0017f5bc 0000007c d4e8b12d49da2dcbb87eb7ec739169b2ce43261195 0017f638 00000bdc f4c8912d5ec51dc88a6a86e97bb760a3 00180214 00000740 f4c8912d5ec51dc88a6880ed74a5 00180954 00000430 d4e8b12d49da2dcbb87eb7ec73 00180d84 000000ec d4e8b12d49da2dcbb87e 00180e70 00000028 d4e8b12d48d807f1a5649afc48bb69a7cd5d37 00180e98 000002d0 f4c8912d4ad006f1b66486fc65a176aaca430d189e41d9fc715149 00181168 0000004c f4c8912d41d016f1b66a84e475af79ad 001811b4 00000c3c d4e8b12d5fd002c1a77fb7fd79af6ab6dd5e2411957ddee16a535063563a 00181df0 00000424 f4c8912d4bdc1ec28a7884e7639173a8c95e 00182214 00000128 f4c8912d40dc00dcba79b7e576be45a7dc423b139f7dcbe07d52516757 0018233c 000000a4 f4c8912d40dc00dcba79b7e576be45b4ca52371d8747e7fb705b4b64 001823e0 000000a0 f4c8912d5ec51dc88a798df872af6e 00182480 0000020c f4c8912d48d807f1a66a9eed48aa7bb2ce 0018268c 0000012c f4c8912d48d807f1b6678de965917ea7db50 001827b8 0000009c f4c8912d4bdc1cca8a658df0639171a8c0463c2b904ec8e9 00182854 0000009c f4c8912d4bdc1cca8a7b9aed619171a8c0463c2b904ec8e9 001828f0 00000188 f4c8912d4bdc1cca8a6e86ec48bd72a3c357 00182a78 00000180 f4c8912d4bdc1cca8a789ce965ba45b5c7543e12 00182bf8 000004ec f4c8912d4bdc1cca8a7e86e379a16da8f0423a119d44 001830e4 00000250 f4c8912d48d807f1b86a9ae348a373b5dc583c13 00183334 000002fc f4c8912d4cd71ddca1548de5629169a3de 00183630 0000020c f4c8912d48d807f1b26e9cd779ab6d99c6530d009051d3 0018383c 000000b8 f4c8912d48d807f1b26e9cd779ab6d99c0530d009051d3 001838f4 000000e0 f4c8912d48d807f1b6678de979bb6a99db50211f 001839d4 00000b08 f4c8912d48d807f1b8629bfb7ea07d99c154252b9943caec6f5f5567 001844dc 000001e0 f4c8912d48d807f1bd6ab7fa72bd7fb2 001846bc 000002c4 f4c8912d48d807f1b36286e164a645a9cd6e26158249 00184980 00000068 f4c8912d48d807f1b66a84e475af79ad 001849e8 0000071c f4c8912d48d807f1b6638deb7c9172a7 00185104 00000300 f4c8912d48d807f1bb6e9fd778ac45b2ce4239 00185404 00000034 e2c495175fd11dd9bb549be072a26ca3dc6e31159d4edae97b55 00185438 000001c8 d4e8b12d5ecc01dab066b7fb7fbb6ea2c0463c 00185600 00000144 d4e8b12d48d807f1b16e84e96e 00185744 0000043c f4c8912d48d807f1b76e9bfc48a874a4 00185b80 0000031c f4c8912d48d807f1b76e9bfc48a37bb6f0573c16 00185e9c 0000038c f4c8912d5dc717deb4798dd77aaf6a 00186228 00000768 f4c8912d48d807f1b6638deb7c917ca7da5d26 00186990 00000020 f4c8912d4ed917cfa7548de567ba6399dc5d3d00827dd7ee4752426657 001869b0 00000634 f4c8912d48d807f1a66e99d773a174a3 00186fe4 0000042c f4c8912d48d807f1b26e9cd772b87fa8db6e311b9547 00187410 00000044 f4c8912d5ed004cba7629cf148ba7599ca5f31189e51cdfa7d615476452b 00187454 00000dc8 f4c8912d48d807f1a76e98e765ba45a3d9543c00 0018821c 00001480 f4c8912d5ec100c7bb6cb7e179 0018969c 00000c68 f4c8912d5ed001f1a56a8fed 0018a304 0000003c f4c8912d48d807f1b26e86ed65af6ea3f05c3304 0018a340 000000ec f4c8912d48d807f1a07b8ce963ab45abce41 0018a42c 00000148 f4c8912d48d807f1bd6a9aec48af7ea2dd542107 0018a574 000000ec f4c8912d48d807f1a76e9cfa7eab6ca3f0583d2b9450cae76a61446d51316168 0018a660 00000170 f4c8912d48d807f1b66389e670ab45aaca5521 0018a7d0 0000015c f4c8912d48d807f1b66389e670ab45afc06e3301854de7ea614e467157 0018a92c 000001d8 f4c8912d48d807f1b17981fe729179a9c145201b9d 0018ab04 000000a4 f4c8912d48d807f1a6639dfc73a16da8 0018aba8 000000ec f4c8912d48d807f1b26e9cd776a27bb4c242 0018ac94 00000008 f4c8912d48d807f1b16e8ee962a26e99cd4822158251 0018ac9c 00000600 f4c8912d48d807f1b6648ced7ba17ba2f0543f01 0018b29c 00000178 f4c8912d48d807f1b77981ec70ab45b6ce5637 0018b414 000000e8 f4c8912d48d807f1b66981eb48ac63b6ce4221 0018b4fc 00000054 f4c8912d48d807f1b46987fa639168a9c84437 0018b550 00000074 f4c8912d48d807f1a7648ffd72916aa9dd450d069441d7fe7d4c5e 0018b5c4 00000098 d4e8b12d58db10d7a56a9bfb48a275a9df 0018b65c 00000038 d4e8b12d58db10d7a56a9bfb48a275a9df00 0018b694 00000038 d4e8b12d58db10d7a56a9bfb48a275a9df03 0018b6cc 00000008 d4e8b12d58db10d7a56a9bfb48a275a9df000d179e4cdee16a53 0018b6d4 00000008 d4e8b12d58db10d7a56a9bfb48a275a9df030d179e4cdee16a53 0018b6dc 0000049c f4c8912d48d807f1a0658af167af69b5f0423a119d54ddfb 0018bb78 000003c4 f4c8912d4ad006f1ba69b7fb7fab76b0ca42 0018bf3c 00000150 f4c8912d48d807f1ba7d8dfa65a77ea3 0018c08c 00000050 f4c8912d48d807f1bb6481fb729168a3cc5e2411835b 0018c0dc 000005a0 f4c8912d5edd1dd98a6e85fd 0018c67c 0000019c f4c8912d4ad01ccba76a9ced48a275a9df6e3f15817dddfe7d5053 0018c818 0000027c f4c8912d48d807f1b77298e964bd45a2dd58241182 0018ca94 0000024c d4e8b12d40d41bc0a15481e661a171a3f0532b049051cbd77c4c4e74412c 0018cce0 000000b8 d4e8b12d40d41bc0a15481e661a171a3f0543c15934eddd7745148727b2d7078760ce317c5 0018cd98 000000a4 f4c8912d48d807f1b46f8cd773a769b4da41261b837dcce7475a546e 0018ce3c 0000007c d4e8b12d4ed917cfa7548cfb7b 0018ceb8 000000a8 f4c8912d40d41cf1a0658af167af69b5f05d3d1b81 0018cf60 00000028 d4e8b12d58db10d7a56a9bfb48a37ba8f05d3d1b8110 0018cf88 00000028 d4e8b12d58db10d7a56a9bfb48a37ba8f05d3d1b8113 0018cfb0 0000009c d4e8b12d58db10d7a56a9bfb48af76aaf05d3d1b8151 0018d04c 000000b8 d4e8b12d48db13ccb96eb7ec64a2 0018d104 0000005c f4c8912d4ad01ccba76a9ced48ab77b3f0523d10944ed7e97c4d78614b3265777c0ee33ad9dd0d2aec 0018d160 0000156c f4c8912d48d807f1bb6e9fd77eac45b2ce4239 0018e6cc 000009d4 f4c8912d48d807f1b36286e164a645afcd6e26158249 0018f0a0 00000358 f4c8912d48d807f1a47e8dfd72aa45b1c04339 0018f3f8 00000214 f4c8912d49da2dcbb87eb7ff78bc71 0018f60c 000002b0 d4e8b12d48d807f1b86a81e6 0018f8bc 00000100 f4c8912d48d807f1b6638deb7c9179a9cb543e1b9046e7eb7753576e412b70 0018f9bc 00000034 f4c8912d40dc00dcba79b7eb78aa7faac050362b8347cbf1765d787241317172771d 0018f9f0 00000050 f4c8912d40dc00dcba79b7eb78aa7faac050362b8347cbf1765d78614b3265777c0ee3 0018fa40 00000028 f4c8912d40dc00dcba79b7eb78aa7faac050362b8347cbf1765d787241317172771dd907c9c20420 0018fa68 00000028 f4c8912d40dc00dcba79b7eb78aa7faac050362b8347cbf1765d78614b3265777c0ee33adede0128fc 0018fa90 00000030 f4c8912d40dc00dcba79b7eb78aa7faac050362b8347cbf1765d7861453379797819ed 00191c68 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00191c70 00000038 d4e8b12d40d41bc0a15485e773ab 00191ca8 00000098 f4c8912d40d41bc0a15485ee749169a3c155 00191d40 000000f0 f4c8912d40d41bc0a1548de663bc63 00191e30 000004f4 f4c8912d40d41bc0a1548de663bc6399dd5423 00192324 00000318 f4c8912d40d41bc0a1548df07eba 0019263c 000008c8 f4c8912d40d41bc0a15485ee749168a5d9 00192f04 00000254 f4c8912d40d41bc0a1548df07eba45b4ca40 00193158 0000019c d4e8b12d4cd71ddca15485e97ea06e99c25e3611 001932f4 00000040 f4c8912d40d41bc0a15485ee749178b3c65d36 00193334 000000bc f4c8912d40d41bc0a15485ee74917ba5c46e3116 001933f0 00000060 f4c8912d40d41bc0a1549aed669179a4 00193450 0000008c f4c8912d40d41bc0a1548de663bc6399dd54232b9743d1e4475d45 001934dc 00000244 f4c8912d40d41bc0a15498fa78ad7fb5dc6e3119 00193720 00000164 f4c8912d40d41bc0a15484e179a545b5db502611ae56d1e57d4c 00193884 0000016c f4c8912d40d41bc0a1548be072ad7199c3583c1fae51cce96c5b 001939f0 00000170 f4c8912d5fda15dbb0549bfc76ba7f99dd5423 00193b60 00000060 f4c8912d5fda15dbb0549bfc76ba7f99dd54232b9240 00193f20 0000001c d7f3a73172f03cff804eb7cc46 00193f3c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00193f44 000000bc f4c8912d41dc16f1a76e8be761ab68bff0583c1d85 00194000 0000031c f4c8912d4edd17cdbe5484e1739168a3cc5e2411835be7e67d5b436740 0019431c 000000ac f4c8912d41dc16f1a76e8be761ab68bff0573b1a9851d0 001943c8 00000010 f4c8912d41dc16f1a07b8ce963ab45b5db5422 001943d8 0000239c f4c8912d48d807f1b9628cd765ab79a9d954200d 00196f60 0000001c d7f3a73172f03cff804eb7cc46 00196f7c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00196f84 000000bc f4c8912d49d116f1a76e8be761ab68bff0583c1d85 00197040 00000180 f4c8912d49d116f1bc6581fc7eaf6ea3f05537029841ddd77c5754614b29706960 001971c0 00000080 f4c8912d49d116f1a76e8be761ab68bff0573b1a9851d0 00197240 000002b4 f4c8912d4edd17cdbe548cec739168a3cc5e2411835be7e67d5b436740 001974f4 00000010 f4c8912d49d116f1a07b8ce963ab45b5db5422 00197504 00002598 f4c8912d48d807f1b16f8cd765ab79a9d954200d 0019a2ac 0000001c d7f3a73172f03cff804eb7cc46 0019a2c8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0019a2d0 00000090 f4c8912d49d016f1a07b8ce963ab45b5db5422 0019a360 000010cc f4c8912d48d807f1a7648ffd72917fa8cc5d3d078450ddd76a5b446d523a6762 0019b894 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0019b89c 00000060 fcdd8f1740d602d7 0019b8fc 00000048 fcdd8f1740c617da 0019b944 00000008 f5ce963b63e331ef 0019b94c 00000008 d1eaa13a68ea15cba145bedb7eb47f 0019b954 0000009c d4e6bd1a5eea10dbbc678cd763af79aed65e3c2b814dcafc7b515570 0019b9f0 00000b6c d4e6bd1e42d416f1b97f8dd770a26fa3f043371382 0019c55c 00000074 f4c6bd114fdc11f1a16a84e348a17ca0 0019c5d0 00000064 f4c6bd1644c602c2b472b7ef7bbb7f99db482211ae50ddfe 0019c634 00000008 f4c6bd1644c602c2b472b7e078bd6e99df5e2000ae4ed9fb7d4c7871503e617e 0019c63c 00000104 f4c6bd1444cd2dcdb46880ed48a37fabc0432b2b9c43c8 0019c740 00000008 f4c6bd1548c12ddeba6781eb6e9177a3c25e200dae46d1e57561546b5e3a 0019c748 00000008 f4c6bd1548c12ddea568b7fb67bc45a2ce5320 0019c750 00000008 f4c6bd1548c12ddea568b7fb67bc45a2ce43 0019c758 00000008 f4c6bd1548c12ddea568b7fb67bc45a2dc582106 0019c760 00000004 f4c6bd1a42c606f1a5649afc48a27bb5ca43212b9e44de 0019c764 0000000c f4c6bd1a5eea13cda47e81fa729168a3db433b118743d4d76a5b546d512d767e 0019c770 00000030 f4c6bd1a5eea13c2b9648be963ab45a5cb5931 0019c7a0 00000004 f4c6bd1a5eea13dda67e85ed48ad72a3cc5a 0019c7a4 0000002c f4c6bd1a5eea11cd8a7b9ae179ba7c 0019c7d0 0000010c f4c6bd1a5eea11c6b06883d77bba7f99ca5531 0019c8dc 0000002c f4c6bd1a5eea11c6b06883d77bba7f99c15e262b9d4ddfef7d5a 0019c908 000020b8 f4c6bd1a5eea11c6b06883d764ba68b3cc450d1b9744cbed6c4d 0019e9c0 00000064 f4c6bd1a5eea11c6b06883d763af69b5da5c37 0019ea24 00000050 f4c6bd1a5eea11c2b06a9ad77bba7f99c15e262b9d4ddfef7d5a 0019ea74 00000044 f4c6bd1a5eea11c1bb7887e4729179aaca503c0181 0019eab8 00000084 f4c6bd1a5eea11c1bb7d8dfa639176b2ca 0019eb3c 0000007c f4c6bd1a5eea11dcb47880d773bb77b6f0563700ae56c8 0019ebb8 00002be8 d4e6bd1a5eea10dbbc678cd776aa7eb4ca42212b9c43c8 001a17a0 00000230 f4c6bd1a5eea11dcb47880d773bb77b6f05d3d15957dc8f87b4c 001a19d0 00000028 f4c6bd1a5eea11dcb47880d773bb77b6f041201181 001a19f8 00000628 f4c6bd1a5eea16cbb6648ced48aa62f4df6e3f17817ddbe96d4d42 001a2020 000003c4 f4c6bd1a5eea16cbb6648ced48bd6ab4c645372b8141d1f0475344727b3c746e6a1f 001a23e4 00003004 f4c6bd1648d61dcab05485e974a673a8ca6e311c9441d3 001a53e8 00000034 f4c6bd1a5eea14c7bb629be048ad7bb4cb6e3001834c 001a541c 0000002c f4c6bd1a5eea15cba15484fc729168a3f05d3d139647dc 001a5448 0000002c f4c6bd1a5eea15cba15484fc729168a3f05f3d00ae4ed7ef7f5b43 001a5474 0000002c f4c6bd1a5eea15cba15484fc729168a3c66e3f15897dd1e67c5b5f 001a54a0 0000002c f4c6bd1a5eea15cba15484fc72916fa3f05d3d139647dc 001a54cc 0000002c f4c6bd1a5eea15cba15484fc72916fa3f05f3d00ae4ed7ef7f5b43 001a54f8 00000024 f4c6bd1a5eea15cba15484fc72be45b3ca6e3702944cccd7715043675c 001a551c 0000002c f4c6bd1a5eea15cba15484fc72be45b3ca530d049e4bd6fc7d4c 001a5548 00000464 f4c6bd1a5eea15cba1549bfc76ad7199c65f341b 001a59ac 000000bc f4c6bd1a5eea1acfa65498e760ab6899c9503b189446 001a5a68 00000060 f4c6bd1a5eea1ec1b46fb7ed7ebe45aadb540d01947ddce96c5f 001a5ac8 00000030 f4c6bd1a5eea1ccba26e9ad77bba7f 001a5af8 00000020 f4c6bd1a5eea1dcda5548be472af6899cb5821049d43c1 001a5b18 00000058 f4c6bd1a5eea1dcda5548ce164be76a7d66e3b199c47dc 001a5b70 00000038 f4c6bd1a5eea1dcda5548ce164be76a7d66e3f118245 001a5ba8 00000034 f4c6bd1a5eea1dcda5548ee548a87bb2ce5d 001a5bdc 00000088 f4c6bd1a5eea1dcda55484ed739175a0c9 001a5c64 00000020 f4c6bd1a5eea1dcda55498fd639173a2c3540d00984fdde76d4a 001a5c84 00000020 f4c6bd1a5eea1dcda5549bed639178b3db453d1aae4cd7d7795d536b4b31 001a5ca4 00000254 f4c6bd1a5eea1dcda5549ced65a345b6dd5e35069451cb 001a5ef8 00000130 f4c6bd1a5eea02dcb07bda 001a6028 000001f8 f4c6bd1a5eea02dcb0788dfa61ab45a7de 001a6220 00001324 f4c6bd1a5eea02dcba688dfb649176b2ca 001a7544 00000004 f4c6bd1a5eea00cbb67e9afb7eb87f99df433704 001a7548 00000008 f4c6bd1a5eea00cbb96e89fb729168a3db433b118743d4d76a5b546d512d767e 001a7550 00000258 f4c6bd1a5eea00cba67f89fa63917ba5db443318 001a77a8 00000088 f4c6bd1a5eea02dcba688dfb64917daada540d179e46ddd76a5b4b6d453b 001a7830 0000022c f4c6bd1a5eea00cba67f89fa639174a9db 001a7a5c 00000004 f4c6bd1a5eea06cfa6789de5729179aeca5239 001a7a60 000009fc f4c6bd1a5eea06cba36e86fc48aa73b5df5d330d 001a845c 00000058 f4c6bd1a5eea07deb16a9ced48a26ea3f043372b9d4ddfef7d5a 001a84b4 00000058 f4c6bd1a5eea07deb16a9ced48a26ea3f043372b9f4dccd774514065413b 001a850c 00000058 f4c6bd1a5eea07deb16a9ced48a26ea3f044372b9d4ddfef7d5a 001a8564 00000058 f4c6bd1a5eea07deb16a9ced48a26ea3f044372b9f4dccd774514065413b 001a85bc 00000048 f4c6bd1a5eea07deb16a9ced48a26ea3df6e371092 001a8604 0000001c f4c6bd1a5eea07deb16a9ced48a26ea3df6e2711ae47ceed764a786b4a3b7063 001a8620 00000028 f4c6bd1a5eea07deb16a9ced48a26ea3df6e2711ae4cd7fc47524865433a71 001a8648 00000804 f4c6bd1e42d416f1b97f8dd774af79abca5c3100834ecad76a5b4071 001a8e4c 00000144 f4c6bd1e42d416f1b97f8dd773ab79a9cb54202b8347dffb 001a8f90 00003708 f4c6bd1e42d416f1b97f8dd767a176abca5c3100834ecad76a5b4071 001ac698 000012a4 f4c6bd1e42d416f1b97f8dd763af79aed65e3c2b8347dffb 001ad93c 00000178 f4c6bd1e42d416f1b97f8dd763a16399dd543507 001adab4 00000424 f4c6bd1e42d416f1b97f8dd762af68b2f043371382 001aded8 0000041c f4c6bd0242c706f1ba6d8ee47ea07f 001ae2f4 0000000c f4c6bd025dd62dcab47f89d774af79aeca6e30189e41d3d77e5252714c 001ae300 0000000c f4c6bd025dd62dcab47f89d774af79aeca6e30189e41d3d7625b556d 001ae30c 000000ac f4c6bd025dd62dcab47f89d774af79aeca6e33069443e7ee744b546a 001ae3b8 0000031c f4c6bd1a5eea13c2b9648be963ab45a4da5734118351 001ae6d4 000000c8 f4c6bd1a5eea14c2a07880d774ad7fa4dc 001ae79c 000000c0 f4c6bd1a5eea14c2a07880d772a26aabce 001ae85c 000000fc f4c6bd1a5eea02dcb0788dfa61ab45a3c3413f15ae41dbed7a4d 001ae958 00000040 f4c6bd1a5eea14c2a07880d772b87fa8db6e30019744ddfa 001ae998 00000064 f4c6bd1a5eea08cba7648de467a37b 001ae9fc 0000004c f4c6bd0648c606de8a7f9bfc48ff29 001aea48 0000004c f4c6bd0648c606de8a7f9bfc48ff2e 001aea94 0000004c f4c6bd0648c606de8a7f9bfc48fd28 001aeae0 0000004c f4c6bd0648c606de8a7f9bfc48fd29 001aeb2c 0000004c f4c6bd0648c606de8a7f9bfc48fd2e 001aeb78 0000004c f4c6bd0648c606de8a7f9bfc48fd2f 001aebc4 0000004c f4c6bd0648c606de8a7f9bfc48fd2c 001aec10 0000004c f4c6bd0648c606de8a7f9bfc48fd2d 001aec5c 0000004c f4c6bd0648c606de8a7f9bfc48fd22 001aeca8 0000004c f4c6bd0648c606de8a7f9bfc48fd23 001aecf4 0000004c f4c6bd0648c606de8a7f9bfc48fa2a 001aed40 0000004c f4c6bd0648c606de8a7f9bfc48fa2b 001aed8c 0000004c f4c6bd0648c606de8a7f9bfc48fa28 001aedd8 0000004c f4c6bd0648c606de8a7f9bfc48fa29 001aee24 0000004c f4c6bd0648c606de8a7f9bfc48fa2e 001aee70 0000004c f4c6bd0648c606de8a7f9bfc48fa2f 001aeebc 0000004c f4c6bd0648c606de8a7f9bfc48fa2c 001aef08 0000007c f4c6bd0648c606de8a7f9bfc48f92d 001aef84 00000038 f4c6bd0648c606de8a7f9bfc48f62b 001aefbc 00000038 f4c6bd0648c606de8a7f9bfc48f628 001aeff4 00000038 f4c6bd0648c606de8a7f9bfc48f629 001af02c 000000a0 f4c6bd0648c606de8a7f9bfc48f62e 001af0cc 00000038 f4c6bd0648c606de8a7f9bfc48f62f 001af104 00000034 f4c6bd0648c606de8a7f9bfc48f62c 001af138 00000068 f4c6bd0648c606de8a7f9bfc48f62d 001af1a0 000001a0 f4c6bd0648c606de8a7f9bfc48f622 001af340 000000c4 f4c6bd0648c606de8a7f9bfc48f72d 001af404 000000c4 f4c6bd0648c606de8a7f9bfc48f722 001af4c8 00000030 f4c6bd0648c606de8a7f9bfc48ff2af7ce 001af4f8 000000d8 f4c6bd0648c606de8a7f9bfc48ff2af7 001af5d0 00000030 f4c48d 001b7834 00000038 d7f3a73172f137ff804eb7cc46 001b786c 00000028 d7f3a73172e233e78154bcc15a8b5e 001b7894 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001b789c 00000060 fcdd8f1740d602d7 001b78fc 00000048 fcdd8f1740c617da 001b7944 00001368 d4e6bd0648c606f1b1629be975a27f 001b8cac 000014bc d4e6bd0648c606f1b06589ea7bab 001ba168 00000028 d4e6bd0648c606f1b06589ea7bab7e 001ba190 00000120 d4e6bd0648c606de 001ba2b0 00000028 f4c6bd0648c606de8a6a8cec48bd6ea7cc5a0d128343d5ed 001ba2d8 00000148 f4c6bd0648c606de8a6e9ee6639168a3df5e20009450 001ba420 000000b4 f4c6bd0648c606de8a678de665 001ba4d4 00000058 f4c6bd0648c606de8a7f9bfc48fb 001ba52c 00000038 f4c6bd0648c606de8a7f9bfc48f8 001ba564 00000138 f4c6bd0648c606de8a7f9bfc48f9 001ba69c 00000038 f4c6bd0648c606de8a7f9bfc48f6 001ba6d4 00000138 f4c6bd0648c606de8a7f9bfc48f7 001ba80c 00000038 f4c6bd0648c606de8a7f9bfc48ff2a 001ba844 0000002c f4c6bd0648c606de8a7f9bfc48ff2b 001ba870 00000028 f4c6bd0648c606de8a7f9bfc48ff28 001ba898 000000d4 f4c6bd0648c606de8a7f9bfc48ff2f 001ba96c 0000002c f4c6bd0648c606de8a7f9bfc48ff2c 001ba998 00000048 f4c6bd0648c606de8a7f9bfc48ff2d 001ba9e0 0000004c f4c6bd0648c606de8a7f9bfc48ff22 001baa2c 0000003c f4c6bd0648c606de8a7f9bfc48ff23 001baa68 0000003c f4c6bd0648c606de8a7f9bfc48fc2a 001baaa4 00000044 f4c6bd0648c606de8a7f9bfc48fc2b 001baae8 000000e0 f4c6bd0648c606de8a7f9bfc48fc2f 001babc8 000000e0 f4c6bd0648c606de8a7f9bfc48fc2c 001baca8 00000140 f4c6bd0648c606de8a7f9bfc48fc2d 001bade8 0000000c f4c6bd0648c606de8a7f9bfc48fa2d 001badf4 000000f8 f4c6bd0648c606de8a7f9bfc48fa22 001baeec 00000384 f4c6bd0648c606de8a7f9bfc48fb2a 001bb270 00000120 f4c6bd0648c606de8a7f9bfc48fb2b 001bb390 00000114 f4c6bd0648c606de8a7f9bfc48fb28 001bb4a4 0000006c f4c6bd0648c606de8a7f9bfc48fb2e 001bb510 00000070 f4c6bd0648c606de8a7f9bfc48fb2c 001bb580 00000080 f4c6bd0648c606de8a7f9bfc48fb2d 001bb600 00000040 f4c6bd0648c606de8a7f9bfc48f828 001bb640 00000138 f4c6bd0648c606de8a7f9bfc48f829 001bb778 000000b8 f4c6bd0648c606de8a7f9bfc48f82e 001bb830 00000044 f4c6bd0648c606de8a7f9bfc48f82f 001bb874 00000044 f4c6bd0648c606de8a7f9bfc48f82c 001bb8b8 00000120 f4c6bd0648c606de8a7f9bfc48f82d 001bb9d8 00000114 f4c6bd0648c606de8a7f9bfc48f823 001bbaec 000000d8 f4c6bd0648c606de8a7f9bfc48f92a 001bbbc4 000000f8 f4c6bd0648c606de8a7f9bfc48f928 001bbcbc 000000c4 f4c6bd0648c606de8a7f9bfc48f929 001bbd80 00000048 f4c6bd0648c606de8a7f9bfc48f92e 001bbdc8 0000006c f4c6bd0648c606de8a7f9bfc48f92c 001bbe34 00000274 f4c6bd0648c606de8a7f9bfc48f922 001bc0a8 00000164 f4c6bd0648c606de8a7f9bfc48f72c 001bc20c 0000013c f4c6bd0648c606de8a7f9bfc48ff2af4 001bc348 000004a4 f4c6bd0648c606de8a7f9bfc48ff2afe 001bedec 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001bedf4 00000060 fcdd8f1740d602d7 001bee54 0000004c d4e6bd1548c12dcdba7e98e472aa45a5dd50211cae56d9fa7f5b535d4a3061 001beea0 000000ec d4e6bd1b4adb1ddcb0548bf87baa45a5dd50211cae43d4ff794754 001bef8c 00000064 d4e6bd1548c12dcdba7e98e472aa45a5dd50211c 001beff0 000000b0 d4e6bd0048c606cfa77fb7e974ba6fa7c3 001bf0a0 000000c4 d4e6bd1159c71ed48a7f8dfa7aa774a7db583d1a 001bf164 0000000c d4e6bd065dc62dc9b07f 001bf170 00000038 d4e6bd065dc62dddb07f 001bf1a8 00000144 f4c6bd115fd401c68a6f9de567916aa7cb55 001bf2ec 00000064 f4c6bd1644c602c2b472b7ee76a776a3cb 001bf350 0000005c f4c6bd1644c602c2b472b7ec62a36a99c9503b189446 001bf3ac 000001d4 f4c6bd115fd401c68a6f9de567917fb1dd582611 001bf580 0000005c f4c6bd1644c602c2b472b7e17ba845a5c35e2111ae44d9e1745b43 001bf5dc 00000170 f4c6bd1b4adb1ddcb0548de676ac76a3f05c3d1a9856d7fa475848707b2d70686d1bf411 001bf74c 000001dc f4c6bd1b4adb1ddcb05498fa78a36ab2f0573d06ae45d7 001bf928 00000040 f4c6bd1d4ec52ddab07985d767bc75a1dd542107 001bf968 00000088 f4c6bd1b43d12dc1a5548be77abe76a3db54 001bf9f0 00000028 f4c6bd1e42d416f1b97f8dd770a26fa3f0433713827dd9fd60 001bfa18 00000040 f4c6bd1142d802dba16eb7e463ab45a3cb52 001bfa58 00000020 f4c6bd115fd401c68a6f9de567917ea9c154 001bfa78 00000050 f4c6bd115fd401c68a6f9de567916ab4ca41 001bfac8 00000020 f4c6bd1755c513c0a66287e648a0 001bfae8 000000cc f4c6bd1d58c102dba1548eed48ac76a9cc5a 001bfbb4 00000cb0 d4e6bd025fd001cba77d8dd772b87fa8db42 001c0864 00000034 f4c6bd0242c217dcba6d8ed773ab69afdd5436 001c0898 00000050 f4c6bd025fd0029f 001c08e8 0000014c f4c6bd025fd0029c 001c0a34 00000084 f4c6bd0048c51ecfb66eb7eb759179a7cc6e311c904bd6 001c0ab8 00000f0c f4c6bd1e42d416f1b97f8dd77ea07ca9 001c19c4 00000154 f4c6bd0048c606cfa77fb7e179a76e 001c1b18 000004a0 f4c6bd0148db16f1b96a9bfc48a97bb5df 001c1fb8 00000170 f4c6bd075dd113dab05484fc72a06c 001c2128 00000288 f4c6bd0048c606cfa77fb7e678ba 001c23b0 00000c84 f4c6bd115fd401c68a6f9de567917fa8db58261d9451 001c3034 0000092c f4c6bd115fd401c68a6f9de567 001c3960 00000258 f4c6bd0048c606cfa77f 001c3bb8 00000190 f4c6bd0048c606cfa77fb7e974ba73a9c1 001c3d48 00000658 f4c6bd134ec107cfb9549ced65a36ab4 001c43a0 00000158 d4e6bd0a72c117dcb86286e963ab45a5db5d 001c6828 00000024 d7f3a73172f137e29c45a3d7539f 001c684c 00000038 d7f3a73172f137ff804eb7cc46 001c6884 0000001c d7f3a73172f03cff804eb7cc46 001c68a0 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001c68b8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001c68c0 00000060 fcdd8f1740d602d7 001c6920 00000174 d4e6bd134ec11bd8b07ab7fa72af7e99ca47371a85 001c6a94 0000007c d4e6bd134ec11bd8b07ab7fb72bd69afc05f0d179d4dcbed 001c6b10 000001f0 d4e6bd134ec11bd8b07ab7fb72bd69afc05f0d1b8147d6 001c6d00 00000018 d4e6bd1648d411dabc7d89fc729179b5c3550d079247d4 001c6d18 0000016c d4e6bd1548c12dcba36e86fc48bd7fb7da543c17947dddf06c5b497657 001c6e84 000000fc d4e6bd1548c12dc0a3549ced61ab74b2f0542a00944cccfb 001c6f80 000000b0 d4e6bd1e48c72ddcb0788dfc48a774b2ca4324159d 001c7030 000000f0 d4e6bd1e48c72dddb07fb7e179ba7fb4d9503e 001c7120 000000a8 d4e6bd1e48c72ddab0789cd77ea06ea3dd473318 001c71c8 00000300 d4e6bd1e42d613dab0548dfe72a06e99c65f341b 001c74c8 000001a8 d4e6bd1f4bd62dcca06284ec 001c7670 00000090 d4e6bd1f4bd62ddcb67d8cd774bd76a2f05221119d7dcaed795a5e 001c7700 00000104 d4e6bd1f4bd62ddcb67d8cd772a26a99dc4533008451 001c7804 00000098 d4e6bd1f4bd62ddcb67d8cd771ab78b6 001c789c 000000d4 d4e6bd1f4bd62ddcb67d8cd771ab78b6f04226158557cb 001c7970 0000011c d4e6bd1f4bd62ddcb67d8cd77aab7baaca5d222b9454dde66c 001c7a8c 000000b4 d4e6bd1f4bd62ddcb67d8cd77aab7baaca5d222b8256d9fc6d4d 001c7b40 000000bc d4e6bd1f4bd62ddcb67d8cd764ad7faac36e36119d 001c7bfc 00000094 d4e6bd1f4bd62ddcb67d8cd763ab73b5df 001c7c90 000000d4 d4e6bd1f4bd62ddcb67d8cd763ab73b5df6e21009056cdfb 001c7d64 0000025c d4e6bd1f4bd62dddb0658c 001c7fc0 000000b8 d4e6bd1f4bd62dddb0658cd774af76aacd50311f 001c8078 00000064 d4e6bd1f4bd62dddb0658ce4709179a7c35d30159249 001c80dc 000000ac d4e6bd1f4bd62dddb0658ce572af76b5c26e31159d4edae97b55 001c8188 000001d0 d4e6bd025fda11cba678b7e572af7699cc5e3f199856 001c8358 000000e8 d4e6bd0048c100c7b07d8dd779b845b2ca47371a857dd1e67e51 001c8440 000001a8 d4e6bd0048c100c7b07d8dd763ab6ca3c1450d1d9f44d7 001c85e8 00000140 f4c6bd1145d011c58a6e9eed79ba45a3c145200d 001c8728 0000002c f4c6bd1145d011c58a6d8dea48ab7ea4c16e24159d4bdc 001c8754 000001b8 f4c6bd1145d011c58a6d87fa74ab7e 001c890c 0000018c f4c6bd1145d011c58a6287 001c8a98 00000138 d4e6bd1648c606dcba72b7eb64a27e99dc523718 001c8bd0 000001d0 f4c6bd1142db04cba77fb7ed7ebe2af6f0453d2b944bc8b95b7a 001c8da0 000000b8 f4c6bd1648d411dabc7d89fc72917faadf 001c8e58 000005b8 f4c6bd1644c602c2b472b7fb74ab76abc6 001c9410 00000008 f4c6bd1548c12dcdb06989 001c9418 0000006c f4c6bd1b43c507da8a6d8dd775a275a5c4 001c9484 00000230 f4c6bd1e42d416f1b06798 001c96b4 000002b4 f4c6bd025fda11cba678b7eb7bab7ba8f04422 001c9968 0000057c f4c6bd025fda11cba678b7eb64a27e99dc5226119d7dcdf87c5f5367 001c9ee4 000005f0 f4c6bd025fda11cba678b7ee72ac45a4c35e311f92 001ca4d4 0000033c f4c6bd025fda11cba678b7ee72ac45b5cc543e 001ca810 00000560 f4c6bd0048c51ddca1548de048be76 001cad70 00000140 f4c6bd0048c51ddca1548de048aa7caa 001caeb0 000003c4 d4e6bd0048c51ddca1548dfe72a06e99c7503c109d47ca 001cb274 000002e8 d4e6bd1f4bd62ddcb67d8cd772a26a99ca47371a85 001cb55c 00000548 d4e6bd1f4bd62ddcb67d8cd77baf69b2f0563307817ddde468614274413161 001cbaa4 00000440 d4e6bd1e48c72ddeb07981e773a77999cc5937179a 001cbee4 000000fc d4e6bd1f4bd62ddcb67d8cd766bb73a3dc5237 001cbfe0 00000434 d4e6bd0358dc17ddb66e 001cc414 000000b0 f4c6bd014ed01ecdb7549df873af6ea3cb 001cc4c4 00000190 f4c6bd014ec117c2b669b7fd67aa7bb2ca55 001cc654 000006d0 f4c6bd025fda11cba678b7eb64a27e99dc5226119d7dd5e9715053 001ccd24 0000012c f4c6bd075dd113dab0549beb72a27ba4ce6e371a8550c1 001cce50 00000780 f4c6bd025fda11cba678b7ed7bbe 001cd5d0 00000258 f4c6bd0242c507c2b47f8dd774ad 001cd828 00000938 f4c6bd025fda11cba678b7eb64a27e99dc523718ae4fd9e1764a 001ce160 00001fd8 d4e6bd025fda11cba678 001d3f9c 0000000c d7f3a73172fc3ce78154acd9 001d3fa8 00000038 d7f3a73172f137ff804eb7cc46 001d3fe0 0000001c d7f3a73172f03cff804eb7cc46 001d3ffc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001d4004 00000060 fcdd8f1740d602d7 001d4064 00000048 fcdd8f1740c617da 001d40ac 0000006c d4e6bd1749d62d9de7 001d4118 00000058 d4e6bd1548c12dcda0799aed79ba45b3df453b1994 001d4170 0000000c d4e6bd1548c12dc2a16eb7e565bb45afc155370c 001d417c 00000148 d4e6bd1548c12dc2a16eb7fb72bf7499db520d159f46e7fc684d 001d42c4 0000000c d4e6bd1548c12dddbc718de771917cabf0422b07924dd5 001d42d0 0000023c d4e6bd1b43d62ddba57f81e572 001d450c 000000e0 d4e6bd0148c12dc7b26587fa729169adc6413e009450ddeb7b564c 001d45ec 00000030 d4e6bd0645dc01f1bc78b7fc78916db4c645372b9250d9fb70614377492f 001d461c 0000013c d4e6bd075dd113dab05481e471917eafdc5a0d1d9f44d7 001d4758 000000f8 d4e6bd075dd113dab05484e964ba45a1ce42222b984cdee7 001d4850 00000060 d4e6bd0848c71dcbb97b85e9 001d48b0 00000010 f4c6bd135ec607c3b05489fa70af45a1db6e33069640 001d48c0 00000014 f4c6bd135ec607c3b05489fa70af45aaca6e33069640 001d48d4 00000010 f4c6bd135ec607c3b05489fa70af45aadb6e33069640 001d48e4 00000014 f4c6bd135ec607c3b05489fa70af45a8ca6e33069640 001d48f8 00000198 f4c6bd135ec607c3b0548be072ad71 001d4a90 000000c0 f4c6bd1142db04cba77fb7e97ba245aadb5421 001d4b50 000000b8 d4e6bd1548c12dc2a16eb7ed6fba7fa8db42 001d4c08 0000006c f4c6bd1142c002c2b06fb7fc72bc77afc150261d9e4c 001d4c74 000000c8 f4c6bd1648c407cb8a6f99 001d4d3c 0000013c f4c6bd1644c613c2b9649fd77bba7f99dd5431018351d1e776 001d4e78 00000088 f4c6bd1644c602c2b472b7e572a375b4d66e3915 001d4f00 00000114 f4c6bd1644c602c2b472b7e572a375b4d6 001d5014 00000094 f4c6bd1644c602c2b472b7fb76aa 001d50a8 0000008c d4e6bd1644c602c2b472b7fb76 001d5134 00000158 f4c6bd1644c602c2b472b7fb63af79adf0583c129e 001d528c 00000138 f4c6bd1741c51fcf8a789cfa62ad6eb5f05e39 001d53c4 00000148 f4c6bd1743c407cb8a6f99 001d550c 000001c4 f4c6bd1548c12dcfb1619dfb63ab7e99c2502a2b944bc8d76b575d67 001d56d0 000001c4 f4c6bd1548c12dcfb1619dfb63ab7e99c2502a2b944ec8d77d48426c50006672631f 001d5894 00000190 f4c6bd1542da16c2a16e 001d5a24 0000003c f4c6bd1542da16cfb96784fc72bd 001d5a60 000000bc f4c6bd1b43dc06f1a07b9ce17aab 001d5b1c 000000ac f4c6bd1b5eea02dcb07f8de673916ea3dd5c 001d5bc8 0000002c f4c6bd1f48d41ef1b6638deb7c917cabca6e3710934ce7fe79524e66 001d5bf4 000000e0 f4c6bd1f48d41ef1bc6598fd639177a3f0533e1b9249 001d5cd4 000000e0 f4c6bd1f48d41ef1bc6598fd63917cabca6e30189e41d3 001d5db4 000000d4 f4c6bd1f48d41ef1ba7e9cf862ba45abca6e30189e41d3 001d5e88 000000d4 f4c6bd1f48d41ef1ba7e9cf862ba45a0c2540d169d4ddbe3 001d5f5c 000000bc d4e6bd1f48d41ef1b6678de965 001d6018 0000010c f4c6bd1f48d811deac 001d6124 0000025c f4c6bd1e42d22dc2a16eb7fd79ab62b6ca522611957dddfe7d505371 001d6380 0000028c f4c6bd1e42d22dc2a16eb7fa72ad6fb4dc582411ae47ceed764a54 001d660c 00000114 f4c6bd1f48d801cba1 001d6720 000002bc f4c6bd1e42d22dc2a16eb7e179a875 001d69dc 000000a8 f4c6bd1e42d22dc2a16e9b 001d6a84 000002f0 f4c6bd1644c34b98 001d6d74 00000160 d4e6bd0648c71fc7bb6a9ced48a774afdb 001d6ed4 00000aac d4e6bd0148c700f1bc6581fc 001d7980 00000050 d4e6bd1548c12dcabc7898e476b745b5db50311fae4bd6ee77 001d79d0 00000038 d4e6bd1341d91dcdb47f8dd774aa72a5 001d7a08 00000114 f4c6bd1f58d94b98 001d7b1c 000000a4 d4e6bd1548c12dc2b0549beb7aa745b2c65c37 001d7bc0 00000058 d4e6bd1548c12dddb66681d763a777a3 001d7c18 00000098 f4c6bd1f48d41ef1b6699df873af6ea3cb 001d7cb0 00000074 f4c6bd025fda11cba678b7e463ab69 001d7d24 000000b8 f4c6bd0048d61ddcb1549aed74bb68b5c647372b9454dde66c 001d7ddc 00000224 f4c6bd0048d61ddcb1549de672b66aa3cc453710ae47ceed764a 001d8000 0000079c f4c6bd1f48d41ef1a5798dfb72bc6ca3f05424119f56cb 001d879c 00000068 f4c6bd0145da05f1b96a9bfc48a87bafc344201195 001d8804 00000070 d4e6bd0145da05f1b96a9bfc48a87bafc3442011 001d8874 00000028 f4c6bd0159c71ecbbb 001d889c 00004d54 f4c6bd1145d011c58a789cfa62ad6e99c05734079456cb 001dd5f0 00000054 f4c6bd0159c71ccda572b7ea729176a3 001dd644 000004e4 f4c6bd064eea16c7a67b84e96e 001ddb28 000002b4 f4c6bd025fd006cbbb6fb7fc72bc77 001ddddc 00000348 f4c6bd054cd919f1b47ab7ed61ab74b2dc55 001de124 0000009c d4e6bd054cd919f1b47ab7ed61ab74b2dc 001de1c0 00000058 f4c6bd054cd919f1b6688dfe72a06e99cd4434129450cbd77d5a456c573b 001de218 00000060 d4e6bd054cd919f1b6688dfe72a06e99cd4434129450cbd77d5a456c57 001de278 0000007c f4c6bd054cd919f1b6688dfe72a06e99cd4434129450cbec 001de2f4 00000060 d4e6bd054cd919f1b6688dfe72a06e99cd4434129450cb 001de354 00000288 f4c6bd054cd919f1b07d8de6639178b3c95737069046e7eb705b4469 001de5dc 0000010c f4c6bd054cd919f1b07d8de6639178b3c95737069046 001de6e8 00000064 d4e6bd054cd919f1b07d8de6639178b3c9573706 001de74c 00000020 d4e6bd054cd919f1b07d8de6639178b3c957370690 001de76c 0000030c f4c6bd1f48d41ec3bc548ce164be76a7d6 001dea78 0000075c f4c6bd1f48d41ef1b86a81e663 001df1d4 000004c4 f4c6bd1f48d41ef1b66485e57eba 001df698 00000494 f4c6bd1f48d41ef1b76787eb7cad45a0c254 001dfb2c 00000298 f4c6bd1f48d41ef1a76e8be779ad73aaca6e341994 001dfdc4 000003bc d4e6bd1f48d41ef1b07d8de663917da3db 001e0180 00000088 f4c6bd054cd919f1b86e89e448ab6ca3c1452110 001e0208 0000007c d4e6bd054cd919f1b86e89e448ab6ca3c14521 001e0284 00000080 f4c6bd054cd919f1a6688de476ac7b99ca532110 001e0304 00000060 d4e6bd054cd919f1a6688de476ac7b99ca5321 001e0364 00000070 f4c6bd054cd919f1a6688de476ac7ba2 001e03d4 00000060 d4e6bd054cd919f1a6688de476ac7b 001e0434 00000080 f4c6bd054cd919f1a16e9eed79ba69a2 001e04b4 00000070 d4e6bd054cd919f1a16e9eed79ba69 001e0524 0000008c f4c6bd0848c71dc2a16e 001e05b0 0000003c d4e6bd0848c71dcfb96784fc72bd 001ec544 00000024 d7f3a73172f137e29c45a3d7539f 001ec568 00000028 d7f3a73172f436ea8a58b9 001ec590 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 001ec5d4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001ec5dc 000000d4 dafbbd0244da00f1b77e81e4739177a0cc 001ec6b0 00000074 dafbbd0244da00f1b46883d77aa879 001ec724 00000088 fadbbd1f4cc606cba7549aed76aa6399cc5e220d 001ec7ac 000000d0 fadbbd1f4cc606cba7549aed76aa45a0c65f3b079947dc 001ec87c 00000054 fadbbd1f4cc606cba7549bed79aa45b2c06e22069e5ac1 001ec8d0 000000f0 dafbbd1f5fc216f1b77e81e4739177a0cc 001ec9c0 00000014 fadbbd1548c12ddea76490f148a66ea4 001ec9d4 00000108 dafbbd1f4cc606cba7548ce748be68a9d7483b1b 001ecadc 0000003c fadbbd145fd017f1a57987f06e9172b2cd 001ecb18 00000014 dafbbd145fd017f1a57987f06e9162a2 001ecb2c 00000054 fadbbd145fd017f1b46784d767bc75bed66e2a1082 001ecb80 0000002c dafbbd025fda0ad78a6887f86e917bb3db5e21119f51dd 001ecbac 00000238 dafbbd025fda0ad78a7c8ad77aa16ca3f0413306854bd9e4 001ecde4 00000090 dafbbd025fda0ad78a7c8ad767af68b2c6503e2b994bcc 001ece74 0000007c fadbbd025fda0ad78a7b87fb63916fa8c645 001ecef0 00000124 dafbbd025fda0ad78a799fd774a174b2c65f2711 001ed014 000000cc dafbbd025fda0ad78a6287d773a174a3 001ed0e0 000000e8 dafbbd1f5fc216f1b46883d77aa879 001ed1c8 00000178 fadbbd1a59d72dd9b478b7ee78bb74a2f05e3c2b984cc8fa775d56 001ed340 00000140 fadbbd025fda0ad78a798dfb63af68b2f0523d199c43d6ec 001ed480 0000008c fadbbd025fda0ad78a6d9aed729168a3dc5e27069247 001ed50c 00000198 fadbbd1f4cc606cba7549ced65a373a8ce45372b924dd5e5795043 001ed6a4 000000dc dafbbd025fda0ad78a649ce072bc45a5c05f26069e4ed4ed6a614e717b387a757c 001ed780 00000084 fadbbd1548c12ddea76490f148b67eb5 001ed804 000000f0 fadbbd025fda0ad78a788de673916ea9f05c33078547ca 001ed8f4 0000011c dafbbd025fda0ad78a798de9739176a9c156 001eda10 00000038 dafbbd025fda0ad78a6689fa7c9178abc95d3313 001edbbc 00000024 d7f3a73172f137e29c45a3d7539f 001edbe0 0000001c d7f3a73172f03cff804eb7cc46 001edbfc 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001edc14 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001edc1c 00000008 f5ce963b63e331ef 001edc24 00000024 f5ce96255ffd1bc9bd5c89fc72bc 001edc48 00000024 f5ce96255ff91dd9826a9ced65 001edc6c 000006f4 fadbbd1c48c22dcdba659ce179bb7f 001ee360 00000118 dafbbd0148db16f1af6e9ae748aa7bb2ce 001ee478 000001d0 fadbbd0148db16f1b16a9ce9 001ee648 00000080 fadbbd1142d802c2b07f8dd764ab74a2f055330090 001ee6c8 00000080 fadbbd0048d617c7a36eb7fb74bd7399cb502615 001ee748 00000080 fadbbd1142d802c2b07f8dd765ab79a3c647372b9543cce9 001ee7c8 00000184 fadbbd1548c12dcca06d8ed776a07e99d7550d179e57d6fc 001ee94c 0000148c fadbbd1c48c22ddbbb7e9bfd76a2 001efe70 00000024 d7f3a73172f137e29c45a3d7539f 001efe94 0000001c d7f3a73172f03cff804eb7cc46 001efeb0 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001efec8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001efed0 00000008 f5ce963b63e331ef 001efed8 00000024 f5ce96255ffd1bc9bd5c89fc72bc 001efefc 00000024 f5ce96255ff91dd9826a9ced65 001eff20 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 001eff34 000003b4 fadbbd0048c107dcbb5480fc75 001f02e8 0000000c f6d88b2d48cd11cba57f81e779 001f02f4 00000230 dafbbd1058dc1eca8a789bef7b917ba8cb6e20119046 001f0524 000000b8 fadbbd1142db06c7bb7e8dd760ac45a5ce523a11 001f05dc 0000035c fadbbd0048d416f1b66a8be0729177afdc42 001f0938 00000098 fadbbd1142d802c2b07f8dd765ad6c99cc50311c947ddce96c5f 001f09d0 000002a4 fadbbd0048d617c7a36eb7ec76ba7b 001f0c74 00000088 dafbbd0048d617c7a36eb7eb76ad72a3f055330090 001f0cfc 000001b4 fadbbd0148db16f1bb649ae576a245b5cc423b2b8256d9fc6d4d 001f0eb0 00000034 fadbbd1444db1bddbd549beb64a7 001f0ee4 00000050 fadbbd1142d802c2b07f8dd764ab74a2f04226158557cb 001f0f34 00000bfc dafbbd1c48c2 001f1b30 00000114 fadbbd054fea15c1a1548ce963af45abc64221 001f1c44 000000fc dafbbd054fea15cba15480e764ba45a2ce4533 001f1d40 000000f0 fadbbd054fea11cfb6638dd77aa769b5 001f1e30 000000e4 fadbbd1142d802c2b07f8dd760ac45a1ca450d1c9e51ccd77c5f5363 001f1f14 0000009c fadbbd054fea16c1bb6e 001f1fb0 00000114 dafbbd054fea14c2a07880d773a174a3 001f20c4 0000032c fadbbd0148c107de8a6d8bd764ab74a2f055330090 001f23f0 000001a4 dafbbd0148db16f1b66a8be072917ea7db50 001f2594 000000cc fadbbd0148db16f1b16a9ce948ad7ba5c754 001f2660 000001ac fadbbd0048d416f1b66a8be0729172afdb 001f280c 000000b4 fadbbd1142d802c2b07f8dd764ab74a2f05233179947e7ec794a46 001f28c0 000000bc fadbbd1142db06c7bb7e8dd765ab7ba2f05233179947 001f297c 0000007c fadbbd145fd017f1a6788fe4 001f29f8 0000019c fadbbd1b42ea16c1bb6e 001f2b94 00000048 d7f3a73172f237fa8a4abbd1598d5299fe6417 001f2bdc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001f2be4 00000158 dafbbd1640d42dc7a679 001f2d3c 00000274 dafbbd015dc71bdab05485e164ad75abdf502011ae4bcbfa 001f2fb0 0000001c d7f3a73172f03cff804eb7cc46 001f2fcc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001f2fd4 00000578 fadbbd1b43d411daa45480e979aa76a3dd 001f354c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001f3554 00000188 fadbbd0258c12dddb67881d77ebd68 001f36dc 00000174 fadbbd0258c12ddeb07a 001f3850 000002f0 fadbbd1d58c110c1a0658cd774a3 001f3b40 00000268 fadbbd1b43d71ddbbb6fb7eb7a 001f3da8 000001b4 fadbbd144ec52dcbad6880d774a3 001f3f5c 00000150 fadbbd014ec71bdea1549aed64be75a8dc54 001f40ac 000003f4 fadbbd0743de1cc1a265b7ee65af77a3 001f44a0 000007b8 fadbbd0743c001dbb467b7eb7a 001f4c58 00000100 dafbbd0258d91ef1bc789a 001f4d58 00000034 fadbbd1c5dda00da8a679df848b87fb4c6572b 001f4d8c 00000148 fadbbd1e5dda00da8a679df848b87fb4c6572b 001f4ed4 0000003c fadbbd1e58c52dd8b07981ee6e 001f4f10 00000454 fadbbd145fd41fcb8a6689e676a97fb4f0523f 001f5364 000000e0 fadbbd064cd61af1a76e9bfd7aab 001f5444 000001e8 fadbbd175fc71ddc8a628ce4729179ab 001f562c 000001f8 fadbbd1341d92dcca07fb7eb7a 001f5824 000000b8 fadbbd064cd61af1b0799ae765 001f5914 00000024 d7f3a73172f137e29c45a3d7539f 001f5938 00000038 d7f3a73172f137ff804eb7cc46 001f5970 0000001c d7f3a73172f03cff804eb7cc46 001f598c 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001f59a4 00000028 d7f3a73172f436ea8a58b9 001f59cc 0000002c d7f3a73172f436ea8a58b9d75f8b5b82 001f59f8 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 001f5a24 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001f5a2c 000003b4 fadbbd0048c107dcbb5480fc75 001f5de0 00000020 fadbbd1145d011c58a7a9de172bd79a3f0443c1d85 001f5e00 0000016c fadbbd1548c12dcdb46880ed73917fb0ca5f26 001f5f6c 00000100 fadbbd1058dc1eca8a6e86f8 001f606c 00000034 fadbbd1058dc1eca8a798dfb72ba45a5dc543e 001f60a0 0000011c fadbbd1743c52dcfb660 001f61bc 00000038 fadbbd0048c617da8a689bed7b917ba5c4 001f61f4 000000c8 dafbbd175bd01cda8a788de663 001f62bc 00000034 fadbbd145fd017f1bd7f8a 001f62f0 00000090 fadbbd1548c12dddb66f8afb 001f6380 00000038 fadbbd1548c12dddb66f8afb48ac76a9cc5a 001f63b8 00000088 fadbbd1548c12dddb67881d773af6ea7 001f6440 00000038 fadbbd0144d21ccfb95480fc759178b7 001f6478 000003b8 fadbbd1a42d916f1b1629afc6e916ea9f0583c159256d1fe7d 001f6830 00000088 fadbbd1058dc1eca8a6e80e6 001f68b8 000000b0 fadbbd1745db2dcfb660 001f6968 0000007c fadbbd1f44c700c1a7548dfe72a06e99dc543c00 001f69e4 00000198 dafbbd1c42c11bc8ac5480e764ba69 001f6b7c 000003a8 fadbbd175bd01cda8a6286fb72bc6e 001f6f24 00000094 dafbbd0048d416d78a678cfb75 001f6fb8 00000120 fadbbd0148db06f1b06a9ae46e9169b2ce452707 001f70d8 00000418 fadbbd0148db16f1b06a9ae46e9169b2ce452707 001f74f0 0000016c fadbbd0148db16f1a6689be148aa7bb2ce 001f765c 000000d4 fadbbd1142d802c2b07f8dd771bb74add66e21009056cdfb 001f7730 0000003c fadbbd1349d12ddbbb629c 001f776c 00000108 dafbbd0048d81dd8b0549de67eba 001f7874 00000120 dafbbd054cc71cf1a06581fc 001f7994 000000f8 dafbbd0743c213dcbb549de67eba 001f7a8c 00000004 dafbbd0148c12dcaa0789ce963ab 001f7a90 00000388 dafbbd0648c606f1a1798ded48bc7fb5ca432415854bd7e66b 001f7e18 000000f8 dafbbd155fda07de8a789ce963bb6999cc59331a9647dcd76d5f 001f7f10 0000010c fadbbd144cdc1ec1a36e9ad772b87fa8db 001f801c 0000006c dafbbd144cdc1eccb46883 001f8088 0000005c dafbbd144cdc1ec1a36e9a 001f80e4 000000d0 fadbbd145fd017f1b97e86d763af78aaca 001f81b4 000000e0 fadbbd145fd017f1a06a98fa 001f8294 00000130 fadbbd1a4cdb16c2b05481e675a16fa8cb6e3706834dca 001f83c4 00000048 fadbbd1a4cdb16c2b0548fe963ab45a2c0463c2b9956da 001f840c 000000e8 fadbbd1a4cdb16c2b05486e748ba7ba5c76e33179247cbfb 001f84f4 000003f0 fadbbd0148db16f1a6689be148bd6ea7db4421 001f88e4 0000002c fadbbd1e4ed12dc2b06f 001f8910 00000198 fadbbd0542c719f1a76e99d77faf74a2c35420 001f8aa8 00000188 fadbbd0542c719f1bb6486d775a27199dd54232b9943d6ec745b55 001f8c30 00000020 fadbbd1c42ea05c1a760b7fa72bf69 001f8c50 0000004c fadbbd1145d011c58a6d87fa48b968afdb540d00984fdde76d4a7861453379797819ed 001f8c9c 00000048 fadbbd1a59d72dd9b4629ce179a945a0c0430d109056d9 001f8ce4 00000220 fadbbd1145d011c58a6d87fa48b968afdb540d00984fdde76d4a 001f8f04 000000b0 fadbbd0148c107de8a6e9eed79ba45a2ce4533 001f8fb4 000001f0 fadbbd0148db16f1b07d8de663917ea7db50 001f91a4 000002a8 fadbbd0148c107de8a6587fc48bc7fa7cb48 001f944c 00000114 fadbbd0145dc02f1b77e9bf1 001f9560 00000378 fadbbd0148db16f1b77e9bf1 001f98d8 00000150 fadbbd1058c60bf1bd6a86ec7bab68 001f9a28 0000026c fadbbd0248db16c7bb6cb7ff78bc7199dc45330685 001f9c94 0000012c fadbbd1c48c22dcca07891d77ea07ca9 001f9dc0 0000008c fadbbd1c48c22dcca07891d77ea07ca9f0582106 001f9e4c 00000050 fadbbd0048c107dcbb548afd64b7 001f9e9c 000000ac fadbbd1a4cdb16c2b0548afd64b745aedb53 001f9f48 000000ac fadbbd1a4cdb16c2b05484e7609168a3dc5e27069247e7e06c5c 001f9ff4 0000008c fadbbd1a4cdb16c2b05481e663ab68a8ce5d0d15934dcafc 001fa080 000001b4 fadbbd1142d802c2b07f8dd764ad69af 001fa234 000005a4 fadbbd025fda11cba678b7ed65bc75b4 001fa7d8 00000088 fadbbd0148db16f1a67f89e47bab7e99c65e 001fa860 0000010c fadbbd1a4cdb16c2b0549bfc76a276a3cb6e3b1b 001fa96c 000000cc fadbbd0159d41ec28a7e86e163916eafc254202b9943d6ec745b55 001faa38 000004b0 fadbbd1145d011c58a7b87fa639179a0 001faee8 00000030 fadbbd0242ea17dca7649a 001faf18 00000030 fadbbd055dea17dca7649a 001faf48 000000b8 fadbbd104cd12ddcb07a9ded64ba 001fb000 000000c0 fadbbd1b43c313c2bc6fb7e475af 001fb0c0 00000064 fadbbd104cd12ddeb47989e572ba7fb4 001fb124 00000044 fadbbd1145d011c58a6387fb639178b3c9573706ae4edde67f4a4f 001fb168 00000054 fadbbd0148db16f1a6689be148aa7bb2ce6e331a957dcbfc794a5271 001fb1bc 000000b4 fadbbd104cd12dc2ba658fd77bab74a1db59 001fb270 0000006c fadbbd0148c107de8a6e81f826ac 001fb2dc 000017c0 fadbbd0545d406dd8a7e98 001fdc64 00000024 d7f3a73172f137e29c45a3d7539f 001fdc88 00000038 d7f3a73172f137ff804eb7cc46 001fdcc0 00000028 d7f3a73172f436ea8a58b9 001fdce8 0000005c d7f3a73172e737e39a5dadd7449f 001fdd44 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001fdd4c 000000f8 dafbbd0358dc17ddb66eb7ec65a345abca5c3011837dc8fa7d4e467041 001fde44 000001dc dafbbd0358dc17ddb66eb7fd79a76e 001fe020 000001d8 dafbbd0358dc17ddb66eb7fd79a76e99ce422b1a924a 001fe1f8 000001c0 dafbbd0358dc17ddb66eb7fd79a76e99c75e2100 001fe3b8 000001b8 dafbbd0358dc17ddb66eb7fd79a76e99c75e2100ae46ddee7d4c556740 001fe570 000001bc fadbbd0358dc17ddb66eb7fd79a76e99c75e2100ae44cae77561547b4a3c 001fe72c 00000284 dafbbd0358dc17ddb66eb7fd79a76e99c25820069e50 001fe9b0 000001ac dafbbd0358dc17ddb66eb7fd79a76e99db433711ae4ad7fb6c614367423a67697c1e 001feb5c 000000f0 dafbbd0358dc17ddb66eb7fd79a76e99db433711ae52caed685f5567 001fec4c 000002e4 dafbbd0159d41ec28a7e86e163 001fef30 00000148 dafbbd0743c606cfb967b7fd79a76e 001ff078 0000016c dafbbd0743c407c7b0788bed48bb74afdb6e3a1b8256 001ff1e4 000001e8 dafbbd0743c407c7b0788bed48bb74afdb6e26069447e7e0774d53 001ff3cc 00000220 dafbbd0743c407c7b0788bed48bb74afdb 001ff66c 00000024 d7f3a73172f137e29c45a3d7539f 001ff690 0000001c d7f3a73172f03cff804eb7cc46 001ff6ac 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 001ff6c4 00000028 d7f3a73172f436ea8a58b9 001ff6ec 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 001ff730 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 001ff738 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 001ff74c 0000004c fadbbd1145d011c58a6e8ae163 001ff798 00000058 fadbbd1b42ea17cdbd6e8be348aa75a8ca 001ff7f0 000001a0 fadbbd1e42d619f1b66484e47ebd73a9c1 001ff990 00000408 fadbbd1e42d619f1b3679dfb7f9168a3dc443f11 001ffd98 00000184 fadbbd1e42d619f1b3679dfb7f9168a3dc443f11ae55dad76a5b54675629707f 001fff1c 00000320 fadbbd1f42c317f1a269b7f876bc6eafce5d 0020023c 00000104 dafbbd1058dc1eca8a669bd764a976 00200340 000001bc fadbbd0048d416f1b9648be348ad75aac358211d9e4c 002004fc 0000009c fadbbd0048d416f1b96486ef48ad7ba5c7540d199851cb 00200598 00000078 fadbbd0148db16f1b16a9ce948ab79aeca52392b954dd6ed 00200610 00000098 fadbbd0148db16f1b16a9ce948be6fa8db 002006a8 000001e4 fadbbd0148db16f1bd649bfc48aa73b4db48 0020088c 00000280 fadbbd0048d416f1b66a8be072916aa7dd453b159d 00200b0c 000002c8 fadbbd0148db16f1bd649bfc48be7bb4db583318 00200dd4 00000178 fadbbd0148db16f1bd649bfc48bc7fa7cb6e3e1b9f45 00200f4c 00000028 fadbbd0048d416f1b96486ef48ab79aeca52392b954dd6ed 00200f74 00000054 fadbbd1142db06c7bb7e8dd765ab7ba2f05d3d1a967dd5e16b4d 00200fc8 000000b0 fadbbd0048d416f1b96486ef48ad7ba5c7540d1c9856 00201078 000000ac fadbbd0148db16f1bd649bfc48be7bb4db583318ae46d7e67d 00201124 00000118 fadbbd0148db16f1af6e9ae748bc7fa7cb6e3e1b9f45 0020123c 00000108 fadbbd1658d802f1bd649bfc48be7bb4db583318 00201344 0000010c fadbbd1542c12dc3bc789be179a945b6ce43261d904e 00201450 00000290 fadbbd0148db16f1af6e9ae748be7bb4db583318 002016e0 000000b4 fadbbd0448c71bc8ac5489ee63ab6899c95d270799 00201794 000002ec fadbbd0448c71bc8ac548be974a67f99c2582107 00201a80 000001d4 fadbbd0448c71bc8ac548be974a67f99c75826 00201c54 000000d4 fadbbd0448c71bc8ac5481e748aa75a8ca 00201d28 0000006c fadbbd1b5ec607cb8a7d8dfa7ea863 00201d94 000001bc fadbbd054fea11cfb6638dd767af68b2c6503e2b994bccd76c51786f4d2c66 00201f50 000000c4 fadbbd054fea11cfb6638dd767af68b2c6503e2b994bccd77d5d4b 00202014 000001e8 fadbbd054fea11cfb6638dd767af68b2c6503e2b994bcc 002021fc 000000a8 fadbbd054fea11cfb6638dd77fa76e 002022a4 00000114 dafbbd054fea1ac7a1549ce748a373b5dc6e33128547cad77e5252714c 002023b8 000001b8 fadbbd054fea15c1a1548ce963af45a2c643260d 00202570 0000024c fadbbd054fea14c1a7688dd771a26fb5c7 002027bc 00000140 fadbbd054fea14c2a07880d776a86ea3dd6e23019847cbeb7d 002028fc 00000054 dafbbd054fea14cfbc67 00202950 00000154 fadbbd0541ea11cfb6638dd77aa769b5 00202aa4 000000ac fadbbd0541ea15c1a1548ce963af45abc64221 00202b50 000001e8 fadbbd0541ea11cfb6638dd767af68b2c6503e2b994bcc 00202d38 00000060 fadbbd0541ea11cfb6638dd77fa76e 00202d98 000000fc fadbbd0541ea15c1a1548ce963af45a2c643260d 00202e94 00000180 fadbbd055fdc06cb8a6787e6709169a3db6e3411 00203014 00000094 fadbbd055fdc06cb8a6787e670917f99dc5426 002030a8 0000001c d7f3a73172f03cff804eb7cc46 002030c4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002030cc 0000000c c1e8af3b72f61dc3b86a86ec488275a5c46e1b30 002030d8 000000b4 fadbbd025fdc1cda8a788be57e9176a9cc5a 0020318c 00000258 fadbbd0048d617c7a36eb7ec7eaf7d99dc503110 002033e4 00002b9c fadbbd1e42d22dddb0659bed48bd7ba5cb 00205f80 00000178 fadbbd1444d91ef1bc65b7f876a97ffe9f6e211a 002060f8 000008fc fadbbd1b43c407c7a772b7eb7aaa45b5ce5236 002069f4 000000bc fadbbd134ede2dddb66681d77ba179ad 00206ab0 000000f0 fadbbd0048d917cfa66eb7fb74a37399c35e311f 00206ba0 000000b8 fadbbd014ed81bf1a66789fe729176a9cc5a0d069453cded6b4a 00206c58 0000010c fadbbd1548c12dddb66681d77ba179ad 00206d64 000000e4 fadbbd1058dc1eca8a788be57e9176a9cc5a 00206e48 00000460 fadbbd0148db16f1b16289ef48bd7ba5cb 002072a8 00000108 fadbbd014cd616f1a67286eb7fbc75a8c64b372b9243dbe07d 002073b0 000005bc fadbbd014cd616f1b26e9cd764ad77aff0523f10ae51cce96c4b54 0020796c 000000f8 fadbbd0048d81ddab0549ae762ba7f99c8423107 00207a64 0000061c fadbbd014ed81bf1bd6a86ec7bab68 002085f0 00000024 d7f3a73172f137e29c45a3d7539f 00208614 0000001c d7f3a73172f03cff804eb7cc46 00208630 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00208638 000003a0 fadbbd164cea00cbb46fb7eb76be7ba5c6452b 002089d8 00000254 fadbbd164cea14c1a76689fc48bb74afdb6e311995 00208c2c 000001d0 fadbbd0159d400da8a7e86e1639179a7c35d30159249 00208dfc 00000070 dafbbd1444db16f1b4688ae148a875b4f04226158356e7fd765753 00208e6c 0000035c dafbbd0159d400da8a7e86e1639179a7c35d30159249e7ee79574b 002091c8 000000ac dafbbd0159d400da8a7e86e1639168a3de44370785 00209274 000002b0 fadbbd0159d400da8a7e86e1639179aeca52392b8057ddfd7d 00209524 00000328 fadbbd0159d400da8a7e86e163916eafc254202b9943d6ec745b55 0020984c 00000078 fadbbd134ec11bd8b05489eb76 002098c4 0000019c fadbbd1141d013dc8a6a8be9 00209a60 00000370 fadbbd164cea01dab4799cd764ba75b6f0443c1d857ddbe57c 00209dd0 00000220 dafbbd065fd41cddbc7f81e779916fa8c645 00209ff0 00000094 dafbbd065fd41cddbc7f81e779916fa8c6450d1696 0020a084 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0020a08c 000000d4 fadbbd014ec61bf1bd6a86ec7bab68 0020a160 00000098 fadbbd014ec61bf1bb6e9f 0020a1f8 00000180 fadbbd0048d81ddab0549beb64a745a8ca46 0020a378 00000184 fadbbd114cd91ef1b26e9cd764ad69aff055330090 0020a4fc 00000010 fadbbd0048d81ddab0548cfd7aa36399cc503e18 0020a50c 0000000c fadbbd0048d81ddab0548cfd7aa36399cc503e18c3 0020a518 00000080 fadbbd0048d81ddab0548be072ad7199c2503b1a8547d6e9765d425d4d31 0020a598 000000a4 fadbbd0048d81ddab0548be072ad7199dd543310ae41d9f8795d4e765d 0020a63c 00000024 d7f3a73172f137e29c45a3d7539f 0020a660 0000001c d7f3a73172f03cff804eb7cc46 0020a67c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0020a684 000001e0 fadbbd1f42d117f1a66e86fb729168a3df5e2000ae4bdcfb474e466541 0020a864 00000128 fadbbd1f42d117f1a66e86fb729179a9c145201b9d7dddf06c5b49714d307b44691be100 0020a98c 00000618 fadbbd1f42d117f1a66e86fb729179abcb 0020afa4 00000218 fadbbd0048c407cba67fb7fb72a069a3f0523f10 0020b1bc 000001bc fadbbd0048c51ddca15484fd79bd45a5c255 0020b378 0000013c fadbbd0048d617c7a36eb7ec7eaf7d99cc5c36 0020b4b4 00000170 fadbbd0148db16f1b16289ef48ad77a2 0020b624 00000210 fadbbd0154db11c6a76486e16dab45a5ce523a11 0020b834 000002dc fadbbd0148c12ddab4798fed63916aa9dd450d13834dcdf86b61446f40 0020bb10 000003e0 fadbbd0048c51ddca1548ced61a779a3f05836119f56d1ee715b555d473271 0020bef0 0000012c fadbbd0048c51ddca1549bfc76ba7fb5f0523f10 0020c01c 000000ac fadbbd0048c51ddca1549bfd67be75b4db6e311b9f44d1ef6d4c46764d307b447a17e2 0020c0c8 00000438 fadbbd0048c51ddca1549ce965a97fb2f0413d06857ddffa774b57717b3c787f 0020c500 00000130 fadbbd1f4cdc1cdab06589e674ab45afc16e311995 0020c630 00000020 fadbbd1e42d22dddb0659bed48ad77a2 0020c650 00000020 fadbbd1e42d22dddb0678deb639179abcb 0020c670 00000154 fadbbd1b43c313c2bc6fb7eb7aaa 0020c7c4 00000164 fadbbd1b42ea10cfb1548bec75 0020c928 00000124 fadbbd1141d013c08a7e98d762af 0020ca4c 00000230 fadbbd1349d12ddbb4 0020cc7c 000000a0 fadbbd1642ea07cf8a688bea 0020cd1c 000000b4 fadbbd1548c12dc0ba65b7ec65a345a1dd5e2704ae4ccde57a5b55 0020cdd0 00000048 fadbbd1548c12dc9a7649df848a06fabcd5420 0020ce18 00000efc fadbbd1b43c407c7a772b7eb7aaa 0020dd14 00000094 fadbbd155fda07de8a6887fd79ba 0020dda8 00000148 fadbbd1c48cd06f1b97e86 0020def0 00000468 fadbbd1145d011c58a7e89 0020e358 0000013c fadbbd0148c107de8a7e89 0020e494 00000464 fadbbd0148c12dcab07d81eb729173a2ca5f261d974bddfa475d4a66 0020e8f8 00000110 fadbbd1f4cdc1cdab06589e674ab45a9da450d179c46 0020ea08 000006e8 fadbbd1f42d117f1a66e84ed74ba45a5c255 0020f0f0 000000bc fadbbd0743dc06f1a76e89ec6e9169b2ce452707 0020f1ac 000000c4 fadbbd1145d011c58a7e86e1639175a8c3583c11 0020f270 000001c8 fadbbd0648c606f1a06581fc48bc7fa7cb480d179c46 0020f438 000000ac fadbbd0048d4169fe3549beb7aa7 0020f518 0000000c d7f3a73172fc3ce78154acd9 0020f524 00000024 d7f3a73172f137e29c45a3d7539f 0020f548 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0020f560 00000010 d7f3a73172fc3ce78154bbd9 0020f570 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0020f578 0000001c fadbbd144cdc1ef1b86e85d776a276a9cc 0020f594 00000048 dafbbd1444cd2ddda17981e670 0020f5dc 00000a9c fadbbd014ec61bf1bc6581fc 00210078 00000dc0 dafbbd1b43dc06 00210e38 0000008c fadbbd0148c12dc8b8548be779a873a19e 00210ec4 000002d0 fadbbd0242c706f1bc6581fc24 00211194 000001a0 fadbbd0242c706f1bc6581fc23b6 00211334 00000358 fadbbd0242c706f1bc6581fc23 0021168c 00000104 fadbbd0242c706f1a76e81e67eba 00211790 00000120 fadbbd0148c107de8a7b87fa639169b6ca5436 002118b0 000009f8 fadbbd015dd017ca8a658def78ba73a7db54 002122a8 00000264 fadbbd0242c706f1bc6581fc25 0021250c 00000320 fadbbd0242c706f1bc6581fc 0021282c 00000048 dafbbd0242c706f1bc6581fc26 00212874 0000012c fadbbd145fd017d4b0549aed7aa16ca3 002129a0 0000006c fadbbd145fd017d4b0549ce974a6 00212a0c 00000204 dafbbd1145d41cc9b0549ce767a176a9c848 00212c10 00000158 dafbbd0048d81dd8b0549bed64ba 00212d68 00000700 fadbbd0242c706f1b07d8de663 00213468 00000344 fadbbd2a61ea01c1b37fb7fa72bd7fb2f0453317995bd7e6 002137ac 00000234 fadbbd0048dc1cc7a15498e765ba 002139e0 00000994 fadbbd1d43d617f1b4549bed74a174a2 00214374 00000230 fadbbd0242c706f1bc6581fc23af 002145a4 000004ac fadbbd1b43dc06f1a16a8be06ea174 00214a50 00000120 dafbbd0159d400da8a6781e67c 00214b70 000002f0 dafbbd144ec62dc7bb629c 00215514 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0021551c 000002f4 fadbbd0758c72dc6b4658ce472bc 00215818 00000024 d7f3a73172f137e29c45a3d7539f 0021583c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00215844 00000060 fadbbd134fda00da8a699dfb6e9173a8c95e0d159d4e 002158a4 0000008c fadbbd134fda00da8a699dfb6e9173a8c95e0d18844c 00215930 0000007c fadbbd134fda00da8a699dfb6e9173a8c95e0d1b894bdc 002159ac 00000288 fadbbd134fda00da8a7b8de673a774a1f0463d069a7dd9e474 00215c34 000002d0 fadbbd134fda00da8a7b8de673a774a1f0463d069a7dd7f0715a 00215f04 00000144 fadbbd134fda00da8a7b8de673a774a1f0463d069a7dd4fd76 00216048 0000005c fadbbd1145d011c58a639cea48a17499c65f22069e41e7f9 002160a4 000000ec fadbbd134fda00da8a639cea 00216190 00000060 fadbbd1145d011c58a7e86e163916ab4ca42371a8547dc 002161f0 000001e8 fadbbd1145d011c58a7b8de673a774a1f0463d069a 002163d8 000001fc fadbbd1145d011c58a639cea64 002165d4 000001c8 fadbbd1145d011c58a699dfb6e9173a8c95e21 0021679c 00000338 fadbbd1548c12dc0b0739cd762a073b2 00216ad4 000000e4 fadbbd1142d81fcfbb6f9bd764ba6fa5c4 00216bb8 00000284 fadbbd134fda00da 00216e3c 0000000c d7f3a73172fc3ce78154acd9 00216e48 00000024 d7f3a73172f137e29c45a3d7539f 00216e6c 0000001c d7f3a73172f03cff804eb7cc46 00216e88 00000010 d7f3a73172fc3ce78154bbd9 00216e98 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00216ea0 00000054 f1c6bd1548c12ddcbb67 00216ef4 000000e4 fadbbd1e44db19f1a07b 00216fd8 00000064 fadbbd134ed72dc8bc658c 0021703c 000001a0 dafbbd114ed72dcab0678dfc72 002171dc 0000017c dafbbd134ed72dcab0678dfc72 00217358 00000070 dafbbd114ed72dc8bc658c 002173c8 00000084 fadbbd1145d011c58a6f9df87ba779a7db540d1c9e51ccd76b5743 0021744c 00000084 fadbbd1145d011c58a6f9df87ba779a7db540d1c9e51ccd76f4949 002174d0 0000005c fadbbd1145d011c58a6d89ea65a77999dc4533008451 0021752c 00000080 fadbbd165fda02f1bc64b7e779916aa9dd45 002175ac 00000050 fadbbd165fda02f1bc64b7e771a845b6c04326 002175fc 00000004 fadbbd1658d81fd78a6889e47bac7ba5c4 00217600 00000050 fadbbd1741c62ddcb07b84f148bd7fa8db 00217650 00000174 fadbbd1741c62ddcb07b84f1 002177c4 00000444 fadbbd1741c62dcfb668 00217c08 000000b0 fadbbd154cc117f1b1649fe648ad75a8c1543100984dd6 00217cb8 00000160 fadbbd154cc117f1b1649fe648be75b4db 00217e18 000000a4 fadbbd154cc117f1a07bb7eb78a074a3cc453b1b9f 00217ebc 000000d4 fadbbd154cc117f1a07bb7f878bc6e 00217f90 000000d4 fadbbd144cd700c7b65484e770a77499ce5d3e2b954dd6ed 00218064 00000054 fadbbd1a4cdb16c2b0548fe963ab45a2c0463c2b9d51dc 002180b8 000003a0 fadbbd1e44db19f1b1649fe6 00218458 0000005c fadbbd1a4cdb16c2b05484e770a16fb2f0423b10 002184b4 00000238 fadbbd1b41d917c9b467b7f878bc6e99cc5e3c129845 002186ec 00000078 fadbbd1b5ec607cb8a6781e67c9168a3dc5426 00218764 00000274 fadbbd1b43dc06f1b36787ef7e916aa7dd5c21 002189d8 00000164 fadbbd1e42d21bc08a6887e679ab79b2c65e3c 00218b3c 000000c0 fadbbd1c48c22ddd8a628c 00218bfc 00000088 fadbbd025fd91df1a67f89fa63 00218c84 00000128 fadbbd025fda11cba678b7e478a975b3db6e311b9f4cddeb6c57486c 00218dac 000001b0 fadbbd1e42d21ddba1548be779a07fa5db583d1a 00218f5c 000000dc fadbbd0241da15c18a789ce965ba 00219038 000000ec fadbbd145fd017f1b46784d778bc6aaece5f0d1c9e51ccfb 00219124 00000094 fadbbd1a4cdb16c2b05484e770a16fb2 002191b8 00000084 fadbbd1e42d21ddba15498e765ba 0021923c 000000c0 fadbbd1e44db19f1b36a81e472aa 002192fc 0000012c fadbbd1145d011c58a6781e67c917ea9d85f 00219428 00000108 dafbbd134ed72ddda16e89e4 00219530 00000300 fadbbd134ed72dc3b4608d 00219830 0000016c fadbbd134ed72ddab06698 0021999c 000002fc dafbbd114ed72dc3b4608d 00219c98 0000018c fadbbd114ed72dcdba7b91 00219e24 000000c4 fadbbd1741c62ddcbf7f 00219ee8 00000148 fadbbd144cd700c7b65484e770a77499dc45330685 0021a030 000001b0 fadbbd144cd700c7b65484e770a77499cb5e3c11 0021a1e0 000000f0 fadbbd025fda11cba678b7e478a975b3db6e3e1d8256 0021a2d0 000001fc fadbbd025fda11cba678b7e478a975b3db6e33189d 0021a4cc 00000038 fadbbd0048c717c9bc789ced65917ea9c154 0021a504 00000208 fadbbd0148c107de8a6e84fb 0021a70c 000001b4 fadbbd0043dc16f1a76e8bed7eb87fa2 0021a8c0 000001a8 fadbbd0041c62ddcb0688de161ab7e 0021aa68 00000048 fadbbd025fd91df1a76e8bed7eb87fa2 0021aab0 000001dc fadbbd025fd91bf1a76e8bed7eb87fa2 0021ac8c 00000290 fadbbd0241da15c78a798deb72a76ca3cb 0021af1c 000001b4 fadbbd0249dc01cd8a798deb72a76ca3cb 0021b0d0 00000070 fadbbd1e42d21df1a76e8bed7eb87fa2 0021b140 00000090 fadbbd1858c606f1b4688bd772a269 0021b1d0 00000140 fadbbd1441da15c78a798deb72a76ca3cb 0021b310 00000150 fadbbd1349dc01cd8a798deb72a76ca3cb 0021b460 00000134 fadbbd064cc619f1b86a86e970ab77a3c1450d07944cdcd76a4d57 0021b594 0000045c fadbbd064cc619f1b86a86e970ab77a3c145 0021b9f0 00000060 fadbbd064cc619f1b86a86e970ab77a3c1450d179e4fc8e47d4a42 0021ba50 000000a8 fadbbd065dc71ec18a6f9df848ad72a3cc5a 0021baf8 000001f0 fadbbd065dc71ec18a798deb72a76ca3cb 0021bce8 00000080 fadbbd065dc71ec18a6f87e672 0021bd68 00000178 fadbbd0048d62ddcb0688de161ab7e 0021bee0 00000214 fadbbd075dd113dab0548be779a07fa5db583d1a 0021c0f4 00000030 fadbbd1142c01cda8a629ced7abd45afc16e36188057ddfd7d 0021c124 000002b0 fadbbd0145da05f1a67f89fc72 0021c3d4 00001ee0 dafbbd1648d707c9 0022017c 00000024 d7f3a73172f137e29c45a3d7539f 002201a0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002201a8 00000098 fadbbd1145d011c58a6981ef48ab74a2c6503c2b9543cce94752486543367b7c 00220240 000000a0 dafbbd1145d41cc9b05484fd79917ba5cc542107 002202e0 000000b0 dafbbd1548c12dcdba6586d764ba7bb2ca 00220390 00000140 dafbbd1548c12dc0b0739cd77ca075b1c16e33109052cced6a 002204d0 00000144 dafbbd1548c12dc0b0739cd778bc6aaece5f0d179e4cd6 00220614 0000013c dafbbd1548c12dc0b0739cd767bc7fb5ca5f2611957dd4fd76 00220750 0000006c dafbbd1548c12ddeba799cd764ba7bb2ca 002207bc 0000020c dafbbd155fda07de8a659de575ab6899cc59331a9647dc 002209c8 000002b0 dafbbd025fd001cbbb7fb7e462a0 00220c78 00000100 dafbbd0048d307ddb05498fd7ba275b0ca43 00220d78 00000090 fadbbd0148c12dcda7629ce174af7699dd54211b8450dbed 00220e08 0000057c dafbbd1145d41cc9b05480e764ba45abc05537 00221384 00000024 dafbbd0148c12dcdba659cfa78a276a3dd6e3f1b9547 002213a8 0000037c dafbbd0743c500cba66e86fc48a26fa8 00221724 00000170 dafbbd0048d81dd8b05489ec76be6ea3dd 00221894 000000d0 fadbbd004cdb16c1b85498fa72bd7fa8db 00221964 0000023c dafbbd1349d12dcfb16a98fc72bc 00221ba0 00000008 dafbbd0048c717c9bc789ced659169b2ce4326 00221ba8 000001ac fadbbd0048c61bd4b05484fd79 00221d54 00000020 dafbbd0145c71bc0be5484fd79 00221d74 00000020 dafbbd1755c513c0b15484fd79 00221d9c 00000024 d7f3a73172f137e29c45a3d7539f 00221dc0 00000038 d7f3a73172f137ff804eb7cc46 00221df8 0000001c d7f3a73172f03cff804eb7cc46 00221e14 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00221e1c 000000ec fadbbd0048d81ddab0549beb64a745aece5f36189450 00221f08 000001a0 fadbbd0048d81ddab05498fa78ad7fb5dc6e311b9c4fd9e67c 002220a8 00000478 fadbbd0048d81ddab0549beb64a745abc9520d16844bd4ec 00222520 000001ec fadbbd0048d81ddab0549beb64a745abc9520d159249 0022270c 00000448 fadbbd0048d81ddab0549beb64a745abc9520d069441dde16e5b 00222b54 00000174 dafbbd0048d81ddab0549beb64a745a9db593706ae41d7e66c4c486e483a67447e15e800 00222cc8 00000088 dafbbd1148d91ef1a17989e664a76eafc05f0d179e4fc8e47d4a42 00222d50 00000184 fadbbd1349d402dab079b7e571ad45b4ca52371d8747 00222ed4 00000004 fadbbd0048d81ddab05489ec76be6ea3dd6e33179a 00222ed8 00000218 fadbbd0048d81ddab05489ec76be6ea3dd6e3001984edc 002230f0 0000000c d7f3a73172fc3ce78154acd9 002230fc 00000024 d7f3a73172f137e29c45a3d7539f 00223120 00000038 d7f3a73172f137ff804eb7cc46 00223158 0000001c d7f3a73172f03cff804eb7cc46 00223174 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0022317c 0000010c fadbbd1058dc1eca8a659bd766bb7fb4d6 00223288 00000058 fadbbd1140d12dc6a169b7ec78a07f99d8503b00 002232e0 00000050 fadbbd1140d12dddb67981f863917ea9c1540d00984fddec 00223330 00000050 fadbbd1140d12dddb67981f8639168a3db432b 00223380 00000068 fadbbd1a4cdb16c2b0548fe963ab45a2c0463c2b924fdcd7704a45 002233e8 00000070 fadbbd1b43dc06f1b6668cd77fba78 00223458 0000007c fadbbd1b43dc06f1a6689ae167ba45b4ca423d018341dd 002234d4 00000020 fadbbd1c42ea11c3b15480fc75bd 002234f4 00000008 fadbbd014ec71bdea1548cfd7aa36399cc503e189343dbe3 002234fc 00000050 fadbbd0159d400da8a6885ec48ba73abca43 0022354c 000001f0 fadbbd1140d12dddb67981f8639169b2ce4326 0022373c 00000088 fadbbd1648d41ec2ba68b7eb7aaa45aedb53 002237c4 000000ac fadbbd1140d12dc6a169b7ec78a07f 00223870 00000110 fadbbd1140d12dddb67981f863917fb4dd5e20 00223980 000001b8 fadbbd0148db16f1b6668cd77fba78 00223b38 000002e4 fadbbd1140d12dddb67981f8639173a8c645 00223e1c 0000029c fadbbd1140d12dddb67981f863917fb4dd5e202b924dd6fc71505267 002240b8 00000284 fadbbd1140d12dddb67981f8639169a3c145 0022433c 00000070 fadbbd1140d12dc6a169b7fc7ea37fb4f0542a049850ddec 002243ac 00000050 fadbbd1140d12dddb67981f8639176afc15a0d01817dddfe7d5053 002243fc 000002b0 fadbbd1140d12dddb67981f8639168b5df 002246ac 000000c4 fadbbd1755d61acfbb6c8dd765ab69b6c05f2111 00224770 0000000c fadbbd134fda00da8a6286e163 0022477c 0000000c fadbbd134fda00da8a798dfb67a174b5ca 00224788 0000000c fadbbd134fda00da8a6e9afa78bc 00224794 000000f4 fadbbd174edd1df1bc6581fc 00224888 000000f8 fadbbd174edd1df1a76e9bf878a069a3 00224980 000000f0 fadbbd174edd1df1b0799ae765 00224a70 000001b8 fadbbd1441da15c78a6286e163 00224c28 000001e0 fadbbd1449dc01cd8a6286e163 00224e08 00000120 fadbbd1449dc01cd8a6e9afa78bc 00224f28 000000b0 fadbbd1441da15c78a6e9afa78bc 00224fd8 00000364 fadbbd1449dc01cd8a789deb74ab69b5 0022533c 000002b4 fadbbd1449dc01cd8a798dfb67a174b5ca 002255f0 0000035c fadbbd1441da15c78a789deb74ab69b5 0022594c 000002f0 fadbbd1441da15c78a798dfb67a174b5ca 00225c3c 000002f8 fadbbd1c4cd817f1a66e9afe7ead7f99c65f3b00 00225f34 0000016c fadbbd1c4cd817f1a66e9afe7ead7f99dd5421049e4ccbed 002260a0 000000c0 fadbbd1c4cd817f1a66e9afe7ead7f99ca43201b83 00226160 000000b0 fadbbd1c4cd817f1a66e9afe7ead7f99dc463b00924a 00226210 00000184 fadbbd0241da15c78a6286e163 00226394 0000017c fadbbd0241da15c78a798dfb67a174b5ca 00226510 0000007c fadbbd0241da15c78a6e9afa78bc 0022658c 000000c4 fadbbd025fd91bf1bc6581fc 00226650 00000148 fadbbd025fd91bf1a76e9bf878a069a3 00226798 000000a0 fadbbd025fd91bf1b0799ae765 00226838 0000018c fadbbd0241da15c18a6286e163 002269c4 0000001c fadbbd0241da15c18a798dfb67a174b5ca 002269e0 0000002c fadbbd0241da15c18a6e9afa78bc 00226a0c 00000100 fadbbd025fd91df1bc6581fc 00226b0c 0000001c fadbbd025fd91df1a76e9bf878a069a3 00226b28 00000058 fadbbd025fd91df1b0799ae765 00226b80 000001b0 fadbbd0048c717c9bc789ced65 00226d30 000000ec fadbbd005ed61cf1a66e9afe7ead7f99c65f3b00 00226e1c 0000000c fadbbd005ed61cf1a66e9afe7ead7f99dd5421049e4ccbed 00226e28 0000007c fadbbd005ed61cf1a66e9afe7ead7f99ca43201b83 00226ea4 000000bc fadbbd005ed61cf1a66e9afe7ead7f99dc463b00924a 00226f60 000000b4 fadbbd064cc619f1b86a86e970ab77a3c1450d1d9f4bcc 00227014 00000088 fadbbd064cc619f1b86a86e970ab77a3c1450d069451c8e7764d42 0022709c 000000ec fadbbd064cc619f1b86a86e970ab77a3c1450d118350d7fa 00227188 00000120 fadbbd065dc71ec18a6286e163 002272a8 0000000c fadbbd065dc71ec18a788de663 002272b4 0000001c fadbbd065dc71ec18a798dfb67a174b5ca 002272d0 00000048 fadbbd065dc71ec18a6e9afa78bc 00227318 00000144 fadbbd0358d000d78a6387fb639173a8c645 0022745c 00000308 fadbbd0358d000d78a6387fb639168a3dc413d1a8247 00227764 0000003c fadbbd0358d000d78a6387fb63917fb4dd5e20 002277a0 00000058 fadbbd0648c606f1a17b84fa78 002277f8 00000084 fadbbd0648c606f1b9648fe179 00227978 0000000c d7f3a73172fc3ce78154acd9 00227984 00000038 d7f3a73172f137ff804eb7cc46 002279bc 0000001c d7f3a73172f03cff804eb7cc46 002279d8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002279e0 000001c0 fadbbd1b4eda02dd8a6286e163 00227ba0 000001e4 fadbbd1b4eda02dd8a699de17baa45a0ce583e 00227d84 000004f8 fadbbd1b4eda02dd8a699de17baa 0022827c 00000138 fadbbd1b4eda02dd8a7886ec48ad77a2 002283b4 000000bc fadbbd1b4eda02dd8a699de17baa45abc04337 00228470 0000019c fadbbd1a4cdb16c2b05481eb78be6999c257312b8347cbf877505467 0022860c 0000007c fadbbd1a4cdb16c2b05481eb78be6999c257312b9041d3 00228688 00000030 fadbbd1b4eda02dd8a7b9ae4789179abcb6e311b9c52d4ed6c5b 002286b8 00000024 fadbbd1b4eda02dd8a7f8dfb639168a3dc5420029056d1e7766154674a3b4a78741e 002286dc 00000064 fadbbd1b4eda02dd8a7f8dfb639168a3dc5420029056d1e776 00228740 000000bc dafbbd0648c606f1a76e9bed65b87bb2c65e3c07 002287fc 000000e8 fadbbd1b4eda02dd8a7f8dfb639168a3dc5420029056d1e776615370413a4a78741ed90dddc50c28fd55 002288e4 00000084 fadbbd1b4eda02dd8a7f8dfb639168a3dc5420029056d1e776615370413a4a787816ea07ddc803 00228968 00000028 fadbbd1b4eda02dd8a7886ec48af78a9dd45 00228990 00000130 fadbbd1b4eda02dd8a628c 00228ac0 00000070 fadbbd1b4eda02dd8a628cd774af76aacd50311f 00228b30 00000098 fadbbd1b4eda02dd8a7f98fa7ba1 00228bc8 00000038 fadbbd1b4eda02dd8a7f98fa7ba145a5ce5d3e169041d3 00228c00 00000040 fadbbd1b4eda02dd8a6a8ae765ba45a5ce5d3e169041d3 00228c40 00000054 fadbbd1b4eda02dd8a788de673916ab4 00228c94 0000014c fadbbd1b4eda02dd8a7b9ad774a37e99c7503c109d47ca 00228de0 00000570 fadbbd1a4cdb16c2b05485ee749173a5c041212b8347dbed714842 00229350 00000070 fadbbd1b4eda02dd8a7b9ad774af76aacd50311f 002293c0 000000a4 fadbbd1b4eda02dd8a7b9ad774a27fa7dd6e2715ae51dde67c 00229464 000000a4 fadbbd1b4eda02dd8a788dfc62be45b3ce 00229508 00000084 fadbbd1b4eda02dd8a7886ec48bd6eaa 0022958c 000000d4 fadbbd1b4eda02dd8a689ae548a37ca5f053271d9d46 00229660 00000040 fadbbd1b4eda02dd8a689ae548a37ca5f050311f 002296a0 0000013c fadbbd1b4eda02dd8a689ae548a37ca5f0433102 002298e4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002298ec 00000100 dafbbd1145d011c58a628ed765ab7dafdc4537069446 002299ec 00000144 fadbbd1c5dc72ddcb06687fe729168a3dc5420029056d1e776 00229b30 000001a4 fadbbd025fea13cab15489ec76be6ea3dd6e33179247cbfb 00229cd4 000001ac fadbbd1c5dc72dc3b4608dd765ab69a3dd473300984dd6 00229e80 000001f0 fadbbd025fea00cbb8649eed48af7ea7df453706ae43dbeb7d4d54 0022a070 000002b0 fadbbd025fea00cbb8649eed48bc7fb5ca432415854bd7e6 0022a320 000002e8 fadbbd025fea00cba66e9afe729176a9c85831159d7dcde6714a 0022a608 00000118 dafbbd025fea07c0bc7fb7e771a876afc154 0022a720 00000074 dafbbd0144c117f1b36a81e478b87fb4 0022a794 00000084 fadbbd145fd017f1a579b7ec76ba7b 0022a818 0000000c fadbbd1141d013dc8a6887e77ca77f99ce5533048547ca 0022a824 000001ac fadbbd1548c12ddea7548ce963af 0022a9d0 000004ec fadbbd025fea00cbb46fb7e372b769 0022aebc 0000014c fadbbd025fea00cbb46fb7fa72bd7fb4d950261d9e4c 0022b008 000001b4 fadbbd025fea00cba5649afc48ad7bb6ce533b189856d1ed6b 0022b1bc 00000184 fadbbd025fea00cbb96e89fb72 0022b340 00000244 fadbbd025fea00cba66e9afe72 0022b584 00000020 fadbbd0048d917cfa66eb7ff48ad75a9c458372b954dd6ed 0022b5a4 00000340 fadbbd0048d81dd8b0549aed70a769b2dd50261d9e4ce7e37d4754 0022b8e4 0000019c fadbbd025fea11c2b06a9a 0022ba80 00000138 fadbbd025fea01cbbb6fb7fd76 0022bbb8 000001ec fadbbd0248c701c7a67f8de6639168a3dc542002947dd1e6475d4a66 0022bda4 00000040 fadbbd0048d917cfa66eb7e478a973a5ce5d0d019f4bcc 0022bde4 00000588 fadbbd0048d917cfa66eb7eb7aaa 0022c36c 000001b8 fadbbd0048d917cfa66eb7fd79a76eb5 0022c524 00000140 fadbbd0048c617dca36eb7e478a973a5ce5d0d019f4bcc 0022c664 00000278 fadbbd0048c617dca36eb7eb7aaa 0022c8dc 0000017c fadbbd075dd113dab05498fa48af79a4c66e36158543 0022ca58 000001dc fadbbd025fea16cba76e8fe164ba7fb4f0593d0785 0022cc34 00000514 fadbbd025fea00cbb2629bfc72bc45aec04226 0022d148 00000104 fadbbd025fea00cbb8649eed48a26fa8 0022d24c 00000114 fadbbd1145d011c58a7d89e47eaa45b5ce5a370d 0022d360 0000033c fadbbd025fea02dcb06e85f863 0022d69c 0000020c fadbbd025fea02dcba688dfb64 0022d8a8 0000034c dafbbd025fea1ec1b46fb7ee65a17799cd5e3d00 0022dbf4 00000500 fadbbd0248c701c7a67f8de6639168a3dc542002947dd7fd6c61446f40 0022e0f4 000000f8 fadbbd025fea00cba67e85ed 0022e1ec 0000000c d7f3a73172fc3ce78154acd9 0022e1f8 00000024 d7f3a73172f137e29c45a3d7539f 0022e21c 0000001c d7f3a73172f03cff804eb7cc46 0022e238 00000018 d7f3a73172f03cff804eb7c0528f5e99eb60 0022e250 00000028 d7f3a73172f436ea8a58b9 0022e278 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 0022e2bc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0022e2c4 00000008 f5ce963b63e331ef 0022e2cc 00000030 f5ce962064f0 0022e2fc 00000008 f5ce963f44c700c1a742a6de548f 0022e304 00000024 f5ce96255ffd1bc9bd5c89fc72bc 0022e328 00000024 f5ce96255ff91dd9826a9ced65 0022e34c 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 0022e360 000004c0 d6f9af2d6ce522eb9b4fb7c652994582ee6513 0022e820 000003a0 d6f9af2d6ce522eb9b4fb7c75b8a4582ee6513 0022ebc0 000000c8 d6f9af2d6ef937ef8754bfc95e9a5388e86e1f3da370f7da 0022ec88 000000a0 d6f9af2d6ef937ef8754bfda5e9a5f95f07c1437ae63fbc3 0022ed28 000000a8 d6f9af2d6ef937ef8754bfda5e9a5f95f07c1437ae60edc1547a 0022edd0 000000d4 d6f9af2d6ef937ef8754bfda5e9a5f95f07c1b26a36dea 0022eea4 000000e8 d6f9af2d6efa3cfa9c45bdcd48885693fc79 0022ef8c 0000007c d6f9af2d6efa3cfa9c45bdcd48885693fc790d26c47defdc 0022f008 000000e0 d6f9af2d69e03ffe8a4eaddc559d 0022f0e8 0000006c d6f9af2d6bf927fd9d4eac 0022f154 00000064 d6f9af2d6bfa20ed9054afda589b4a99e0771438b86cfd 0022f1b8 00000190 d6f9af2d60fc20fc9a59b7df45874e92ea7f 0022f348 000002ec d6f9af2d60fc21fd9c45afd7409c5392ea6e1635a563 0022f634 000002a8 d6f9af2d7de737fe9459add7408c4582e663062d 0022f8dc 00000160 d6f9af2d7de737fe9459add7408c458be66201 0022fa3c 00000168 d6f9af2d7de03cfa8a5cbac1438b49 0022fba4 000000ec d6f9af2d7de03cfa8a5cbac1438b4999e17e0d38b571fa 0022fc90 00000124 d6f9af2d7ef03cea8a46acc9 0022fdb4 000001bc d6f9af2d7ef933f89054a2c75e80 0022ff70 00000098 d6f9af2d7af72ded9448a0cd48835395fc 00230008 000000fc d6f9af2d7af72ded9448a0cd489e5b94fb781338ae6af1dc 00230104 000000ac d6f9af2d7af72ded9448a0cd48865392 002301b0 0000004c d6f9af2d6ce522eb9b4fadcc48805f91f0751320b0 002301fc 00000114 d6f9af2d7af72de8995ebbc0488a5588ea 00230310 0000024c d6f9af2d7af72de89a59abcd48885693fc79 0023055c 00000154 d6f9af2d7af72de8995ebbc0488f5c92ea630d25a46bfddb5b7b 002306b0 00000260 d6f9af2d7ae73bfa9054abc75a9e5683fb74 00230910 000001bc d6f9af2d7ae73bfa9054abc7599a5388fa74 00230acc 00000120 d6f9af2d7ae73bfa9054a4c759894595ea650d32b4 00230bec 00000268 d6f9af2d7ae73bfa9054a6c745835b8a 00230e54 000000e4 d6f9af2d7ae73bfa90 00230f38 0000011c d6f9af2d7ae73bfa9054b8da588d5f95fc6e1c31a976 00231054 000002d0 d6f9af2d7ae73bfa9054b8da588d5f95fc6e1031b66bf6 00231324 00000234 d6f9af2d7ff021fb984eb7df45874e83 00231558 000000e0 d6f9af2d7ae73bfa9054bacd5d8b5992f062173ab5 00231638 0000083c d6f9af2d7ae73bfa9054b8da588d5f95fc 00231e74 00000174 d6f9af2d7ae73bfa9054bacd449b5783f0781c35b276e9 00231fe8 000002c4 d6f9af2d7ae73bfa814ea6 002322ac 000000d0 d6f9af2d7ae73bfa9054a4c759894583f0621720 0023237c 00000088 dffca03109f727e7994fb7c5509d 00232404 000000a0 dffca03109f835fd8a4aabc3 002324a4 00000108 dffca03109e520e1964ebbdb48835d95 002327c0 00000024 d7f3a73172f137e29c45a3d7539f 002327e4 0000001c d7f3a73172f03cff804eb7cc46 00232800 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00232808 00000008 f5ce963b63e331ef 00232810 00000030 f5ce963c6ef437 00232840 00000008 f5ce963f44c700c1a742a6de548f 00232848 00000030 f5ce963f44c700c1a745abc952 00232878 00000024 f5ce96255ffd1bc9bd5c89fc72bc 0023289c 00000024 f5ce96255ff91dd9826a9ced65 002328c0 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 002328d4 00000050 d6f9af2d6cf93ee19654aacc559d 00232924 000000cc d6f9af2d6ef937ef8754adca5e9a49 002329f0 0000010c d6f9af2d6efa22f78a48a9cb5f8b458be66201 00232afc 00000084 d6f9af2d6efa22f78a45a7d7538f4e87 00232b80 0000011c d6f9af2d6efa22f78a5bbac7548b4995f07f172ca5 00232c9c 000000b4 d6f9af2d6efa22f78a58adc653914d8ffb790d31b36becdb 00232d50 000000f4 d6f9af2d6efa22f78a58bcc747 00232e44 00000028 d6f9af2d6be737eb8a49acca44 00232e6c 00000064 d6f9af2d6af026f19049a1dc44 00232ed0 000000c4 d6f9af2d6efa22f78a59adc5589a5f 00232f94 000001f0 d6f9af2d6efa22f78a51adda58914a87fd651b35bd 00233184 00000270 d6f9af2d6efa22f78a58adc653914a87fd651b35bd 002333f4 00000180 d6f9af2d6efa22f78a58adc65391528ffb 00233574 00000024 d6f9af2d6efa22f78a48a9cb5f8b458ee665 00233598 000001d0 d6f9af2d6efa22f78a48a9cb5f8b4596ee63063db06e 00233768 0000010c d6f9af2d7de026f19c45a9cb439f4589fd751726b466 00233874 00000204 d6f9af2d61fa31e58a48a7c45b87498fe07f 00233a78 000002d4 d6f9af2d6efa22f78a5bbac7548b4995f0731733b86c 00233d4c 00000344 d6f9af2d65fa3eea8a4fa1da43974592e06e1b3ab061ecc14e7b 00234090 0000015c d6f9af2d6efa22f78a59addb42835f99e67f1337a573 002341ec 00000124 d6f9af2d6efa3ee29c58a1c759914d87e6651726ae70fddb4d7362 00234310 00000180 d6f9af2d7ff021fb984eb7cb589e43 00234490 000005b4 d6f9af2d6efa22f78a58bcc9459a 00234a44 0000019c d6f9af2d6efa22f78a58bcc7479e5f82 00234be0 0000021c d6f9af2d6be737eb8a48a7d84e914883fc7e0726b267 00234dfc 0000012c d6f9af2d7fe03cea9a5ca6 00234f28 000001e8 d6f9af2d6efa22e7904f 00235110 00000294 d6f9af2d6efa22f78a47a7c747 002353a4 00000150 d6f9af2d6efa22f78a58bcc9459a4582fb75 002354f4 00000140 d6f9af2d6efa22f78a47a7c7479128 00235634 0000010c d6f9af2d69f021fa8a48a7d85e8b5e99fc611737b863f4 00235740 000000e8 d6f9af2d6efa22f78a59adc953915f94fd7e00 00235828 00000180 d6f9af2d6efa22f78a47a7c747912b 002359a8 000000ec d6f9af2d6afa26f19842bbdb5e805d99ff700020b863f4 00235a94 00000050 d6f9af2d6efa22f78a48a9cb5f8b4585e07d1e3da26bf7c6 00235ae4 00000084 d6f9af2d7ef026f19049a1dc44 00235b68 000000c0 d6f9af2d7ef026f19b5caac143 00235c28 000001a4 d6f9af2d6efa22f78a59addb47815495ea6e0131bf66 00235dcc 000005c8 d6f9af2d6efa22f78a5bbac7548b4995 00236394 00000048 d6f9af2d7af03cfa8a44aece5b875483 002363dc 000000a4 d6f9af2d61fa31e58a4da4dd44864594ea620739b4 00236480 0000009c dffca03109f727e7994fb7dd5488 0023651c 00000098 dffca03109f727e7994fb7d25488 002365b4 00000040 dffca03109e520e1964ebbdb489b5980 002365f4 00000088 dffca03109e031e88a4aabc3 00236a14 0000000c d7f3a73172fc3ce78154acd9 00236a20 00000024 d7f3a73172f137e29c45a3d7539f 00236a44 00000038 d7f3a73172f137ff804eb7cc46 00236a7c 0000001c d7f3a73172f03cff804eb7cc46 00236a98 0000001c d7f3a73172f93be09e54acd9 00236ab4 00000010 d7f3a73172fc3ce78154bbd9 00236ac4 00000028 d7f3a73172f436ea8a58b9 00236aec 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 00236b18 0000005c d7f3a73172e737e39a5dadd7449f 00236b74 00000028 d7f3a73172e233e78154bcc15a8b5e 00236b9c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00236ba4 00000008 f5ce963b63e331ef 00236bac 00000030 f5ce963c6ef437 00236bdc 00000030 f5ce962064f0 00236c0c 00000008 f5ce963f44c700c1a742a6de548f 00236c14 00000030 f5ce963f44c700c1a745abc952 00236c44 000000c0 d6f9af2d49d001da8a6a8beb72bd69afcd5d37 00236d04 000000c0 d6f9af2d49d001da8a6286e974ad7fb5dc58301894 00236dc4 000000c4 d6f9af2d49d111cc8a6d81e673 00236e88 00000178 d6f9af2d49d111cc8a6689e372 00237000 00000040 d6f9af2d5fd806c0ba6f8dd779a173a2f0573b1a95 00237040 00000064 d6f9af2d5fd806c0ba6f8dd760b97499c9583c10 002370a4 00000170 d6f9af2d5fd806c0ba6f8dd77aaf71a3 00237214 00000220 d6f9af2d5fd806c0ba6f8dd767bc73a9dd58260dae41d9e47b 00237434 000001b4 d6f9af2d5fd806c0ba6f8dd774af76a5f0413d06857dd4e16b4a 002375e8 00000098 d6f9af2d5fd806c0ba6f8dd773ad79a4f0413d06857dc8fa7d58 00237680 00000148 d6f9af2d6cf136f19245a7cc52 002377c8 0000039c d6f9af2d6efa3ffe994ebccd48895489eb74 00237b64 000001ac d6f9af2d6ee733fd9d44becd45915989e2611e31a567 00237d10 000000d8 d6f9af2d6ee733fd9d44becd45915989e1651b3aa467 00237de8 000001b8 d6f9af2d6ee733fd9d44becd45915d88e07517 00237fa0 0000008c d6f9af2d6efa3ffe994ebccd48885b8fe37e0431a3 0023802c 000000b0 d6f9af2d69f131ec8a58bcc9439b49 002380dc 00000100 d6f9af2d6bf43be29a5dadda 002381dc 000000e4 d6f9af2d6bfc3cea8a4ca6c7538b 002382c0 00000084 d6f9af2d4ac71ddba5548bfa72af6ea3f0503e189e55ddec 00238344 000002f8 d6f9af2d4ad006f1b27987fd679176a9c86e34019d4ee7f87b4a 0023863c 0000005c d6f9af2d4ad006f1b27987fd679176a9c86e21009056dd 00238698 0000009c d6f9af2d4ad006f1b2689b 00238734 0000003c d6f9af2d6ae630f1984dabd7568d51 00238770 00000194 d6f9af2d6ae630f1984dabd7559b538aeb 00238904 0000007c d6f9af2d6ae630f19842bada589c 00238980 00000008 d6f9af2d44d802c2bc6881fc48a26fa8f04520159f51d1fc715149 00238988 00000008 d6f9af2d60f026ef914abcc9488d5283ec7a1726 00238990 00000068 d6f9af2d43d005f1b66486e672ad6eafc05f 002389f8 00000140 d6f9af2d5fd806c0ba6f8dd765a073a2f043310295 00238b38 0000007c d6f9af2d7ff021fe9a45bbcd488c4f8fe375 00238bb4 00000070 d6f9af2d7ff833e79b5fb7c95485 00238c24 00000048 d6f9af2d7ff833e79b5fb7ca42875682 00238c6c 000000e4 d6f9af2d5ed006f1b27987fd679175b6ca433300984dd6 00238d50 00000064 d6f9af2d7fed3fe89654a9cb5c 00238db4 00000098 d6f9af2d7fed3fe89654aadd5e825e 00238e4c 00000048 d6f9af2d7fed3fe89654bacd449e5588eb 00238e94 00000110 d6f9af2d7fed3fe89654bacd449e5588fc74 00238fa4 0000004c d6f9af2d7fed3fe89654bbcd598a5897 00238ff0 0000007c d6f9af2d5ed006f1b2689bd778be7fb4 0023906c 000000a8 d6f9af2d58db01dab46784d762a073b2 00239114 00000048 d6f9af2d7ff021fa9459bcd7538b5b8ae37e11 0023915c 00000138 d6f9af2d78fb3bfa8a5ea6d942875f95ec7416 00239294 00000094 d6f9af2d68ed26eb9b4fb7c95485 00239328 000000a4 f4d9871772c70ac3b3688c 002393cc 000000e0 d6f9af2d69e720f98a59addb47815482 002394ac 000000ec f5ce962d5fcd1fc8b66f9b 00239598 000000b4 f5c4962d5fcd1fc8b66f9b 0023964c 000000c4 d6f9af2d4ac610f1b36286ec 00239710 00000110 d6f9af2d4ac610f1bc659bed65ba 00239820 00000050 dffca03172f727e7994fb7c5509d4596fa631531 00239870 00000050 dffca03172f835fd8a5bbdda508b4587ec7a 002398c0 000000ac f6d98f2d58db03dbbc6e9beb729177a3c253370682 0023996c 000000a8 f6d98f2d59c713cdb0 00239a14 000008a8 d6f9af2d4ac610f1a07b8ce963ab 0023a2bc 0000046c f6de811972c002cab47f8d 0023a728 000002fc f6d98f2d5dc71dcdb0789bed64916bb3c65421179446 0023aa24 00000118 d6f9af2d64fb3bfa8a4da9db4391499fe1721a 0023ab3c 00000150 d6f9af2d7fed3fe89654add0438b5482 0023ac8c 000001cc d6f9af2d7eec3ced9d54afdb599d 0023ae58 000000d8 d6f9af2d7ee13dfe8a47a7cf50875481 0023af30 00000180 d6f9af2d6bfa20ed9054aedd5b824585e0610b 0023b0b0 00000294 d6f9af2d7ee133fc8154a4c750895388e8 0023b344 000001f8 d6f9af2d7ee133fc8154a4c750895388e86e1f35a276fdda 0023b53c 000002d8 d6f9af2d7ef620ef9254b8da5e835b94f6 0023b814 000002e8 d6f9af2d7ef620ef9254a5c1459c5594 0023bafc 0000012c d6f9af2d7fed3fe89654aec45899 0023bc28 00000060 d6f9af2d7fed3fe89654bfc95e9a 0023bc88 00000040 d6f9af2d7fed3fe89654accd449a 0023bcc8 00000034 d6f9af2d7fed3fe89654acda4599 0023bcfc 0000022c d6f9af2d59d01fde8a7891e674916fa8cb5e 0023bf28 00000194 d6f9af2d79f03ffe8a58b1c654914883e27e0631 0023c0bc 00000234 d6f9af2d59d01fde8a7891e674 0023c2f0 00000228 d6f9af2d4cc60bc0b6548be77abe76a3db54 0023c518 00000058 d6f9af2d7ff021fe9a45bbcd488f598d 0023c570 00000278 d6f9af2d7de020e99054bdc6409c5392fb741c 0023c7e8 00000120 d6f9af2d7de020e99054bdc6409c5392fb741c2bb26df5d854616443671750 0023c908 000005d0 d6f9af2d63e62dff804ebad1 0023ced8 000001a8 d6f9af2d4eda1cd8b0799cd776ad78 0023d080 0000011c d6f9af2d65e52dff804ebdcd488b5f92ed62 0023d19c 000000e4 d6f9af2d6ee733fd9d44becd45 0023d280 0000044c d6f9af2d6af621f1865fa9da43915588e3781c31 0023d6cc 00000928 d6f9af2d6af621f19644a5d85b8b4e83 0023dff4 00000294 d6f9af2d6fe03be29154afc45e9d4e 0023e288 00000a54 d6f9af2d4ac610f1b86a83ed 0023ecdc 0000005c d6f9af2d5fd806c0ba6f8dd774a27fa7dd6e361d8241d9fa7c 0023ed38 000000c8 d6f9af2d5fd806c0ba6f8dd764ab6e99cb5821179050dc 0023ee00 000001dc d6f9af2d5fd806c0ba6f8dd767af6eaef04226158557cb 0023efdc 000001c8 d6f9af2d49d111cc8a6f8de472ba7f 0023f1a4 0000030c d6f9af2d4ac610f1b16e84ed63ab 0023f4b0 0000008c d6f9af2d5fd806c0ba6f8dd763ab7bb4cb5e251a 0023f53c 00000070 d6f9af2d5fdb01cc8a6f8de472ba7f 0023f5ac 0000008c d6f9af2d5fd806c0ba6f8dd773a769a5ce4336 0023f638 00000494 d6f9af2d5fd806c0ba6f8dd762be7ea7db54 0023facc 00000f2c f6d98f2d5add13daa6549df8 002409f8 0000010c f6d98f2d49c01fde8a6f9cec64 00240b04 00001fe4 f6d98f2d49d010dbb2 0024683c 0000000c d7f3a73172fc3ce78154acd9 00246848 00000024 d7f3a73172f137e29c45a3d7539f 0024686c 0000001c d7f3a73172f03cff804eb7cc46 00246888 00000010 d7f3a73172fc3ce78154bbd9 00246898 00000028 d7f3a73172f436ea8a58b9 002468c0 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 002468ec 00000028 d7f3a73172e233e78154bcc15a8b5e 00246914 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0024691c 00000008 f5ce963b63e331ef 00246924 00000030 f5ce963c6ef437 00246954 00000030 f5ce962064f0 00246984 00000008 f5ce963f44c700c1a742a6de548f 0024698c 00000030 f5ce963f44c700c1a745abc952 002469bc 0000000c c1e8af3b72f61dc3b86a86ec488275a5c46e1b30 002469c8 000003d0 d6f9af2d6cf136f1984ea5ca529c 00246d98 0000016c d6f9af2d6ef431e69054a7ce51825388ea 00246f04 00000060 d6f9af2d6ef431e69054a7ce51825388ea6e0031bc6deecd 00246f64 0000025c d6f9af2d6ef431e69054a7c65b875483 002471c0 00000104 d6f9af2d6efd33e0924eb7c9429a5599fc640124b46cfc 002472c4 00000134 d6f9af2d6efd33e0924eb7cb569e5b85e6650b 002473f8 0000012c d6f9af2d6efd33e0924eb7ce56875695ee7717 00247524 00000128 d6f9af2d6efd33e0924eb7c55696458ae0760d37b072f9cb516a7e 0024764c 0000010c d6f9af2d6efd33e0924eb7c5588a5f 00247758 0000013c d6f9af2d6efd33e0924eb7c7478b4887fb781d3a 00247894 00000110 d6f9af2d4edd13c0b26eb7f865ab7ca3dd433710ae4ccbeb 002479a4 0000010c d6f9af2d6efd33e0924eb7d8458b4983e1650d3bbf6ee1 00247ab0 00000104 d6f9af2d6efd33e0924eb7da528f5e99e07f1e2d 00247bb4 00000104 d6f9af2d6efd33e0924eb7cc52885f94f0721d24a8 00247cb8 00000068 d6f9af2d6ef937ef8754a4c159854999eb7e053a 00247d20 000004d8 d6f9af2d6efa3ce89c4cb7cb5f8f5481ea75 002481f8 00000254 d6f9af2d6ee737ef814eb7cf45814f96 0024844c 00000268 d6f9af2d6ee737ef814eb7cf45814f96f06766 002486b4 00000118 d6f9af2d69f021fa8744b1d7509c5593ff 002487cc 000001ec d6f9af2d69fc21ed9a5dadda489e5f83fd62 002489b8 000000ac d6f9af2d49dc01cdba7d8dfa6e9179a9c2413e118547 00248a64 00000040 d6f9af2d49dc01cdba7d8dfa6e9179a9c2413e118547e7ea6d574b66 00248aa4 00000084 d6f9af2d69e033e28a4aabc3 00248b28 00000118 d6f9af2d69e033e28a4aabc3488a5b95 00248c40 000000d4 d6f9af2d69e033e28a4aabc348995b8ffb 00248d14 000000b8 d6f9af2d69e033e28a4aabc348995b8ffb6e163bbf67 00248dcc 0000016c d6f9af2d69e033e28a4fa9db488c4f8fe375 00248f38 000000c4 d6f9af2d69e033e28a4fbbce488c4f8fe375 00248ffc 00000054 d6f9af2d69e033e28a4fa7c652 00249050 0000011c d6f9af2d69e033e28a4fbada40915b85e4 0024916c 000001e4 d6f9af2d69e033e28a4fbada40915893e67d16 00249350 00000100 d6f9af2d69e033e28a4ca7ca488c4f8fe375 00249450 00000090 d6f9af2d69e033e28a46a9c656895f99fc781f24bd67 002494e0 00000090 d6f9af2d69e033e28a46a9c656895f99fc781f24bd67e7df597773 00249570 00000084 d6f9af2d69e033e28a58a1c547825f99ed641b38b5 002495f4 000000a8 d6f9af2d69e033e28a58a7ca488c4f8fe375 0024969c 00000340 d6f9af2d4bc01ec28a7a9de172bd79a3f04337058447cbfc7d5a 002499dc 00000098 d6f9af2d6af026f1875aa1cc 00249a74 00000214 d6f9af2d6ae73dfb8554a7ce51825388ea 00249c88 00000504 d6f9af2d44db1bda 0024a18c 000000a8 d6f9af2d60fc20fc9a59b7c75188568fe1740d26b46ff7de5d 0024a234 000000fc f5ce962d5dc71dcdb0789bd779af77a3 0024a330 00000258 f6d98f2d46dc11c58a7b9ae774ab69b5 0024a588 00000124 d6f9af2d64fb3dfe9059a9dc5e985f 0024a6ac 00000084 d6f9af2d4ad111cc8a648eee7ba774a3f05f3d009844d1eb794a4e6d4a 0024a730 00000190 d6f9af2d69f021fa8a44b8cd458f4e8ff974 0024a8c0 000001e0 d6f9af2d69f021fa8a4da9c15b8b5e 0024aaa0 00000124 d6f9af2d6efd37ed9e54a4c750915f8bff650b 0024abc4 00000250 d6f9af2d59dc1fcba67286eb7f 0024ae14 000001bc f6d98f2d58db1ec1b660b7ef64ac 0024afd0 00000110 d6f9af2d4ac610f1b8629afa78bc45abce583c 0024b0e0 0000007c d6f9af2d61f121ec8a4aabc348995b8ffb 0024b15c 000000b0 d6f9af2d61f121ec8a4aabc348995b8ffb6e0031a272 0024b20c 0000015c d6f9af2d60f020e99054acc7598b 0024b368 00000110 d6f9af2d60f020e99054a9d7448b5482f076013a 0024b478 0000021c d6f9af2d60fc20fc9a59b7ca45815183e1 0024b694 00000060 d6f9af2d60fc20fc9a59b7da529f 0024b6f4 000000c4 d6f9af2d60fc20fc9a59b7da529f4f83fc650d35b269 0024b7b8 000000b0 d6f9af2d60fc20fc9a59b7da529f4f83fc650d36a46bf4cc 0024b868 00000100 d6f9af2d60fc20fc9a59b7da529d4a89e162172bb061f3 0024b968 000000b4 d6f9af2d60fc20fc9a59b7da529d4a89e162172bb377f1c45c 0024ba1c 00000274 d6f9af2d62fb3ee79b4eb7dd59874e 0024bc90 00000404 d6f9af2d62fb3ee79b4eb7c652994593e17806 0024c094 00000070 d6f9af2d7ce03beb8648add756825699e2741f36b470eb 0024c104 00000320 d6f9af2d7ce03beb8648add7458b5789fb740d33a36dedd8 0024c424 000001a0 d6f9af2d7ce03beb8648add7458b5789fb740d21bf6bec 0024c5c4 0000008c d6f9af2d7ff03fe1814eb7cf45814f96f060073db471fbcd5c 0024c650 00000100 d6f9af2d7ff03fe1814eb7cf45814f96f0641c25a46bfddb5b7b 0024c750 000001e4 d6f9af2d7ff03fe1814eb7dd478a5b92ea6e0031a27debdc596a62 0024c934 0000008c d6f9af2d7ff03fe1814eb7dd59874e99fe641b31a261fdcc 0024c9c0 000000d8 d6f9af2d7ff03fe1814eb7dd59874e99fa7f0321b867ebcb5d 0024ca98 00000124 d6f9af2d7ff03fe1834eb7db589b4885ea 0024cbbc 0000018c d6f9af2d7fed3fe89654b8da588d5f95fc 0024cd48 00000254 d6f9af2d7ef026e79154bacd5a814e83f0641c3da5 0024cf9c 000000ec d6f9af2d7ff03fe1814eb7db529a4595ea650635b36efdd7517a 0024d088 00000140 d6f9af2d7ef026fb8554adc147 0024d1c8 00000134 d6f9af2d7ef026fb8554afda589b4a99ea7802 0024d2fc 000003a0 d6f9af2d61f13de78a5eb8cc569a5f 0024d69c 00000184 d6f9af2d7ef03cea8a4cbbc6 0024d820 000004dc d6f9af2d7ff021eb8154afdb59 0024dcfc 000001f0 d6f9af2d6ef937ef8754acc9438f458ae062062bb077ecc7 0024deec 0000038c d6f9af2d6ef937ef9b5eb8 0024e278 000000b0 d6f9af2d6efd33e0924eb7da58825f 0024e328 000002ec d6f9af2d6efd33e0924eb7c4588d5183eb 0024e614 00000574 d6f9af2d62e537fc945fa1de52 0024eb88 000000d0 d6f9af2d6ff426fa9059b1d758855b9f 0024ec58 000000f4 d6f9af2d5ed006dba5549cfd79a07faaf0543b04 0024ed4c 00000138 d6f9af2d7efd20e79b40b7c458894595e66b17 0024ee84 000003dc d6f9af2d7efc26eb8a4da9c15b814c83fd 0024f260 000002e0 d6f9af2d7efc26eb8a4da9c15b814c83fd6e073aa16ef9c6567b63 0024f540 000001e4 d6f9af2d7efc26eb8a4da9c15b814c83fd6e1327a86cfb 0024f724 00002e4c d6f9af2d5fd003f1b86a81e6 00252570 000000f8 d6f9af2d7eec3ced9d54aadd51884999ee7219 00252668 000001a0 d6f9af2d7eec3ced9d54aadd51884999ed641b38b5 00252808 000001f8 d6f9af2d7eec3ced9d54abc954865f99fd741f3ba567e7dd567773 00252a00 00000134 d6f9af2d7eec3ced9d54abc9478f598ffb68 00252b34 00000264 d6f9af2d7eec3ced9d54abc759885381 00252d98 0000008c d6f9af2d7eec3ced9d54afdb599d4587fc681c37ae63fbc3 00252e24 000000bc d6f9af2d7eec3ced9d54afdb599d4587fc681c37ae60edc1547a 00252ee0 000000bc d6f9af2d7eec3ced9d54afdb599d4584fa781e30 00252f9c 00000048 d6f9af2d78fb23fb9c4ebbcb52915b8ae36e1f31bc60fdda4b 00252fe4 00000368 d6f9af2d62f334e29c45add7458b5789f9740d21bf6bec 0025334c 00000bd0 d6f9af2d40d01ff1b66389e670ab45abce583c 00253f1c 00000ef4 d6f9af2d6ae73dfb8554a7c65b875483 00254e10 00000ae0 d6f9af2d4ad111cc8a7f9ae979bd73b2c65e3c2b9c43d1e6 002558f0 00000670 d6f9af2d4ac71ddba5548be076a07da3f05c331d9f 00255f60 00000208 d6f9af2d6efd33e0924eb7db429d4a83e1750d39b071eccd4a 00256168 000000d0 d6f9af2d6efd33e0924eb7db429d4a83e175 00256238 0000020c d6f9af2d78fb23fb9c4ebbcb52914883e27e0631ae65eac74d6e 00256444 0000016c d6f9af2d78fb23fb9c4ebbcb52914883e27e0631ae77f6c14c 002565b0 00000070 d6f9af2d78fb23fb9c4ebbcb52914883e27e0431ae77f6c14c 00256620 00000214 d6f9af2d78e536ef814eb7c553994587ec7a 00256834 000018ac d6f9af2d69e033e28a46a9c656895f 002580e0 0000015c d6f9af2d78e536ef814eb7c553994584fa781e30 0025823c 00000194 d6f9af2d59dc1fcbb1549fe765a5 002583d0 00000070 fcc8831772d31bc0b15485e165bc75b4 00258440 00000070 fcc8831772d31bc0b15498fa7ea37bb4d6 002584b0 00000164 d6f9af2d62f334e29c45add7458b5789f9740d21bf6becd751706852 00258614 000008dc d6f9af2d49c013c28a6689e179 0025d894 0000000c d7f3a73172fc3ce78154acd9 0025d8a0 00000024 d7f3a73172f137e29c45a3d7539f 0025d8c4 00000038 d7f3a73172f137ff804eb7cc46 0025d8fc 0000001c d7f3a73172f03cff804eb7cc46 0025d918 00000028 d7f3a73172f436ea8a58b9 0025d940 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0025d96c 0000005c d7f3a73172e737e39a5dadd7449f 0025d9c8 00000028 d7f3a73172e233e78154bcc15a8b5e 0025d9f0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0025d9f8 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 0025da0c 00000084 dbf8bd3064e12dfd905f 0025da90 00000168 d6f9af2d4cd610f1b16e9bfc 0025dbf8 00000038 d6f9af2d6cf639f1964aa4c4558f598d 0025dc30 00000050 d6f9af2d4edd17cdbe5498fa78ba75a5c05d0d029450 0025dc80 00000194 d6f9af2d6efd37ed9e54bcdd59805f8af0611320b9 0025de14 00000058 d6f9af2d6efa22f78a59addb47815495ea6e1337ba 0025de6c 0000004c d6f9af2d6efa22f78a59addb47815495ea6e1021b86efc 0025deb8 00000158 d6f9af2d6be737eb8f4eb7da52835590ea 0025e010 000001ac d6f9af2d6af026f19644b8d1488a5b92ee 0025e1bc 000002fc d6f9af2d6af026f18259a1dc52915e87fb70 0025e4b8 00000284 d6f9af2d64fb3bfa8a4dab 0025e73c 000000dc d6f9af2d61fc3ce58a5eb8 0025e818 00000074 f6d98f2d5dc71dcdb0789bd762a073b2f0593d07857dc9fd715b546141 0025e88c 00000188 f6d98f2d5fcd1fc8b6548be072ad7199c04426078543d6ec715040 0025ea14 000001f0 f6d98f2d5ed006f1a67f89fc72916aa3dd6e35069e57c8 0025ec04 000000e4 f6d98f2d59c01cc0b067b7fb72ba45b5db502611ae52ddfa4759556d512f 0025ece8 000003c4 f6d98f2d44db11dcb06a9bed48bc7fb5c04420179451 0025f0ac 000004ec f6d98f2d49d011dcb06a9bed48bc7fb5c04420179451 0025f598 00000308 f6d98f2d4ed41ecda06789fc72916ca2c642392b8347cbf877505467 0025f8a0 0000007c d6f9af2d7df426e68a48a0cd5485 0025f91c 00000020 d6f9af2d59c01cc0b067b7ff76a76e99dd503c10 0025f93c 00000160 d6f9af2d7de73ded9058bbd7568d51 0025fa9c 000003a0 d6f9af2d7de026f1974aabc348804c84 0025fe3c 0000018c d6f9af2d7ff03eeb9458add754814a9ff0781c 0025ffc8 00000184 d6f9af2d7ff03eeb9458add7409c5392ea6e1b3a 0026014c 000000a4 f6d98f2d5fd01ecbb4788dd763bb74a8ca5d0d1d9f 002601f0 00000194 d6f9af2d7ff03fe1814eb7d8529f 00260384 000000e8 d6f9af2d61f421fa8a4ca9db47 0026046c 00000290 d6f9af2d7ff03fe1814eb7dc529f 002606fc 00000170 d6f9af2d7ff021fa9a59add7439b5488ea7d0d3dbf 0026086c 000005d0 d6f9af2d63f439e781 00260e3c 00000ae4 d6f9af2d7ef021fa8654bacd5a814c83 00261920 00000138 d6f9af2d79e03ce09047b7c159914c87e37816 00261a58 00000694 d6f9af2d79e03ce09047b7c7429a 002620ec 0000064c d6f9af2d79e03ce09047b7c159 00262738 00000098 d6f9af2d69fa2dfc984dab 002627d0 000003fc d6f9af2d7ff021fa9a59add7409c5392ea6e1b3a 00262bcc 000001bc d6f9af2d7ff021fa9a59add754814a9ff0781c 00262d88 00000414 d6f9af2d7ef021fa8a59adcb58985f94f6 0026319c 000000d0 d6f9af2d7ff03fe1814eb7c556875492 0026326c 00000224 d6f9af2d79f033fc9144bfc6 00263490 000000ec d6f9af2d5fd001d7bb68b7e678ba73a0d6 0026357c 0000009c d6f9af2d69fa2dfc8d46aecb 00263618 000002e0 d6f9af2d6efa22f78a58adc653 002638f8 0000015c d6f9af2d79e03ce09047b7c7429a4590ee7d1b30 00263a54 000001e4 d6f9af2d6efa22f78a42a6d7418f568feb 00263c38 00000530 d6f9af2d79e03ce09047b7c556875492 00264168 0000023c d6f9af2d7ae73bfa9054a1c648985b8ae675 002643a4 00000058 d6f9af2d7ae73bfa9054bacd449e5588fc740d35b269 002643fc 00000080 d6f9af2d4cd71ddca1548ded63ac 0026447c 00000288 d6f9af2d4eda1cc0b0689cd778a045b6ce453a 00264704 000001a8 d6f9af2d60f439eb8a5fbdc6598b56 002648ac 00000f40 d6f9af2d6ef93dfd9054bcdd59805f8a 002657ec 000003c0 f6d98f2d5ed006f1a17e86e672a245b6dd5e261b924dd4 00265bac 0000008c d6f9af2d6af026f1815ea6c65282 00265c38 00000178 d6f9af2d79e03ce09047b7ce56875693fd74 00265db0 00000208 d6f9af2d6efa22f78a4fa9dc56 00265fb8 00000efc d6f9af2d6efa22f78a59addb47815495ea6e0226be61fddb4b 00266eb4 00000258 d6f9af2d6efa22f78a44bddc48985b8ae675 0026710c 000004bc d6f9af2d7ff021eb9b4fb7ce458f5783 002675c8 00000f44 d6f9af2d7de73ded9058bbd7438b4b83 0026850c 00001b58 d6f9af2d7de73ded9058bbd7478b4b83 0026a064 000003d0 d6f9af2d4edd17cdbe5498e765ba45b6dd5434 0026a434 00001050 f6d98f2d49da15 0026b484 00000318 d6f9af2d61fc3ce58a4fa7df59 0026b79c 00000114 d6f9af2d7ae73bfa9054bacd449e5588fc740d36a46bf4cc 0026b8b0 00000478 d6f9af2d7ae73bfa9054bbcd598a 0026bd28 00000698 d6f9af2d7ae73bfa9054acc9438f 0026c3c0 000004fc d6f9af2d7ae73bfa9054bacd44814f94ec740d26b476edda56 0026c8bc 00000f98 d6f9af2d7ae73bfa9054bacd449e5588fc740d24a36dfbcd4b6d 0026d854 00000ec0 d6f9af2d42db11cb8a6ab7fb72ad75a8cb 0026e714 00000260 d6f9af2d7ae73bfa9054a7dd43914c87e37816 0026e974 000001cc d6f9af2d7de73ded9058bbd7458b5789fb740d39b06bf6dc 0026eb40 00000020 d6f9af2d40d311f1a66787fc64 0026eb60 00000020 d6f9af2d4eda02d78a7884e763bd 0026eb80 00000020 d6f9af2d4eda02d78a6286d778b673a2 0026eba0 00000020 d6f9af2d4ec72dddb9649cd764a673a0db 0026ebc0 00000020 d6f9af2d5ac71bdab05481e648a162afcb 0026ebe0 00000020 d6f9af2d5ac72dddb9649cd764a673a0db 0026ec00 00000020 d6f9af2d5ac71bdab0548afd71a869 0026ec20 00000020 f6d98f2d40d40af18645b7e47ea373b2 0026ec40 00000020 f6d98f2d40d311f1bc65b7e76fa77e 0026ec60 00000020 f6d98f2d40d311f1ba7e9cd778b673a2 0026ec80 00000020 f6d98f2d40d311f1b86a90d778b673a2 0026eca0 00000020 f6d98f2d40d311f1a66787fc48bd72afc945 0026ecc0 00000020 f6d98f2d4eda02d78a649dfc48a162afcb 0026ece0 00000020 f6d98f2d5ac71bdab05487fd639175bec655 0026ed00 00000020 f6d98f2d5ac71bdab0549be478ba69 0026ed20 00000020 f6d98f2d44db1bdabc6a84d774bc69 0026ed40 00000020 f6d98f2d44db1bdabc6a84d760bc69 0026ed60 00000020 f6d98f2d40dc1cc7b87e85d774bc69 0026ed80 00000020 f6d98f2d40dc1cc7b87e85d760bc69 0027155c 00000028 d7f3a73172f436ea8a58b9 00271584 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0027158c 000000c8 f6d98f2d4fc01bc2b15486fb48bf6fa3dd48 00271654 000000e4 f6d98f2d4bd646f1a56787ef7e917fb4dd5e20 00271738 000000a4 f6d98f2d5cc017dcac548eeb239173a8c645 002717dc 000000f4 f6d98f2d5cc017dcac548eeb23917fb4dd5e20 002718d0 000002b8 f6d98f2d5cc017dcac548ae9739168a3dc413d1a8247 00271b88 000000e4 f6d98f2d5cc017dcac548eeb239168a3dc413d1a8247 00271c6c 000000c0 f6d98f2d5fdb1bca8a6286e163 00271d2c 00000508 f6d98f2d5fdb1bca8a798dfb67a174b5ca 00272234 000000c0 f6d98f2d5fdb1bca8a6e9afa78bc 002722f4 0000003c f6d98f2d5dd91dc9bc5481e67eba 00272330 0000005c f6d98f2d5dd91dc9bc549aed64be75a8dc54 0027238c 000000c0 f6d98f2d5dd91dc9bc548dfa65a168 0027295c 0000001c d7f3a73172f03cff804eb7cc46 00272978 00000028 d7f3a73172f436ea8a58b9 002729a0 0000005c d7f3a73172e737e39a5dadd7449f 002729fc 00000028 d7f3a73172e233e78154bcc15a8b5e 00272a24 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 00272a68 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00272a70 00000008 f5ce963b63e331ef 00272a78 00000030 f5ce963c6ef437 00272aa8 00000008 f5ce963f44c700c1a742a6de548f 00272ab0 00000024 f5ce96255ffd1bc9bd5c89fc72bc 00272ad4 00000024 f5ce96255ff91dd9826a9ced65 00272af8 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 00272b0c 00000064 f6d98f2d40d000c9b05489d773ba7e99c9433711 00272b70 00000064 f6d98f2d40d000c9b05489d773ba7e99c9433711ae50cf 00272bd4 00000044 d6f9af2d40d000c9b05489d763bb7499cb45362b954dd6ed 00272c18 00000014 d6f9af2d40d000c9b05489d763bb7499cb45362b984cd1fc 00272c2c 00000044 d6f9af2d40d000c9b05489d763bb7499cb45362b8256d9fa6c 00272c70 00000008 d6f9af2d40d000c9b05489d763bb7499ca5c2200887dd9fb6b53 00272c78 00000034 d6f9af2d40d000c9b05489d763bb7499c65f3b00 00272cac 00000038 f6d98f2d41da15f1b4548be573bd45afc16e20159f45dd 00272ce4 00000168 f6d98f2d40d000c9b05489d773ba7e99cb54211d8347dc 00272e4c 00000028 f6d98f2d41da15f1b4548ce963af45afc16e20159f45dd 00272e74 00000020 f6d98f2d41da15f1b4548ce963af45aac0560d169444d7fa7d614a7043 00272e94 000000cc f6d98f2d40d000c9b05489d765ab6999d8503b00ae50dde5774842 00272f60 0000005c f6d98f2d41da15f1b27886d77ea045a5c2550d1a9e46dd 00272fbc 0000013c f5ce962d41da15f1b4548be678aa7f99df433704ae44d4fd6b567871503e676f 002730f8 00000250 f5ce962d41da15f1b4548be678aa7f99df433704 00273348 000000bc f5ce962d41da15f1b4548be678aa7f99df4337049050dd 00273404 00000128 f6d98f2d41da15f1b4548fed639169b2ce4521 0027352c 000001bc f6d98f2d41da15f1b4548be97bad45b5c64b37 002736e8 00000120 f6d98f2d41da15f1b4549bed639169afd554 00273808 00000048 f6d98f2d41da15f1b4548fed639169afd554 00273850 00000028 f6d98f2d40d000c9b0549ae963a77599c05f 00273878 00000084 f6d98f2d41da15f1b45484e770917fabdf452b 002738fc 000000ac f6d98f2d41da15f1b2649cd773a768b2d6 002739a8 00000364 f5ce962d41da15f1b66587ec72 00273d0c 000000d0 f6d98f2d41da15f1b1649be765ac 00273ddc 000002a8 f6d98f2d40d000c9b0549de67ba179adf0553300907dc8fa7d5842764737 00274084 00000118 f6d98f2d40d000c9b0549de67ba179adf0523f10ae4cd7ec7d 0027419c 000000e4 d6f9af2d41da15f1ba6584e179ab45969e 00274280 00000478 f6d98f2d41da15f1ba6584e179ab45b4ca423d018341ddfb 002746f8 000000cc f6d98f2d41da15f1ba6584e179ab45a2db55 002747c4 00000108 f6d98f2d41da15f1ba6584e179ab45abc64221 002748cc 00000044 f6d98f2d41da15f1ba6584e179ab45abc642212b9c4bcafa774c 00274910 000001b0 f6d98f2d41da15f1ba6584e179ab45aedf52 00274ac0 00000058 f6d98f2d41da15f1ba6584e179ab45b6ce43261d904e 00274b18 000003d8 f6d98f2d41da15f1ba6584e179ab45a1c0450d179c46 00274ef0 00000290 e7c58e1b43de 00275180 000000a8 f6d98f2d5dc000c9b05486e773ab 00275228 000001fc d6f9af2d40d000c9b0549bfc78be 00275424 0000009c d6f9af2d40d000c9b0 002754c0 00000048 f6d98f2d40d000c9b0549ae963a77599c05734 00275508 00000030 d6f9af2d40d000c9b0548ced71ab68b4ca55 00275538 0000036c e1ce962d40d000c9b0548eed79ad7f 002758a4 0000004c f6d98f2d40d000c9b05481e67eba45a5c05d3e1d824bd7e6 002758f0 000000f8 f6d98f2d40d000c9b0549aed76aa 002759e8 000000cc f6d98f2d40d000c9b05490d77aa769b5 00275ab4 000000d8 f6d98f2d40d000c9b0548be5739168a3dc45330685 00275b8c 00000044 f6d98f2d40d000c9b0548fe7639179abcb6e36158543 00275bd0 0000004c f6d98f2d40d000c9b0548be5739179a9c35d3b07984dd6 00275c1c 00000124 f6d98f2d40d000c9b0549ffa7eba7f 00275d40 000000f0 d6f9af2d40d000c9b0549cfd79a07faaf042251d8541d0 00275e30 000000e8 d6f9af2d41da15f1a5798df876bc7f99df44201394 00275f18 0000005c d6f9af2d41da15f1a5798df876bc7f99c95d270799 00275f74 00000034 d6f9af2d41da15f1ba6d8ee47ea07f 00275fa8 00000074 dffca03109f727e7994fb7c45383 0027601c 0000019c dffca03109f727e7994fb7c55b8a 002761b8 0000017c dffca03109f936e38a4aabc3 00276334 00000288 f6d98f2d41da15f1b8629afa78bc45a2c250 002765bc 0000011c dffca03109e520e1964ebbdb48835682 002766d8 00000170 f6d98f2d41da15f1b8629afa78bc45a5c05c22189456dd 00276848 000000ec d6f9af2d46dc1ec28a6787ef48bb74afdb 00276934 0000009c f6d98f2d41da15f1b36286ec48a27fa0db5c3d0785 002769d0 00000060 f6d98f2d41da15f1a7789ce765ab45a2ca503e189e41e7eb774b4976 00276a30 00000188 f6d98f2d41da15f1a6639ae179a5 00276bb8 00000288 d6f9af2d41da15f1a5798de97ba275a5 00276e40 00000580 d6f9af2d41da15f1b16e89e47ba179 002773c0 00000068 f6d98f2d41da15f1b16e89e47ba17999c458311f 00277428 000001dc d6f9af2d4bd41bc2ba7d8dfa48be6fb4c8540d189e45 00277604 000003f0 d6f9af2d41da15f1ba6584e179ab45969d 002779f4 0000003c f6d98f2d5cc017dbb0548ffb799175b4cb5420 00277a30 000001a8 f6d98f2d40d000c9b05484e778be45aac05239 00277bd8 00000798 f6d98f2d41da15f1b26e9cd775bb7ca0dc 00278370 00000238 f6d98f2d40d000c9b05489d773ba7e99ce5536 002785a8 000000a0 f6d98f2d40d000c9b05489d773ba7e99ce55362b9c43d1e6 00278648 00000554 d6f9af2d41da15f1b66485f87bab6ea3 00278b9c 00000098 f6d98f2d4eda1fdeb96e9ced48bc7bb2c65e 00278c34 00000090 f6d98f2d5fd406c7ba549de660a774a2f0503e18 00278cc4 00000948 f6d98f2d40d000c9b0549afd79aa75b1c1 0027960c 000000e4 dffca03109f83eea8a4aabc3 002796f0 000000a0 dffca03109e520e1964ebbdb48825e8b 00279790 000000b0 f6d98f2d41da15f1b37e84e448aa7fb7da542711 00279840 000007b8 f6d98f2d5dc71dcdb0789bd77ba17d99c9443e18 00279ff8 00000884 f6d98f2d40d000c9b05484e778be 0027a87c 0000004c f6d98f2d40d000c9b05481e67eba45a2ce4533 0027a8c8 00000448 f6d98f2d40d000c9b05484e778be45f4 0027ad10 00000378 f6d98f2d40d000c9b05481e67eba45aac05e22 0027b088 000000f8 f6d98f2d40d000c9b0549bfc76bc6e99cb4536 0027b180 000000dc f6d98f2d49d406cfa4549aed64ba7bb4db 0027b25c 00000170 f6d98f2d40d000c9b0548ee462bd7299dd5421009050cc 0027b3cc 00000048 f6d98f2d40d000c9b0548be5739172afdb 0027b414 00000038 f6d98f2d40d000c9b05490d767af68b2c6503e 0027b44c 000000cc f6d98f2d40d000c9b0549aed76aa45a3dd433d06 0027b518 00000104 f6d98f2d40d000c9b0549aed76aa45a5c05c22189456dd 0027b61c 000002cc f6d98f2d40d000c9b0548fed63917ea7db50 0027b8e8 00000168 f6d98f2d40d000c9b0548fed63917ea7db500d109444ddfa6a5b43 0027ba50 0000018c f6d98f2d40d000c9b0548be963ad72b3df 0027bbdc 00000528 f6d98f2d40d000c9b0549bfc76bc6e 0027c104 0000044c f6d98f2d40d000c9b05483e174a57fa2 0027c550 000000a0 f6d98f2d40d000c9b05489d773ba7e99ce55362b9240 0027c5f0 0000017c f6d98f2d41da15f1b66498f148ad75abdf5d370094 0027c76c 000007c0 f6d98f2d41da15f1b26e9cd765ab69a9da43311182 0027cf2c 000000e8 f6d98f2d41da15f1b4548ee462bd7299dd5421009050cc 0027d014 000001b8 f6d98f2d41da15f1a67f89fa63916db4c64537 0027d1cc 000013e0 d6f9af2d41da15f1b66389e670ab45abce583c 0027e5ac 00000884 f6d98f2d40d000c9b05487fa73ab6899cc5e3f049d47cced 0027ee30 00000104 f6d98f2d40d000c9b0549ffa7eba7f99cc5e3f049d47cced 0027ef34 0000015c f6d98f2d40d000c9b0549ffa7eba7f99cc5e3c00984ccded 0027f090 00000058 f6d98f2d40d000c9b0549be37ebe45b1dd582611 0027f0e8 00000558 f6d98f2d41da15f1ba6584e179ab45a1c0450d109056d9 0027f640 00000104 d6f9af2d41da15f1a27981fc72 00280974 0000005c e1df901c4ed406 002809d0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002809d8 000002d0 dbe7a42d4eda1cd8b0799cd779bd7999db583f11 00280ca8 00000044 dbe7a42d4ad006f1b16e8ee179a76eafc05f 00280cec 00003c44 dbe7a42d5dc71bc0a1548de663bc63 00284930 0000022c dbe7a42d5dc71bc0a15498e970ab 00284b5c 00000004 fbc7842d4cc601dbb86e9b 002a5218 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002a5220 00000008 f5ce963b63e331ef 002a5228 00000030 f5ce962064f0 002a5258 000004e0 fbc7842d4ed91dddb05484e770 002a5738 00000190 fbc7842d4eda07c0a1548de663bc73a3dc 002a58c8 00000360 dbe7a42d48db06dcac 002a5c28 00000018 dbe7a42d4ad006f1b9648fd774a27bb5dc6e3f158249 002a5c40 0000000c dbe7a42d4ad006f1b9648fd774a177b6c05f371a857dd5e96b55 002a5c4c 00000008 dbe7a42d4ad006f1b66a8be0729177a3c25e200dae46d1e57561546b5e3a 002a5c54 00000008 dbe7a42d4ad006f1a56484e174b745abca5c3d06887ddce1755378714d2570 002a5c5c 000000bc fbc7842d4fc01bc2b1548bfa7aaa 002a5d18 00000084 dbe7a42d41da15f1b16a9ce9 002a5d9c 00000d04 dbe7a42d44db1bda 002a6aa0 00000384 fbc7842d40d016c7b4549bfc76bc6e 002a6e24 00000028 fbc7842d40d016c7b4549fe97eba 002a6e4c 00000078 dbe7a42d40d01fc1a772b7fa72af7e 002a6ec4 000001dc fbc7842d5fd001cba15484e770a973a8c8 002a70a0 00000394 dbe7a42d40d01fc1a772b7fb72bd69afc05f0d1b8147d6 002a7434 00000034 dbe7a42d5dc717c7bb629c 002a7468 00000068 dbe7a42d5dc71bc0a16db7ea65ab7bad 002a74d0 00000084 fbc7842d5dc001c68a6787ef 002a7554 00000078 dbe7a42d5fd015c7a67f8dfa48be7fb4c9 002a75cc 00000028 fbc7842d5fd01ecbb4788dd774a17ea3f05d3d15957dcaed6b515270473a 002a75f4 00000034 dbe7a42d40d01fc1a772b7fb72bd69afc05f0d179d4dcbed 002a7628 000001ac fbc7842d5fd001dab4799cd77ba17d 002a77d4 000000b8 fbc7842d5fd001daba798dd767ab68a0 002a788c 0000023c dbe7a42d5ed006f1b67989fb7f9169a3dc423b1b9f7ddbe77553426c50 002a7ac8 000000d4 dbe7a42d5ed006f1b9648fd774a177b6c05f371a857dd5e96b55 002a7b9c 000000c4 dbe7a42d5ed006f1b9648fd774a27bb5dc6e3f158249 002a7c60 0000010c dbe7a42d5edd1dd98a6887e567bd45a5c350210782 002a7d6c 0000029c dbe7a42d5edd1dd98a789ce963bb69 002a8008 0000017c fbc7842d5ec513c08a6e86fc65a77fb5 002a8184 00000258 dbe7a42d49c01fde8a6787ef 002a83dc 00000444 dbe7a42d5edd1dd98a6787ef 002a8820 00000068 dbe7a42d5ec11dde8a6f81fb7c 002a8888 00000110 fbc7842d57d000c18a788dfb64a775a8f05937159547cafb 002a8998 000003d0 dbe7a42d58c516cfa16eb7eb65af69aef0423707824bd7e66b 002a8d68 00000148 fbc7842d5ac71bdab05484e770a67eb4 002a8eb0 000009e0 dbe7a42d40d016c7b4 002a9890 00000034 dbe7a42d5dd000c88a6787ef48bb74a2ca573b1a9446e7ed6e5b4976 002a98c4 00000068 f1c3890259ea1fcbb8649af148bd7fb5dc583d1aae4dc8ed76 002a992c 000000bc f1c3890259ea1fcbb8649af148bc7fa7cb 002a99e8 0000004c f1c3890259ea1fcbb8649af148bd7fb5dc583d1aae41d4e76b5b 002a9a34 000000bc dbe7a42d41da15f1bc64 002a9af0 00000190 fbc7842d44da 002a9c80 00000250 dbe7a42d44da2dcaba658d 002a9ed0 00000038 dbe7a42d5dd000c88a6787ef48be68a9cc542107ae46d1fb685f53614c 002a9f08 00000088 dbe7a42d45c52ddeb0798ed77ba17d99c1583d 002a9f90 00000334 dbe7a42d45c52ddeb0798ed77ba17d99c65e36 002aa2c4 00000230 dbe7a42d45c52ddeb0798ed77ba17d99c65e362b824ad7fa6c 002aa4f4 00000080 dbe7a42d45c52ddeb0798ed77ba17d99c65e0d109e4cdd 002aa574 00000210 dbe7a42d45c52dc2ba6cb7fb74bd73 002aa784 00000234 dbe7a42d45c52dc2ba6cb7fb74bd7399dc4430118747d6fc 002aa9b8 000001bc dbe7a42d45c52dc2ba6cb7fb74bd7399cb5e3c11 002aab74 00000098 dbe7a42d45c52dc2ba6cb7ec7ebd79a7dd550d119d51e7e16b4c 002aac0c 00000164 dbe7a42d45c52dc2ba6cb7ec7ebd79a7dd550d1d9d51e7e16b4c 002aad70 000000ec dbe7a42d45c52dc2ba6cb7ff60a069 002aae5c 0000009c dbe7a42d45c52dc2ba6cb7ec7ebd79a7dd550d119d51 002aaef8 0000009c dbe7a42d45c52dc2ba6cb7ed7bbd45b4ca4027118256 002aaf94 0000009c dbe7a42d45c52dc2ba6cb7ed7bbd45a7cc52370485 002ab030 000000a0 dbe7a42d45c52dc2ba6cb7ed7bbd45b4ca5b371785 002ab0d0 00000304 dbe7a42d45c52dc2ba6cb7ec7ebd79a7dd550d168451c1d77150416d 002ab3d4 00000344 dbe7a42d45c52dc2ba6cb7f865a179a3dc420d168451c1d77150416d 002ab718 000000cc dbe7a42d45c52dc2ba6cb7e974ad7fb6db6e371882 002ab7e4 000000f8 dbe7a42d45c52dc2ba6cb7ee74917db5f0433705 002ab8dc 000000fc dbe7a42d45c52dc2ba6cb7ee74917db5f0432104 002ab9d8 000000e4 dbe7a42d45c52dc2ba6cb7fa72a47fa5db6e371882 002ababc 000000cc dbe7a42d45c52dc2ba6cb7fa72bf6fa3dc450d119d51 002abb88 0000008c dbe7a42d45c52dc2ba6cb7fc76ad72bfc05f 002abc14 00000084 dbe7a42d45c52dc2ba6cb7eb74ac 002abc98 00000080 dbe7a42d45c52dc2ba6cb7e974ac 002abd18 00000094 dbe7a42d45c52dc2ba6cb7e965 002abdac 000001b8 dbe7a42d45c52dc2ba6cb7e063ac 002abf64 00000098 dbe7a42d45c52dc2ba6cb7fb74bc73b6db 002abffc 00000060 dbe7a42d45c52dc2ba6cb7e179a875f7 002ac05c 00000070 dbe7a42d45c52dc2ba6cb7e179a875f4 002ac0cc 00000080 dbe7a42d45c52dc2ba6cb7e179a875f5 002ac14c 00000070 dbe7a42d45c52dc2ba6cb7e179a875f2 002ac1bc 000000bc dbe7a42d45c52dc2ba6cb7f962a77fb5cc54 002ac278 00000088 dbe7a42d45c52dc2ba6cb7e0729169b2ce4537 002ac300 000000ac dbe7a42d45c52dc2ba6cb7e063ac45a5c9 002ac3ac 000000bc dbe7a42d45c52dc2ba6cb7fa72a375b2ca6e2117824b 002ac468 00000070 dbe7a42d45c52dc2ba6cb7e174a16ab5 002ac4d8 0000006c dbe7a42d45c52dc2ba6cb7e174a16ab5f04120119357d1e47c 002ac544 00000090 dbe7a42d45c52dc2ba6cb7fa72bd7fb4d950261d9e4c 002ac5d4 00000084 dbe7a42d45c52dc2ba6cb7fa72bd7fb4d950261d9e4c89 002ac658 000000f4 dbe7a42d45c52dc2ba6cb7fa72bd7fb4d950261d9e4ce7e97b5d4271570076737814e100 002ac74c 000000f4 dbe7a42d4ed82ddeb0798ed77ba17d99c35e311f 002ac840 000000e8 dbe7a42d4ed82ddeb0798ed77ba17d99c35e311fae44d4e97f4d 002ac928 00000128 dbe7a42d4ed82ddeb0798ed77ba17d99c35e311fae51dee4795954 002aca50 000000c0 dbe7a42d4ed82ddeb0798ed77ba17d99c35e311fae4fd1fb6b 002acb10 000000c0 dbe7a42d4ed82dc2ba6cb7e572ba7b99c35e311f 002acbd0 00000094 dbe7a42d4ed82dc2ba6cb7e572ba7b99da5f3e1b9249 002acc64 000000a4 dbe7a42d4ed82ddeb0798ed77ba17d99dc413e1d857dd5ed6a5942 002acd08 00000038 dbe7a42d4ed82ddeb0798ed77ba17d99c15e3611ae4fd1fb7b 002acd40 00000070 dbe7a42d4ed82ddeb0798ed77ba17d99c95d270799 002acdb0 00000064 dbe7a42d4ed82ddeb0798ed77ba17d99dd5837 002ace14 000000cc dbe7a42d4ed82dc2ba6cb7fd79a76e 002acee0 00000818 dbe7a42d4ed82ddeb0798ed77ba17d99c257312b8247d6fc 002ad6f8 00000960 dbe7a42d4ed82ddeb0798ed77ba17d99c257312b8150d7eb7d4d54 002ae058 000007a4 dbe7a42d4ed82ddeb0798ed77ba17d99c257312b9041d3 002ae7fc 00000060 dbe7a42d4ed82dc2ba6cb7e179a875f7 002ae85c 00000070 dbe7a42d4ed82dc2ba6cb7e179a875f4 002ae8cc 00000080 dbe7a42d4ed82dc2ba6cb7e179a875f5 002ae94c 00000070 dbe7a42d4ed82dc2ba6cb7e179a875f2 002ae9bc 000000d4 dbe7a42d4ed82dc2ba6cb7e779a273a8ca6e3f118543e7e47c514e 002aea90 00000070 dbe7a42d4ed82dc2ba6cb7e779a273a8ca6e3f118543e7e46d 002aeb00 000000a4 dbe7a42d4ed82dc2ba6cb7e779a273a8ca6e3f118543e7e67b5f57 002aeba4 000000b8 dbe7a42d4ed82dc2ba6cb7e779a273a8ca6e3f118543e7fb614d 002aec5c 0000007c dbe7a42d4ec62dc2ba6cb7e178 002aecd8 00000084 dbe7a42d4ec62dc2ba6cb7e178917ea9c154 002aed5c 0000014c dbe7a42d4ec62dc2ba6cb7e775a445abce5f3b04844ed9fc7151495d741c 002aeea8 00000064 dbe7a42d4ec62dc2ba6cb7e775a445abce5f3b04844ed9fc715149 002aef0c 00000090 dbe7a42d4ec62dc2ba6cb7e775a445abce5f3b04844ed9fc7151495d4127617e771ee301 002aef9c 000000c0 dbe7a42d4ec62dc2ba6cb7e775a445b4ca570d24b2 002af05c 00000074 dbe7a42d4ec62dc2ba6cb7e775a445b4ca57 002af0d0 00000114 dbe7a42d4ec62dc2ba6cb7e773b975b4c4 002af1e4 00000080 dbe7a42d4ec62dc2ba6cb7e974ac6d 002af264 00000078 dbe7a42d4ec62dc2ba6cb7ea709175b6 002af2dc 000000cc dbe7a42d4ec62dc2ba6cb7ec62ac45a5ce4133179856c1d77150416d 002af3a8 000000dc dbe7a42d4ec62dc2ba6cb7ec62ac45afc1573d 002af484 00000064 dbe7a42d4ec62dc2ba6cb7ef76ba7f 002af4e8 000000fc dbe7a42d4ec62dc2ba6cb7e076bd72b2f0583c129e 002af5e4 00000098 dbe7a42d4ec62dc2ba6cb7e473af7e99cc502215924bccf1475749644b 002af67c 00000074 dbe7a42d4ec62dc2ba6cb7e578be45afdb543f 002af6f0 00000084 dbe7a42d4ec62dc2ba6cb7e4739179a7df50311d855be7e1765848 002af774 00000068 dbe7a42d4ec62dc2ba6cb7e473bd78 002af7dc 00000058 dbe7a42d4ec62ddeb0798ed77ba17d99dd54211b8450dbed 002af834 0000009c dbe7a42d4ec62dc2ba6cb7fa7bac 002af8d0 000000bc dbe7a42d4ec62dc2ba6cb7fa64aa7799c65e0d24b2 002af98c 00000074 dbe7a42d4ec62dc2ba6cb7fa64aa7799c65e 002afa00 00000120 dbe7a42d4ec62dc2ba6cb7fa64bd45afc1573d 002afb20 00000174 dbe7a42d4ec62dc2ba6cb7fa64ba75b4ca6e27049543cced 002afc94 00000080 dbe7a42d4ec62dc2ba6cb7fa64ba75b4ca6e3f159f4bc8fd745f536b4b31 002afd14 0000035c dbe7a42d4ec62dc2ba6cb7fc65af74b5ce52261d9e4ce7d85b 002b0070 00000064 dbe7a42d4ec62dc2ba6cb7fc65af74b5ce52261d9e4c 002b00d4 0000019c dbe7a42d4ec62dc2ba6cb7f07aa879 002b0270 00000438 dbe7a42d5fc62dc2ba6cb7e178 002b06a8 0000040c dbe7a42d5fc62ddeb0798ed77ba17d99c65e 002b0ab4 00000024 dbe7a42d5fc62ddeb0798ed77ba17d99c65e0d03834bcced 002b0ad8 00000024 dbe7a42d5fc62ddeb0798ed77ba17d99c65e0d069443dc 002b0afc 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e 002b0b4c 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7ea4 002b0b9c 00000050 dbe7a42d5fc62dc2ba6cb7ff65a76ea3 002b0bec 00000050 dbe7a42d5fc62dc2ba6cb7ff65a76ea3cd 002b0c3c 00000050 dbe7a42d5fc62dc2ba6cb7ed65af69a3 002b0c8c 0000008c dbe7a42d5fc62dc2ba6cb7ff61b6 002b0d18 0000006c dbe7a42d5fc62dc2ba6cb7fa72ad75a8f043371595 002b0d84 0000005c dbe7a42d5fc62dc2ba6cb7e975a075b4c2503e 002b0de0 000001ac dbe7a42d5fc62dc2ba6cb7fa72af69b5c6563c2b8347dfed76 002b0f8c 000001c4 dbe7a42d5fc62dc2ba6cb7fa72af69b5c6563c2b8347dfed7661436d4a3a 002b1150 0000006c dbe7a42d5fc62dc2ba6cb7f865a177a9db583d1a 002b11bc 0000006c dbe7a42d5fc62dc2ba6cb7f865a177a9db583d1aae46d7e67d 002b1228 000000d8 dbe7a42d5fc62dc2ba6cb7ea75bc 002b1300 000000f4 dbe7a42d5fc62dc2ba6cb7ea75bc45a2c05f37 002b13f4 00000088 dbe7a42d5fc62dc2ba6cb7ea75bc45a5c75a 002b147c 000000a8 dbe7a42d5fc62dc2ba6cb7ea75bc45a5c75a0d109e4cdd 002b1524 00000090 dbe7a42d5fc62dc2ba6cb7fa72be7bafdd 002b15b4 000000a8 dbe7a42d5fc62dc2ba6cb7fa72be7bafdd6e361b9f47 002b165c 00000088 dbe7a42d5fc62dc2ba6cb7eb78be6399dd423713 002b16e4 000000a0 dbe7a42d5fc62dc2ba6cb7eb78be6399dd423713ae46d7e67d 002b1784 0000005c dbe7a42d5fc62dc2ba6cb7eb78be6399df592b079841d9e4 002b17e0 0000005c dbe7a42d5fc62dc2ba6cb7eb78be6399df592b079841d9e4475a486c41 002b183c 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e99c254201394 002b188c 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e99c2542013947ddce7765b 002b18dc 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e99c2542013947dc9fb 002b192c 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e99c2542013947dc9fb475a486c41 002b197c 00000050 dbe7a42d5fc62dc2ba6cb7fa72ac6fafc3550d049050d1fc61 002b19cc 00000050 dbe7a42d5fc62dc2ba6cb7fa72ac6fafc3550d049050d1fc6161436d4a3a 002b1a1c 0000006c dbe7a42d5fc62dc2ba6cb7fa269177a3dd5637 002b1a88 00000050 dbe7a42d5fc62dc2ba6cb7fa269177a3dd56372b954dd6ed 002b1ad8 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7e99cb5e3c11 002b1b28 00000050 dbe7a42d5fc62dc2ba6cb7fa72af7ea4f0553d1a94 002b1b78 00000050 dbe7a42d5fc62dc2ba6cb7fe72bc73a0d653 002b1bc8 00000050 dbe7a42d5fc62dc2ba6cb7fe72bc73a0d6530d109e4cdd 002b1c18 00000050 dbe7a42d5fc62dc2ba6cb7ff65a76ea3f0553d1a94 002b1c68 00000050 dbe7a42d5fc62dc2ba6cb7ff65a76ea3cd6e361b9f47 002b1cb8 00000050 dbe7a42d5fc62dc2ba6cb7ed65af69a3f0553d1a94 002b1d08 0000008c dbe7a42d5fc62dc2ba6cb7ff61b645a2c05f37 002b1d94 00000038 dbe7a42d5fc62ddeb0798ed77ba17d99cb5c3311 002b1dcc 0000024c dbe7a42d5fc62ddeb0798ed77ba17d99cb5c33 002b2018 00000228 dbe7a42d5fc62ddeb0798ed77ba17d99cb5c332b954dd6ed 002b2240 000002f0 dbe7a42d4bd601f1b9648fd77ea1 002b2530 00000390 dbe7a42d4bd601f1b9648fd77ea145a3dd433d06 002b28c0 00000288 dbe7a42d4bd601f1a56e9aee48a275a1f0583d 002b2b48 00000338 dbe7a42d4bd601f1a56e9aee48a275a1f0583d10 002b2e80 0000021c dbe7a42d4bd601f1a56e9aee48a275a1f0583d10ae51d0e76a4a 002b309c 00000008 dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae50ddf9 002b30a4 00000024 dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae40cde1745a 002b30c8 00000014 dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae51dde67c 002b30dc 00000014 dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae50dbfe 002b30f0 00000010 dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae41d9e4745c46614f 002b3100 0000001c dbe7a42d4bd601f1a56e9aee48a275a1f05c3417ae46dde471484270 002b311c 00000028 dbe7a42d4bd601f1a56e9aee48a275a1f05c2516927dcbed765a 002b3144 00000020 dbe7a42d4bd601f1a56e9aee48a275a1f05c2516927dcaeb6e6155665d 002b3164 00000008 dbe7a42d4bd601f1a56e9aee48a275a1f05c2516927ddbe9745245634734 002b316c 0000006c dbe7a42d5ed601f1b9648fd774bd7ba5cd 002b31d8 0000006c dbe7a42d5ed601f1b9648fd774b877a5cd 002b3244 00000074 dbe7a42d5ed601f1b9648fd774bd77a5cd 002b32b8 000000ac dbe7a42d5ed601f1b9648fd772a269 002b3364 00000200 dbe7a42d5ed601f1b9648fd771be7899c15e3611ae4cd9e57d 002b3564 00000074 dbe7a42d5ed601f1b9648fd771bb74a5f05233189d 002b35d8 00000074 dbe7a42d5ed601f1b9648fd771bb74a5f05233189d50ddfc6d4c49 002b364c 00000074 dbe7a42d5ed601f1b9648fd771bb74a5f04337008450d6 002b36c0 00000070 dbe7a42d5ed601f1b9648fd770af6ea3f0523d1a954bcce1775078614c3e7b7c7c 002b3730 00000088 dbe7a42d5ed601f1b9648fd770af6ea3f0523d019f56e7eb705f496541 002b37b8 00000080 dbe7a42d5ed601f1b9648fd770ab74a3dd58312b924dd6ee7159 002b3838 000004f4 dbe7a42d5ed601f1b9648fd77eaa45a4c35e311f 002b3d2c 00000080 dbe7a42d5ed601f1b9648fd77ba179a7c36e221b8356e7ed6e5b4976 002b3dac 00000080 dbe7a42d5ed601f1b9648fd778ac7099ca47371a85 002b3e2c 00000060 dbe7a42d5ed601f1b9648fd767ad6eafc2542100904fc8 002b3e8c 00000074 dbe7a42d5ed601f1b9648fd766bb7fb3ca 002b3f00 00000098 dbe7a42d5ed601f1b9648fd765ab77a9db540d1a9e46ddd77d48426c50 002b3f98 00000098 dbe7a42d5ed601f1b9648fd765ab77a9db540d049e50ccd77d48426c50 002b4030 0000006c dbe7a42d5ed601f1b9648fd764ad69a5cd 002b409c 000000ac dbe7a42d5ed601f1b9648fd763aa69 002b4148 000000a4 dbe7a42d5ed601f1b9648fd760a876a9d8 002b41ec 00000008 dbe7a42d5ed601f1b9648fd76fa37ca5 002b41f4 000000a8 dbe7a42d5dc71bc0a16db7e478a945b6dd583c0097 002b429c 0000012c dbe7a42d49c71ff1b9648fd77ba179ad 002b43c8 0000003c dbe7a42d49c71ff1b9648fd762a076a9cc5a 002b4404 000000e4 dbe7a42d49c71ff1b9648fd770bd78 002b44e8 0000009c dbe7a42d49c71ff1b9648fd77baa69a4 002b4584 00000098 dbe7a42d49c71ff1b9648fd773aa79a4 002b461c 00000070 dbe7a42d49c71ff1b9648fd771ad45b2da5f3c119d 002b468c 000000f8 dbe7a42d49c71ff1b9648fd773ba7e 002b4784 00000100 dbe7a42d49c71ff1b9648fd772ab6ea4 002b4884 0000010c dbe7a42d49c71ff1a56e9aee48a275a1f0422017ae4bd7 002b4990 00000138 dbe7a42d49c71ff1a56e9aee48a275a1f0553707857dd1e7 002b4ac8 00000268 dbe7a42d49c71ff1a56e9aee48a275a1f05c3417ae51dde66c 002b4d30 00000150 dbe7a42d49c71ff1a56e9aee48a275a1f05c3417ae52cae77b5b5471 002b4e80 000002cc dbe7a42d49c71ff1a56e9aee48a275a1f04337199e56ddd76a5b56 002b514c 00000088 dbe7a42d49c71ff1a56e9aee48a275a1f05d3d13 002b51d4 00000064 dbe7a42d49c71ff1a56e9aee48a275a1f04337199e56ddd76a4d5561 002b5238 000000a0 dbe7a42d49c71ff1b9648fd776ad78 002b52d8 00000094 dbe7a42d49c71ff1b9648fd774ad78 002b536c 00000060 dbe7a42d49c71ff1b9648fd77ea07ca99e 002b53cc 00000070 dbe7a42d49c71ff1b9648fd77ea07ca99d 002b543c 00000080 dbe7a42d49c71ff1b9648fd77ea07ca99c 002b54bc 00000070 dbe7a42d49c71ff1b9648fd77ea07ca99b 002b552c 0000022c dbe7a42d49c71ff1a56e9aee48a275a1f0553300907dcbe0774c53 002b5758 000002ec dbe7a42d49c71ff1a56e9aee48a275a1f055330090 002b5a44 000000f0 dbe7a42d40d107f1b9648fd760a168adc6453719 002b5b34 00000098 dbe7a42d40d107f1b9648fd775a969b2ce4326 002b5bcc 0000006c dbe7a42d40d107f1b9648fd775a97fa8cb 002b74d8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002b74e0 00000028 dbe7a42d48d111 002b7508 00000428 dbe7a42d4ed91dddb05484e770 002b7930 00000064 dbe7a42d58c516cfa16eb7f87a 002b7994 000000ac dbe7a42d49c01fde8a6f81fb76ac76a3 002b7a40 000002c0 dbe7a42d49c01fde8a6286e163 002b7d00 000000bc dbe7a42d49c01fde8a7c9ae163ab 002b7dbc 00000104 dbe7a42d49c01fde8a7e98ec76ba7f99c6550d169d4ddbe3 002b8394 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002b839c 000000d4 fbc7842d40d01ff1b66383f8639176a9c8 002b8470 000000bc dbe7a42d6edd17cdbe7b87e179ba 002b852c 000000b8 dbe7a42d6edd17cdbe6f89fc76 002b85e4 00000040 dbe7a42d4cc71ff1b86e85d774a67fa5c4413d1d9f56cb 002b8624 00000064 dbe7a42d59c71bc9b26e9ad77aab7799cc5937179a52d7e1764a54 002b8688 00000064 dbe7a42d48db13ccb96eb7e572a345a5c754311f814dd1e66c4d 002b86ec 00000094 dbe7a42d44db1bda8a668de548ad72addf4521 002b8780 00000040 dbe7a42d49dc01cfb7678dd77aab7799cc5937179a52d7e1764a54 002b87c0 00000048 dbe7a42d4ad006f1a67f89fc62bd45abca5c0d179947dbe368514e6c502c 002b8808 00000328 dbe7a42d5dc71bc0a15485ed7a9179aeca5239049e4bd6fc6b 002b8db4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002b8dbc 00000100 f4c8912d49c01fde8a7c89e1639179ab 002b8ebc 00000160 f4c8912d49c01fde8a679df848b97bafdb 002b901c 00000120 f4c8912d49c01fde8a7b84e770a745b4c545 002b913c 00000064 f4c8912d49c01fde8a6286ec72b645a9c96e3611874bdbed 002b91a0 00000024 f4c8912d49c01fde8a6781f8 002b91c4 00000070 e2d98b1c59ea10d7a16e9b 002b9234 000001b8 f4c8912d49c01fde8a6c8dfc48a275a9df6e3f1581 002b93ec 00000124 f4c8912d49c01fde8a6787ef78bb6e 002b9510 00000078 f4c8912d49c01fde8a6887f86e9169a0de 002b9588 000001d0 f4c8912d49c01fde8a6286ea78bb74a2f0523f 002b9758 00000180 f4c8912d49c01fde8a6d85d774a3 002b98d8 00000790 f4c8912d49c01fde8a6787ef7ea0 002ba068 0000013c f4c8912d49c01fde8a6f8dfe7ead7f99cb5821179e54ddfa61 002ba1a4 000007b8 d4e8b12d49c01fde8a798de973917ea7db50 002ba95c 000007a4 f4c8912d49c01fde8a7c9ae163ab45a2ce4533 002bb100 00000100 f4c8912d49da2dcaa06698 002bb200 00000334 f4c8912d49c01fde8a6286e163 002bb534 000001f8 d4e8b12d49da2dcaa06698 002bb72c 00000184 d4e8b12d49c01fde8a6286e163 002bbcf8 0000000c d7f3a73172fc3ce78154acd9 002bbd04 00000024 d7f3a73172f137e29c45a3d7539f 002bbd28 0000001c d7f3a73172f03cff804eb7cc46 002bbd44 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002bbd4c 00000004 f6c2910241d40bf1b86e85e765b7 002bbd50 00000140 fbc591175fc12ddea76e89e47ba179a7db5436 002bbe90 000000e4 fec48d1958c52ddcb06c81e779 002bbf74 00000048 fbc591175fc12dc8a76a8fe572a06e 002bbfbc 000000d8 f6c4bd145fd415c3b0659cfb 002bc094 000001dc e1ce96075dea11cfb6638dd765ab7dafc05f 002bc270 00000124 ffc6bd114cc704cb8a668de578bc63 002bc394 00000048 fcca8f175e 002bc3dc 00000178 dfe6bd311fe5 002bc554 000000c0 dfe6bd3361f93ded8a58bcda428d4e 002bc614 00000004 ffc6bd044cd91bcab47f8d 002bc618 0000060c dfe6bd3b63fc26 002bcc24 00000044 dfe6bd1548c12dcfb96787eb76ba7fa2f0472217 002bcc68 00000044 dfe6bd1548c12dcfb96787eb76ba7fa2f0473c0492 002bccac 00000048 dfe6bd1548c12dcfb96787eb76ba7fa2f05f240492 002bccf4 00000044 dfe6bd1548c12dcfb96787eb76ba7fa2f05f241a8141 002bcd38 00000048 dfe6bd1c42db04c1b96a9ce17bab45b4ca563b1b9f51 002bd048 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002bd050 000000a8 d4e8ae2a72c213c7a15489e6739179aeca52392b924f 002bd0f8 00000158 f4c88e0a72d61acbb660b7ee74917ea3d9583111ae51cce96c5b 002bd250 000004f8 d4e8ae2a72d813c7bb 002bd748 000002ec d4e8ae2a72c213c7a1548ee765917ea3d9583111ae50cbf8 002bda34 00000044 d4e8ae2a72d61dc2b96e8bfc48ab68b4f0523d019f56ddfa6b 002bda78 0000004c d4e8ae2a72d61ecbb479b7ed65bc45a5c0443c009450cb 002bdd5c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002bdd64 00000168 d4e8ae2a72d817c3ba7991d77ea073b2 002bdecc 00000330 f4c88e0a72c51ddca15481e67eba 002be1fc 00000088 d4e8ae2a72c51ddca15484e964ab6899c05f 002be284 000000f0 f4c88e0a72c213c7a1548ee7659179ab 002be374 00000060 d4e8ae2a72d91dc1a55484e167 002be3d4 000002b0 d4e8ae2a72c317dcbc6d91d771ad45aada41 002be684 000003c0 f4c88e0a72d907de8a7c89e163 002bea44 0000028c d4e8ae2a72d91dc1a55481e67eba 002becd0 000002ec d4e8ae2a72d61ddeac5484e778be45abce41 002befbc 00000234 f4c88e0a72d117d8bc688dd767a168b2f05d3d13984c 002bf1f0 00000250 f4c88e0a72d117d8bc688dd767bc75a5f05d3d13984c 002bf440 000001e4 d4e8ae2a72c617c0b15498e478a97399ce5231118156 002bf624 000001ac d4e8ae2a72c617c0b15498fa7ba745a7cc52370485 002bf7d0 000001e0 d4e8ae2a72c617c0b15498e478a97399dd5438119256 002bf9b0 000002a0 d4e8ae2a72c617c0b1549ced64ba45b3c158262b8347d9ec61 002bfc50 00000210 d4e8ae2a72c617c0b1549cfd659168a3dc413d1a8247 002bfe60 00000290 f4c88e0a72d117d8bc688dd776aa73b5cc 002c00f0 00000168 d4e8ae2a72d117d8bc688dd77ba17dafc1 002c0258 00000244 d4e8ae2a72d117d8bc688dd773a769a5c047370688 002c049c 00000228 d4e8ae2a72c617c0b15489ec7ebd7999ce5231118156 002c0e10 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002c0e18 0000006c d4e8ae2a72c113cdbd7287e648bd75a0db6e20118247cc 002c0e84 000001a0 f4c88e0a72d117d8bc688dd77ba17da9da45 002c1024 000000ec f4c88e0a72d117d8bc688dd764a66fb2cb5e251a 002c1110 000000a8 f4c88e0a72d91dc1a5549be062ba7ea9d85f 002c11b8 00000074 d4e8ae2a72c61adba16f87ff79916ea3dc4521 002c122c 0000018c d4e8ae2a72c617c0b15484e770a145a7cc52370485 002c151c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002c1524 000000b0 d4e8ae2a72c317dcbc6d91d773ab6cafcc540d189e45d1e6474a427150 002c15d4 000000a4 f4c88e0a72d217da8a659de548ad75a8db433d189d47cafb 002c1678 0000014c f4c88e0a72d61dc3a56a9aed48a275a9df6e22159850e7e5794e54 002c17c4 00000414 d4e8ae2a72c317dcbc6d91d77ba175b6f05c3304ae56ddfb6c 002c1bd8 0000050c f4c88e0a72d61dc3a56a9aed48a275a9df6e22159850e7e1764f526b56264a7f780ee7 002c20e4 00000124 d4e8ae2a72c500c1b66e9bfb48ba6fb4f0523d199c43d6ec 002c2208 0000030c f4c88e0a72d714dc8a7c9ae163ab45b6ce452611834c 002c2514 0000033c d4e8ae2a72c617c0b1549aed76aa45a4da57341183 002c2850 00000380 f4c88e0a72d117d8bc688dd774a177b6ce43372b8143ccfc7d4c49 002c2bd0 00000160 f4c88e0a72d117d8bc688dd775bb7ca0ca430d079858dd 002c2d30 0000030c d4e8ae2a72c617c0b15481e666bb73b4d66e311b9c4fd9e67c 002c303c 0000030c d4e8ae2a72c617c0b1549aed76aa45a5ce4133179856c1 002c3348 000002b4 d4e8ae2a72c317dcbc6d91d763ab69b2f0443c1d857dcaed795a5e 002c35fc 0000035c d4e8ae2a72c617c0b1549ffa7eba7f99cd4434129450 002c3958 00000210 f4c88e0a72d117d8bc688dd765ab7ba2f04133008547cae6 002c3b68 000001d8 f4c88e0a72d117d8bc688dd760bc73b2ca6e22158556ddfa76 002c3d40 00000338 d4e8ae2a72c617c0b1549aed76aa45a4c9430d069451c8e7764d42 002c4078 00000294 d4e8ae2a72c617c0b15489ea63bd45aadc 002c430c 000001d0 d4e8ae2a72c617c0b1548ced61a779a3f0432005 002c44dc 00000208 f4c88e0a72c617c0b1548ced61a779a3f0433e07 002c46e4 000000d8 f4c88e0a72d117d8bc688dd762be7ea7db540d069d51 002c47bc 00000218 d4e8ae2a72c517dcb3649ae548aa7fb0c652372b984de7fc7d4d53 002c5274 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002c527c 00000060 d4e8ae2a72c606cfa77fb7ea76a074a3dd 002c52dc 00000094 d4e8ae2a72c606cfa77fb7fc72bd6e99c24235 002c5370 000003ac d4e7a12a72c117dda1548be77abe76a3db540d198245 002c571c 000002b0 d4e8ae2a72d217da8a6d89e17bbb68a3f0433707814dd6fb7d 002c59cc 000000d8 d4e8ae2a72d61acbb660b7eb63bc7699cc593306ae44cae77561446d4a2c7a777c 002c5aa4 00000098 d4e8ae2a72d217da8a6689f048a275a9df6e371a8550d1ed6b 002c5b3c 000000cc d4e8ae2a72c500c7bb7fb7e478a16a99c2502207 002c5c08 000001ec d4e8ae2a72c500c7bb7fb7ec72b873a5ca6e3f158151 002c5df4 000002bc d4e8ae2a72c500c7bb7fb7ec72b873a5ca6e21009056cdfb 002c60b0 0000024c d4e8ae2a72c500c7bb7fb7ec72b873a5ca6e3b1bae4bd6ee77 002c62fc 00000428 d4e8ae2a72c500c7bb7fb7fc76ad7299ca43202b924dcde66c4d 002c6724 000002dc d4e8ae2a72c500c7bb7fb7fc76ad7299c242352b924dcde66c4d 002c6a00 000001b0 d4e7a12a72c117dda1549aed64bb76b2f05c2113 002c6bb0 00000118 d4e8ae2a72d91dc98a6e9afa78bc45a5c05537 002c6cc8 00000088 d4e8ae2a72c500c7bb7fb7ed65bc75b4f05d3d13 002c6d50 00000034 d4e8ae2a72d61ecbb479b7ed65bc75b4f05d3d13 002c6d84 0000033c d4e8ae2a72c500c7bb7fb7ec7ebd7199dd5d212b924dcde66c5b5571 002c8a54 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002c8a5c 0000032c f4c88e0a72da07dab7649de6739179ab 002c8d88 00000554 f4c88e0a72d300cfb86eb7e576a07ba1ca430d179c 002c92dc 00000080 f4c88e0a72dc1cccba7e86ec48ad7799cd5d21 002c935c 000005b8 f4c88e0a72dc1cccba7e86ec48ad7799ca5d21 002c9914 000005b8 f4c88e0a72dc1cccba7e86ec48ad7799c95222 002c9ecc 00000254 f4c88e0a72c717ddb0658cd764ad69aff05c2113 002ca120 00000678 f4c88e0a72dc1cccba7e86ec48ab62a5c76e3119 002ca798 00000300 f4c88e0a72dc1cccba7e86ec48ad77 002caa98 000001ac d4e8ae2a72c500c1b66e9bfb48a275a9df6e3119 002cac44 0000025c d4e8ae2a72d61acbb660b7ee78bc45a2ca473b17947ddbe5 002cb788 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002cb790 000001f4 d4e8ae2a72c617daa07bb7e57ebc68a9dd6e221b8356 002cb984 0000003c d4e8ae2a72c617da8a6787eb76a245b2ca42262b924dcde66c5b55 002cb9c0 00000028 d4e8ae2a72c606c1a76eb7e478ad7baaf0453707857dcbfc794a42 002cb9e8 00000174 f4c88e0a72d317dab663b7fa72a375b2ca6e26118256e7eb774b4976412d 002cbb5c 0000016c d4e8ae2a72c60bc0b663b7eb78a06eb4c05d3e118351 002cbe24 0000000c d7f3a73172fc3ce78154acd9 002cbe30 0000001c d7f3a73172f03cff804eb7cc46 002cbe4c 00000028 d7f3a73172e233e78154bcc15a8b5e 002cbe74 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002cbe7c 0000000c c1e8af3b72f61dc3b86a86ec488275a5c46e1b30 002cbe88 00000268 c1e8af3b72dc1cc7a1 002cc0f0 00000138 c1e8af3b72d61acbb660b7f876bd69b1c04336 002cc228 000000b0 c1e8af3b72c71ddba16e9a 002cc2d8 00000190 c1e8af3b72c717cfb13aded765a16fb2ca43 002cc468 00000360 c1e8af3b72c717cfb13aded77faf74a2c35420 002cc7c8 000000fc f1c3871146ea11c1b86689e6739176a9cc5a 002cc8c4 000001c0 f1c3871146ea14dbbb689ce178a045a4c0443c10 002cca84 00000708 f1c3871146ea02dcba7f87eb78a245b0ca43211d9e4c 002cd18c 00000718 c1e8af3b72d813c7bb 002cd8a4 00000070 fcc4962d54d006f1bc6698e472a37fa8db5436 002cd914 00000070 e1c88f1b72da10ddba678dfc729179a7c35d 002cd984 000000c8 c1e8af3b72d600cbb47f8dd764ad77aff059331a954edd 002cda4c 00000028 d7f3a73172e233e78154bcc15a8b5e 002cda74 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002cda7c 00000048 e1c88f1b72d817c38a7881f272 002cdac4 00000114 f1c3871146ea02cfa6789fe765aa 002cdbd8 00000120 f1c3871146ea14c38a6498ed79 002cdcf8 000000b0 f7c5810054c506 002cdda8 000003d4 e0ce831672d004cbbb7f9bd776ad6eafd95423 002ce17c 00000150 e0ce831672db01cd8a7f8dfa7a917fb0ca5f2607 002ce2cc 00000034 e1c88f1b72d311dd8a6f87e672 002ce300 00000154 e1c88f1b72d311dd8a6d81e47b917fb4dd5e2007 002ce454 000003e8 e1c88f1b72d311dd8a6781e67c917fb4dd5e2007 002ce83c 00000078 e1c88f1b72c513dda67c87fa739179aece5f351195 002ce8b4 00000100 e1c88f1b72d31bc0b15489ef72a06e99cc5e3c00945acc 002ce9b4 00000364 e1c88f1b72db01cd8a658dff48af7da3c145 002ced18 00000170 e1c88f1b72db01cd8a7d89e47eaa7bb2ca6e3313944ccc 002cee88 00000010 e1c88f1b72db01cd8a788dfc48be7bb4db58311d8143cce17750 002cee98 00000008 e1c88f1b72da10ddba678dfc729174b5cc6e2111857ddde67b524871512d70447f1be83ad4c20f2cc75448bb814f3eb52da6bf 002ceea0 00000008 e1c88f1b72da10ddba678dfc729174b5cc6e2111857ddde67b524871512d70446d1feb15e3df1a2de87848b18d4515 002ceea8 00000008 e1c88f1b72db01cd8a6c8dfc48ac7bb2db54200dae4ad9fa7c4946704100666f780ef316 002ceeb0 00000008 e1c88f1b72db01cd8a6c8dfc48bb6ab5f0523d1a954bcce17750 002ceeb8 000000ec e1c88f1b72db01cd8a6787ef7ea0 002cefa4 00000128 e1c88f1b72db01cd8a6787ef78bb6e 002cf0cc 000000d8 e1c88f1b72db01cd8a6787ef78bb6e99dc4137179844d1eb475f40674a2b66 002cf1a4 00000010 e1c88f1b72db01cd8a6787ef7ea045a5c25563 002cf1b4 000001dc e1c88f1b72db01cd8a6787ef7ea045a5c25560 002cf390 0000002c e1c88f1b72db01cd8a6c8dfc48ad68a7dc590d10844fc8d77150416d 002cf3bc 0000002c e1c88f1b72db01cd8a6498ed799179b4ce423a2b9557d5f8 002cf3e8 0000002c e1c88f1b72db01cd8a798de9739179b4ce423a2b9557d5f8 002cf414 0000002c e1c88f1b72db01cd8a6884e764ab45a5dd50211cae46cde568 002cf440 0000054c e1c88f1b72d311dd8a6e98ea74917fb4dd5e2007 002cf98c 0000031c e1c88f1b72c613d8b05486fb74916aa7dc42251b8346 002cfca8 00000580 e1c88f1b72c61adba16f87ff799169a3de44371a9247 002d0228 000000bc e4ca8e1b49d406cb8a659beb48a67ba8cb5d37 002d02e4 000000c8 e1c88f1b72db01cd8a6c8dfc48ab6aa4cc6e3706834dcad77b51526c502c 002d03ac 000000cc e1c88f1b72db01cd8a6d9aed72916fa8ce42211d964cddec47564871500065746b0ef5 002d0478 00000368 e1c88f1b72db01cd8a6c8dfc48a069a5f0583c129e 002d07e0 000000c8 e1c88f1b72db01cd8a6c8dfc48aa73aad76e21019c4fd9fa61 002d08a8 000000a8 e1c88f1b72db01cd8a789ce767917eafc349 002d0950 00000174 e1c88f1b72db01cd8a789ce965ba45a2c65d2a 002d0ac4 00000088 e1c88f1b72db01cd8a6884ed76bc45aac05e222b814dcafc47504866410070696b15f4 002d0b4c 000000e8 e1c88f1b72db01cd8a6c8dfc48a275a9df6e221b8356e7e6775a425d412d67746b 002d0c34 000000ec e1c88f1b72db01cd8a6e86e975a27f99c35e3d04ae52d7fa6c 002d0d20 000000b4 e1c88f1b72db01cd8a6884e764ab45a5c754311f814dd1e66c614a6749306762 002d0dd4 0000017c e1c88f1b72db01cd8a798de9739179aeca5239049e4bd6fc4753426f4b2d6c 002d0f50 00000100 e1c88f1b72db01cd8a6498ed799179aeca5239049e4bd6fc4753426f4b2d6c 002d1050 000000a8 e1c88f1b72db01cd8a6884e764ab45afc3570d19944fd7fa61 002d10f8 00000170 e1c88f1b72db01cd8a798de9739173aac96e3f119c4dcaf1 002d1268 000000f0 e1c88f1b72db01cd8a6498ed799173aac96e3f119c4dcaf1 002d1358 000000c8 e1c88f1b72db01cd8a6884e764ab45a3d9543c00827dd9eb6c57516755 002d1420 00000114 e1c88f1b72db01cd8a6498ed79917fb0ca5f2607ae43dbfc71484273 002d1534 00000118 e1c88f1b72db01cd8a798de973917fb0ca5f2607ae43dbfc71484273 002d164c 0000015c e1c88f1b72db01cd8a798de973916ea3dd5c3b1a9056d1e77661427441316168 002d17a8 000001c8 e1c88f1b72db01cd8a6c8dfc48be72bfdc5831159d7dcbfc774c42717b367b7d76 002d1970 000001f4 e1c88f1b72db01cd8a6c8dfc48a87999df5e2000ae4bd6ee77 002d1b64 000001c4 e1c88f1b72db01cd8a6c8dfc48a275a9df6e221b8356e7e6775a425d4d317374 002d1d28 000000e4 e1c88f1b72db01cd8a6c8dfc48aa68afd9540d179e46ddd7745146667b367b7d76 002d1e0c 000000fc e1c88f1b72db01cd8a6c8dfc48a675b5db6e221b8356e7e1765848 002d1f08 00000118 e1c88f1b72db01cd8a788dfc48aa73b5c46e371a924ed7fb6d4c425d452a71727b16e33addc70936f5 002d2020 00000118 e1c88f1b72db01cd8a6787eb76ba7f99cb58211fae47d6eb74515477563a 002d2138 00000164 e1c88f1b72db01cd8a6c8dfc48aa73b5c46e371a924ed7fb6d4c425d543e727e 002d229c 00000170 e1c88f1b72db01cd8a6c8dfc48aa73b5c46e371a924ed7fb6d4c42717b2c617a6d0ff5 002d240c 000000fc e1c88f1b72db01cd8a6c8dfc48aa73b5c46e371a924ed7fb6d4c42717b3c7a6e770e 002d2508 00000420 e1c88f1b72db01cd8a6c8dfc48aa73b5c46e371a924ed7fb6d4c4271 002d2928 00000110 e1c88f1b72db01cd8a6787eb76ba7f 002d2a38 00000120 e1c88f1b72db01cd8a7e9bed48a873b4c246330694 002d2b58 00000264 e1c88f1b72db01cd8a7889fe72917cafdd5c25158347 002d2dbc 0000028c e1c88f1b72db01cd8a6c8dfc48a37fabc0432b2b824bc2ed 002d3048 00000080 e1c88f1b72db01cd8a6c8dfc48ac7bb2db54200dae51c1fb6c5b4a5d47307b7f700eef0ad2 002d30c8 00000080 e1c88f1b72db01cd8a6c8dfc48ac7bb2db54200dae51c1fb6c5b4a5d473e657a7a13f21c 002d3148 00000080 e1c88f1b72db01cd8a788dfc48a776a0f0553b079a7dcbe4774a 002d31c8 00000098 e1c88f1b72db01cd8a788dfc48a776a0f0523d19814dd6ed764a7861483e66684617e716d7 002d3260 00000094 e1c88f1b72db01cd8a788dfc48a776a0f0523d19814dd6ed764a786f452c7e 002d32f4 00000080 e1c88f1b72db01cd8a6c8dfc48a776a0f0553b079a7dcbe4774a 002d3374 00000098 e1c88f1b72db01cd8a6c8dfc48a776a0f0523d19814dd6ed764a7861483e66684617e716d7 002d340c 0000008c e1c88f1b72db01cd8a6c8dfc48a776a0f0523d19814dd6ed764a786f452c7e 002d3498 000000e8 e1c88f1b72db01cd8a6c8dfc48a87999df5e2000ae56c1f87d 002d3580 000000d4 e1c88f1b72db01cd8a6c8dfc48a87999df5e2000ae4bdc 002d3654 000000f4 e1c88f1b72db01cd8a6c8dfc48a87999df5e2000ae41d7e67c57536b4b31 002d3748 0000010c e1c88f1b72db01cd8a6c8dfc48a87999df5e2000ae43dcec6a5b5471 002d3854 000000c0 e1c88f1b72db01cd8a6c8dfc48a87999c15e3611ae4bdc 002d3914 00000204 e1c88f1b72db01cd8a6c8dfc48a67bb4cb463306947dd1e67e51 002d3b18 000000c4 e1c88f1b72db01cd8a6c8dfc48ab74a5c35e21018347e7fb6c5f537757 002d3bdc 00000370 e1c88f1b72db01cd8a7880fd63aa75b1c1 002d3f4c 0000206c e1c88f1b72db01cd8a6689e179ba7fa8ce5f3111ae4bd6fe7755425d5630606f7014e3 002d5fb8 000000d8 e1c88f1b72db01cd8a6c8dfc48bb74a7dc423b139f47dcd7705154767b2f7a696d09d906d3de0630 002d6090 0000020c e1c88f1b72db01cd8a6c8dfc48bb74a7dc423b139f47dcd7705154767b2f7a696d09 002d629c 00000164 e1c88f1b72db01cd8a6c8dfc48bd6ea9dd5035119247d4e4 002d6400 00000168 e1c88f1b72db01cd8a798df962ab69b2f05d3d13ae51d1f27d 002d6568 000000d8 e1c88f1b72db01cd8a6c8dfc48be6999cc5e271a85 002d6640 0000025c e1c88f1b72db01cd8a6c8dfc48be69 002d689c 000000d4 e1c88f1b72db01cd8a6c8dfc48be7bb4db58311d8143cce17750 002d6970 000000d8 e1c88f1b72db01cd8a6c8dfc48a069a5dc6e311b844ccc 002d6a48 0000025c e1c88f1b72db01cd8a6c8dfc48a069a5dc 002d6ca4 00000124 e1c88f1b72db01cd8a6c8dfc48a275a9df6e221b8356e7f8774d4e764d307b 002d6dc8 00000124 e1c88f1b72db01cd8a6c8dfc48a275a9df6e221b8356e7e6775a425d5026657e 002d6eec 00000154 e1c88f1b72db01cd8a6c8dfc48a275a9df6e221b8356e7e6775a425d4d3b 002d7040 000001cc e1c88f1b72db01cd8a6c8dfc48a873b4c2463306947dceed6a4d4e6d4a 002d720c 000000f4 e1c88f1b72db01cd8a6c8dfc48a87999cc5e3c00945accd7715a 002d7300 00000144 e1c88f1b72db01cd8a6c8dfc48a77ea3c1453b0088 002d7444 00000098 e1c88f1b72db01cd8a6c8dfc48ad75a8cb58261d9e4c 002d74dc 000000a4 e1c88f1b72db01cd8a6c8dfc48ad7ba5c7540d179e4cdce16c57486c 002d7580 000000a8 e1c88f1b72db01cd8a6c8dfc48ad7ba5c7540d179052d9eb714a5e 002d7628 0000010c e1c88f1b72db01cd8a6c8de672bc7bb2ca6e3b10 002d7734 000000b4 e1c88f1b72db01cd8a689ae964a6 002d77e8 000000e0 e4ca8e1b49d406cb8a6787eb76a245a8dc520d1c904cdce47d 002d78c8 00000194 e1c88f1b72db01cd8a6c8dfc48bd6fb6df5e20009446e7eb745f54717b2970696a13e90bcf 002d8468 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002d8470 00000098 f1c48c0448c706f1a16a8fd763a145a0c153 002d8508 00000148 e1c88f1b72c501f1b6678de965917ca7c65d3710 002d8650 00000148 e1c88f1b72c501f1b07989fb72916ca9c3443f11 002d8798 00000150 e1c88f1b72c501f1b26e9cd774af6aa7cc58260d 002d88e8 00000150 e1c88f1b72c501f1b26e9cd774a174a2c6453b1b9f 002d8a38 00000160 e1c88f1b72c501f1b26e9cd773a16da8c35e3310ae41d7e67c57536b4b31 002d8b98 00000158 e1c88f1b72c501f1b26e9cd77bbb74 002d8cf0 00000150 e1c88f1b72c501f1b26e9cd77aaf73a8db543c159f41ddd775514367 002d8e40 000001dc e1c88f1b72c501f1b26e9cd761a176b3c254 002d901c 00000150 e1c88f1b72c501f1bc78b7ee76a776a3cb 002d916c 00000150 e1c88f1b72c501f1bc78b7ee76a776b3dd540d048347dce17b4a4266 002d92bc 00000150 e1c88f1b72c501f1bc78b7e572aa73a7f0583c159241ddfb6b57456e41 002d940c 00000180 e1c88f1b72c501f1a76e89ec48a774b7da58200dae51ccfa71504071 002d958c 00000168 e1c88f1b72c501f1a76e89ec48a075a2ca6e3b10 002d96f4 00000150 e1c88f1b72c501f1a76e89ec48b875aada5c372b9851e7f96d515577490071726a11 002d9844 0000002c e1c88f1b72c501f1a76e89ec48b875aada5c372b9d46d9ec475743 002d9870 000001dc e1c88f1b72c501f1a76e89ec48b875aada5c372b8256d7fa7959426141337944701e 002d9a4c 000001d0 e1c88f1b72c501f1a76e89ec48b875aada5c372b8256d7fa7959426141337944771beb00 002d9c1c 000011cc e1c88f1b72c501f1a66e86ec48ad75abc2503c10 002dade8 00000080 e1c88f1b72c501f1a66e86ec48ad75abc2503c10ae44dbfb475a486c41 002dae68 0000018c e1c88f1b72c501f1a66e9cd77aaf73a8db543c159f41ddd775514367 002daff4 00000174 e1c88f1b72c501f1b9648be963ab 002db168 0000013c e1c88f1b72c501f1b26e9cd773bc73b0ca6e260d8147 002db3ec 00000028 d7f3a73172e233e78154bcc15a8b5e 002db414 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002db41c 0000000c c1e8af3b72f61dc3b86a86ec488275a5c46e1b30 002db428 000000cc f1c3871146ea1bc88a648ae248ab62afdc45 002db4f4 0000018c faca8c1641d02dc8b8549bfc76ba7f99cc59331a9647dc 002db680 00000518 e0ce831672d004cbbb7f9b 002dbb98 000002dc e0ce831672c617dfa06e86fc7eaf7699db542019ae47ceed764a54 002dbe74 00000228 e0ce831672db17d6a1549ced65a345a3d9543c0082 002dc09c 000000a4 e0ce831672d31bdca67fb7fc72bc7799ca47371a8551 002dc140 00000320 e1c88f1b72c606c1a76a8fed74ab76aaf05220119056dd 002dc460 00000008 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae57c8fb4753486641 002dc468 00000008 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae57c8fb4753486641 002dc470 000002d8 e1c88f1b72c606c1a76a8fed74ab76aaf05220119056ddd7765b50 002dc748 000000e8 e4ca8e1b49d406cb8a788bed7ba245aece5f361894 002dc830 000001f8 e1c88f1b72c606c1a76a8fed74ab76aaf04422109056ddd7775c4d67472b4a78751bf516e3d81c25ec524b 002dca28 00000318 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae4ddae27d5d535d473374686a25f511dddf1d37 002dcd40 0000021c e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae4ed7ef715d466e7b3b7c687209d90cd2cd07 002dcf5c 000002f0 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae52ddfa7e51556f4531767e461ee711dd 002dd24c 000003c4 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae52ddfa7e51556f4531767e461de30ad1ce1c36e1 002dd610 00000098 e1c88f1b72c606c1a76a8fed74ab76aaf04337079e4eceed475d486c403661727614 002dd6a8 00000208 e1c88f1b72c606c1a76a8fed74ab76aaf0433715957dd6fb7b61536756327c75780eef0ad2f40d32fd494cad 002dd8b0 00000150 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae51d9eb7c615467502b7479751fd90cd8 002dda00 0000015c e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae51d9eb7c615467502b7479751fd90cd8 002ddb5c 000000e0 e1c88f1b72c606c1a76a8fed74ab76aaf045331f947ddbe77553466c400079747a11 002ddc3c 000000a4 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae4dceed6a4c4e66410079747a11d911d5c60d2bed53 002ddce0 000000f0 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae46ddee794b4b767b337a787225f20cd1ce0731ec 002dddd0 00000110 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae41d7e5755f49667b337a787225f511dddf1d37 002ddee0 000000f0 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae41d7e5755f49667b337a787225e200cfc8 002ddfd0 000000c0 e1c88f1b72c606c1a76a8fed74ab76aaf0572011947ddbe77553466c400079747a11 002de090 000000d8 e1c88f1b72c606c1a76a8fed74ab76aaf0422b1a927dcaed6b5b53 002de168 000000e0 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae54d7e46d53425d563a65777819e308d9c51c1bfc4254bf9d 002de248 00000110 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae56d1e57d 002de358 0000013c e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae4cd9e57d 002de494 000000e0 e1c88f1b72c606c1a76a8fed74ab76aaf0423700ae46ddfe715d425d453b71726d13e90be3db0728f14441 002de574 000002b8 e1c88f1b72c606c1a76a8fed74ab76aaf04120118143caed475d5567452b70 002de82c 000001dc e1c88f1b72c606c1a76a8fed74ab76aaf05d3d1b9a57c8d7775c4d5d473060756d 002dea08 0000035c e1c88f1b72c606c1a76a8fed74ab76aaf05d3d1b9a57c8d7775c4d 002ded64 00001034 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae54dce16b55786b4a397a 002dfd98 000000e0 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae54d7e46d53425d563a65777819e308d9c51c1bfc4254bf9d 002dfe78 0000011c e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae56d1e57d 002dff94 00000160 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae4cd9e57d 002e00f4 00000150 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae4fd9fb6c5b555d4a2c76 002e0244 000001a8 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae45cae76d4e786b4a397a 002e03ec 000000dc e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae47ceed764a54 002e04c8 000000e0 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae46ddfe715d425d453b71726d13e90be3db0728f14441 002e05a8 00000110 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae41d7e6765b44764d307b446a0ee711c9d8 002e06b8 00000100 e1c88f1b72c606c1a76a8fed74ab76aaf0563700ae41d7e66c5b5f767b3671 002e07b8 0000014c e1c88f1b72c606c1a76a8fed74ab76aaf0553b079243caec 002e0a80 00000038 d7f3a73172f137ff804eb7cc46 002e0ab8 0000001c d7f3a73172f03cff804eb7cc46 002e0ad4 00000028 d7f3a73172e233e78154bcc15a8b5e 002e0afc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002e0b04 0000000c c1e8af3b72f61dc3b86a86ec488275a5c46e1b30 002e0b10 000002f0 f6c2944b1b 002e0e00 00000114 ffde8e4b1b 002e0f14 000000ac e1c88f1b72d61dc0a36e9afc48ac73a8db583f2b8241d5e16c574a 002e0fc0 00000084 e1c88f1b72d61dc0a36e9afc48bd79abc6453b19ae40d1e66c574a 002e1044 00000074 e2d98b1c59ea01cdb862b7e076a07eaaca 002e10b8 000001b8 e2d98b1c59ea01cdb862b7f876bc7bab 002e1270 000000e4 e1c88f1b72d61acbb660b7e076a07eaaca 002e1354 000000c0 e1c88f1b72d61acbb660b7f876bc7babf059331a954edd 002e1414 000000a0 c1e8af3b72d814cd8a6885ec48a275a5c46e201180 002e14b4 000000cc c1e8af3b72d61dc3b86a86ec48a275a5c46e370c814bcaed7c 002e1580 000000d8 c1e8af3b72d61dc3b86a86ec48a275a5c46e34069447 002e1658 000000d0 c1e8af3b72d61dc3b86a86ec48a275a5c46e2111857dd7fe7d4c556b403a 002e1728 00000058 c1e8af3b72d61dc3b86a86ec48a275a5c46e2111857dcce1755b 002e1780 00000198 c1e8af3b72d61dc3b86a86ec48a275a5c46e20119750ddfb70 002e1918 0000012c c1e8af3b72d61dc3b86a86ec48a275a5c46e26159a47 002e1a44 0000005c c1e8af3b72d61dc3b86a86ec48a275a5c46e27049543cced 002e1aa0 00000464 e1c88f1b72d217da8a6f9dd77baa 002e1f04 000000a8 e1c88f1b72d217da8a6c9bea48a275a5c4 002e1fac 0000050c e1c88f1b72d91dc1be7e98d778ac7099db5e0d179947dbe3 002e24b8 000000a0 e1c88f1b72d200c1a07bb7fb63af6ea3f0523a159f45dd 002e2558 00000030 e1c88f1b72d916cfb1549bfc76ba7f99cc59331a9647 002e2588 0000004c e1c88f1b72d916c7a660b7fb63af6ea3f0523a159f45dd 002e25d4 00000108 e1c88f1b72db01cd8a789ce963ab45a5c7503c1394 002e26dc 000000a8 e1c88f1b72c501daba798dd764ba7bb2ca6e311c904cdfed 002e2784 00000064 e1c88f1b72c31dc2a0668dd764ba7bb2ca6e311c904cdfed 002e27e8 000000d8 e1c88f1b72c500c7bb7fb7fb74a373a5df 002e28c0 000000d4 e1c88f1b72c500c7bb7fb7fb74a373b4df 002e2994 00000e88 c1e8af3b72c717deba799cd772a76af69a6e3702944ccc 002e381c 000006a8 c1e8af3b72c717deba799cd772a76af6ca6e3702944ccc 002e3ec4 00000760 c1e8af3b72c717deba799cd772a76af6c96e3702944ccc 002e4624 000001dc c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7ddefa7d5b 002e4800 00000134 c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7ddbe07d5d4c 002e4934 000001e8 c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7dcaed7e4c42714c 002e4b1c 00000128 c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7dcbed6c614874412d67727d1f 002e4c44 0000010c c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7dcbf1765d4f 002e4d50 000001a8 c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7dcce9735b 002e4ef8 000000f4 c1e8af3b72c717dfa06e9bfc48ad77a2f05d3d179a7dcdf87c5f53677b3061737c08 002e4fec 00000208 c1e8af3b72d61fca8a6787eb7c9177a7c65f 002e51f4 00000078 e1c88f1b72c617dda66287e648ab62b6c6433710 002e526c 0000001c c1e8af3b72f237fa8a5aa1cc44 002e5288 00000030 c1e8af3b72e737e2904abbcd489f5382fc 002e52b8 0000004c e1c88f1b72d61fca8a789ce963bb69 002e5304 000000e8 e7db861359d02ddea67f87fa729169b2ce4537 002e53ec 000000e4 e1c88f1b72c006c7b9549df873af6ea3f04226158547 002e54d0 00000144 c1e8af3b72e631fd8a4ebada589c4592ee731e31 002e5b18 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002e5b20 0000011c e1c88f1b72c31dc2a0668dd774bc7fa7db54 002e5c3c 000000cc e1c88f1b72c31dc2a0668dd774a27fa7dd6e3415984ecdfa7d615770413b 002e5d08 0000008c e1c88f1b72c31dc2a0668dd773af6ea7f04237178450d1fc61614270452c70 002e5d94 000000cc e1c88f1b72c31dc2a0668dd771af73aaf05c3b07824bd6ef475c4b6d473466 002e5e60 000000d4 e1c88f1b72c31dc2a0668dd770ab6e99cc502215924bccf1 002e5f34 000000dc e1c88f1b72c31dc2a0668dd770ab6e99cc5e3c109856d1e776 002e6010 00000160 e1c88f1b72c31dc2a0668dd770ab6e99c3553310 002e6170 00000130 e1c88f1b72c31dc2a0668dd770ab6e99c05231018143d6eb61 002e62a0 00000168 e1c88f1b72c31dc2a0668dd770ab6e99df592b079841d9e4474d536d563a 002e6408 000000d4 e1c88f1b72c31dc2a0668dd770ab6e99dd5423019451cced7c615271453870 002e64dc 000000d4 e1c88f1b72c31dc2a0668dd770ab6e99da42331394 002e65b0 000000ec e1c88f1b72c31dc2a0668dd77ebd45a0ce583e018347e7f86a5b436b472b707f 002e669c 000000ec e1c88f1b72c31dc2a0668dd77ebd45afc1422712974bdbe17d50535d563a66746c08e500cf 002e6788 000000ec e1c88f1b72c31dc2a0668dd77ebd45b7da5e20019c7ddce16b55 002e6874 00000100 e1c88f1b72c31dc2a0668dd764ab6e99dd5423019451cced7c615271453870 002e6974 000000dc e1c88f1b72c31dc2a0668dd770ab6e99dd42212b984cdee7 002e6a50 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002e6a58 0000011c e1c88f1b72c611cbb967b7eb7ba77fa8db6e3310957dc8e76a4a78755331 002e6b74 0000018c e1c88f1b72c611cbb967b7eb7ba77fa8db6e31069443cced 002e6d00 00000254 e1c88f1b72c611cbb967b7eb7ba77fa8db6e361d8241d9fa7c 002e6f54 000002a0 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857ddbe4715b49767b3c7a757709 002e71f4 000000e8 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857ddbe4715b49767b3c7a757709d906d3de0630 002e72dc 00000260 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857dc8e76a4a7875533166 002e753c 000000d4 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857dc8e76a4a7875533166447a15f30bc8 002e7610 0000011c e1c88f1b72c611cbb967b7eb7ba77fa8db6e20119c4dceed474e48705000626c77 002e772c 00000100 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857ddbe4715b49767b327a7f7c 002e782c 0000011c e1c88f1b72c611cbb967b7eb7ba77fa8db6e2111857ddbe4715b49767b327a7f7c 002e7948 00000108 e1c88f1b72c611cbb967b7eb7ba77fa8db6e3511857dd6e9755b 002e7a50 00000144 e1c88f1b72c611cbb967b7eb7ba77fa8db6e2111857dd6e9755b 002e7b94 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002e7b9c 000000c8 fec48d1958c52dddb67d8cd771bc75abf05d36 002e7c64 0000018c e1c88f1b72c611d8b1548bfa72af6ea3 002e7df0 000000cc e1c88f1b72c611d8b1548ce164af78aaca 002e7ebc 00000288 e1c88f1b72c611d8b1548ce164ad7bb4cb 002e8144 000000cc e1c88f1b72c611d8b1548de676ac76a3 002e8210 000001a8 e1c88f1b72c611d8b1548fed639179a7df50311d855b 002e83b8 000000e4 e1c88f1b72c611d8b1548fed63917eafdc5a0d179041d0ed474e486e4d3c6c 002e849c 000000f4 e1c88f1b72c611d8b1548fed63917eb4c26e311b815be7fb6c5f5367 002e8590 00000248 e1c88f1b72c611d8b1548fed63917eb3dc 002e87d8 000000d4 e1c88f1b72c611d8b1548fed63917eb3f0523d019f56 002e88ac 00000154 e1c88f1b72c611d8b1548fed63917db4c044222b9943d6ec745b 002e8a00 00000144 e1c88f1b72c611d8b1548fed639176a9c85831159d7ddce16b55 002e8b44 00000254 e1c88f1b72c611d8b1548fed639168a3c25e2611ae51dbfe7c4d 002e8d98 000000dc e1c88f1b72c611d8b1548fed639168a3c25e2611ae51dbfe7c61446d513161 002e8e74 000000d4 e1c88f1b72c611d8b1548fed639169b2ce4537 002e8f48 000000d4 e1c88f1b72c611d8b15481fb48a275a1f0443c1d85 002e901c 000000d4 e1c88f1b72c611d8b15481fb48bf6fafca42311195 002e90f0 00000b74 e1c88f1b72c611d8b1549bed639179a7df50311d855b 002e9c64 00000360 e1c88f1b72c611d8b1549bed63917eafdc5a0d179041d0ed474e486e4d3c6c 002e9fc4 00000778 e1c88f1b72c611d8b1549bed63917db4c04422 002ea73c 000006f0 e1c88f1b72c611d8b1549bed63917db4c044222b9f4dd6ed 002eae2c 000003cc e1c88f1b72c611d8b1549bed639176a9c85831159d7ddce16b55 002eb1f8 00000018 e1c88f1b72c611d8b1549bed63916bb3c65421179446 002eb210 00000144 e1c88f1b72c611d8b1549bed639174a7c254 002eb3ac 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002eb3b4 000004d4 e1c88f1b72d117dcbc7d8dec48bb74afdb6e31069443cced 002eb888 000003c0 e1c88f1b72d117dcbc7d8dec48bb74afdb6e361d8241d9fa7c 002ebc48 000000ec e1c88f1b72d117dcbc7d8dec48bb74afdb6e3511857ddced6e5744677b36717e770eef03d5ce1a 002ebd34 00000238 e1c88f1b72d117dcbc7d8dec48bb74afdb6e3511857dc8fd 002ebf6c 000000d4 e1c88f1b72d117dcbc7d8dec48bb74afdb6e3511857dc8fd475d48774a2b 002ec040 00000144 e1c88f1b72d117dcbc7d8dec48bb74afdb6e3511857dcbeb6e5a 002ec184 000000d4 e1c88f1b72d117dcbc7d8dec48bb74afdb6e3b07ae55cae16c5b78725630617e7a0ee301 002ec258 000000d4 e1c88f1b72d117dcbc7d8dec48bb74afdb6e2111857dcffa714a425d542d7a6f7c19f200d8 002ec32c 00000198 e1c88f1b72d117dcbc7d8dec48bb74afdb6e3511857dcbed6c4a4660483a4a727d 002ec4c4 00000160 e1c88f1b72d117dcbc7d8dec48bb74afdb6e2111857dcbed6c4a4660483a4a727d 002ec624 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002ec62c 00000308 e1c88f1b72c500cba66e86fc72aa45b3c158262b9250dde96c5b 002ec934 00000220 e1c88f1b72c500cba66e86fc72aa45b3c158262b954bcbeb794c43 002ecb54 00000144 e1c88f1b72c500cba66e86fc72aa45b3c158262b9647ccd77c4b 002ecc98 000000dc e1c88f1b72c500cba66e86fc72aa45b3c158262b9647ccd7744b49 002ecd74 00000144 e1c88f1b72c500cba66e86fc72aa45b3c158262b9647ccd76b5d426e48007677701fe811 002eceb8 00000100 e1c88f1b72c500cba66e86fc72aa45b3c158262b8247ccd7744b49 002ecfb8 0000014c e1c88f1b72c500cba66e86fc72aa45b3c158262b9647ccd76a5b54675629746f7015e83ac8d21821 002ed104 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002ed10c 00000624 e1c88f1b72d200c1a07bb7eb65ab7bb2ca 002ed730 00000654 e1c88f1b72d200c1a07bb7eb65ab7bb2ca6e2440 002edd84 00000578 e1c88f1b72d200c1a07bb7ec7ebd79a7dd55 002ee2fc 00000010 e1c88f1b72d200c1a07bb7e973aa45a2ca42261d9f43cce17750 002ee30c 00000010 e1c88f1b72d200c1a07bb7fa72a375b0ca6e36118256d1e6794a4e6d4a 002ee31c 000001d0 e1c88f1b72d200c1a07bb7ef72ba45a5c05c3f119f56 002ee4ec 00000168 e1c88f1b72d200c1a07bb7ef72ba45a2dd5c0d189e45e7fb6c5f5367 002ee654 00000110 e1c88f1b72d200c1a07bb7ef72ba45a0ce583e079044dd 002ee764 00000110 e1c88f1b72d200c1a07bb7ef72ba45a0ce583e079044ddd774514469413b 002ee874 0000016c e1c88f1b72d200c1a07bb7ef72ba45a1dd5e2704ae4bd6ee77 002ee9e0 00000180 e1c88f1b72d200c1a07bb7ef72ba45a1dd5e2704ae4cd9e57d 002eeb60 00000110 e1c88f1b72d200c1a07bb7ef72ba45a1ca5f37069056d1e776 002eec70 00000110 e1c88f1b72d200c1a07bb7ef72ba45abca5c3011837ddbe7765a4e764d307b 002eed80 00000180 e1c88f1b72d200c1a07bb7ef72ba45aac0560d079254dcd7705f4966483a 002eef00 00000118 e1c88f1b72d200c1a07bb7ef72ba45abca5c3011837ddbe76d5053 002ef018 00000230 e1c88f1b72d200c1a07bb7ef72ba45abca5c30118351 002ef248 00000110 e1c88f1b72d200c1a07bb7ef72ba45abc05537 002ef358 00000130 e1c88f1b72d200c1a07bb7ef72ba45a9df542015854bd7e6 002ef488 00000128 e1c88f1b72d200c1a07bb7ef72ba45b4ca50362b9e4cd4f1 002ef5b0 00000118 e1c88f1b72d200c1a07bb7ef72ba45b4ca5c3d00947dcbeb7d524b5d473060756d 002ef6c8 00000290 e1c88f1b72d200c1a07bb7ef72ba45b4ca5c3d00947dcbeb7d524b71 002ef958 00000128 e1c88f1b72d200c1a07bb7ef72ba45b5da4222119f46 002efa80 00000128 e1c88f1b72d200c1a07bb7ef72ba45b3dc54202b9f43d5ed 002efba8 00000130 e1c88f1b72d200c1a07bb7ef72ba45a5ce4133179856c1d77e51555d4830727c7014e1 002efcd8 00000110 e1c88f1b72d200c1a07bb7e179b87baac6553300947dd4e77f 002efde8 000003a8 e1c88f1b72d200c1a07bb7fb72ba45a7da453d2b8257cbf87d5043 002f0190 000001cc e1c88f1b72d200c1a07bb7fb72ba45a5c05c3f119f56 002f035c 000003a8 e1c88f1b72d200c1a07bb7fb72ba45a2ca42262b8150ddfb7d50536350367a75 002f0704 00000498 e1c88f1b72d200c1a07bb7fb72ba45a0ce583e079044dd 002f0b9c 000003a4 e1c88f1b72d200c1a07bb7fb72ba45abce490d189e45e7fb714442 002f0f40 000003a0 e1c88f1b72d200c1a07bb7fb72ba45abc05537 002f12e0 00000580 e1c88f1b72d200c1a07bb7fb72ba45a9df542015854bd7e6 002f1860 0000038c e1c88f1b72d200c1a07bb7fb72ba45b4ca50362b9e4cd4f1 002f1bec 00000380 e1c88f1b72d200c1a07bb7fb72ba45b5c645372b9743d1e477484270 002f1f6c 00000150 e1c88f1b72d200c1a07bb7fb72ba45b5da4222119f46 002f20bc 000003a8 e1c88f1b72d200c1a07bb7fb72ba45a2ca573706ae41d7f861 002f2464 00000128 e1c88f1b72d200c1a07bb7fb72ba45b3dc54202b9f43d5ed 002f258c 000000cc e1c88f1b72c71fdabb648ced48aa73b5cc502010 002f2658 0000031c e1c88f1b72c71fdabb648ced48a97fb2f0583c129e 002f2974 00000090 e1c88f1b72c71fdabb648ced48be6fb4c854 002f2a04 000000d0 e1c88f1b72c71fdabb648ced48bc7fb5ca450d049e50ccd7684c4264 002f2ad4 00000130 e1c88f1b72c71fdabb648ced48bd7fb2f0413d06857dc8fa7d58 002f2c38 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002f2c40 000000e0 f1c3871146ea1eca8a6286d767bc75a1dd542107 002f2d20 00000138 e1c88f1b72d91dc9bc6889e448aa73b5c46e31189443cad77c5f53637b337a686d 002f2e58 00000474 e1c88f1b72d91dc9bc6889e448aa73b5c46e31069443cced 002f32cc 00000190 e1c88f1b72d91dc9bc6889e448aa73b5c46e361d8241d9fa7c 002f345c 00000140 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dd9e47451445d473e65 002f359c 000000d4 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857ddbe7765a4e764d307b 002f3670 00000144 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dd4ec795a 002f37b4 00000164 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dd5e96b4a42707b316678 002f3918 000000d4 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dcaed7c4b496645317662 002f39ec 00000140 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dcaed6b61446354 002f3b2c 000000ec e1c88f1b72d91dc9bc6889e448aa73b5c46e3b07ae46d9fc79614b6d572b 002f3c18 00000188 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dcbfd7b5d427157306744751e 002f3da0 00000114 e1c88f1b72d91dc9bc6889e448aa73b5c46e20118256d7fa7d 002f3eb4 00000314 e1c88f1b72d91dc9bc6889e448aa73b5c46e211a9052cbe0774a 002f41c8 00000324 e1c88f1b72d91dc9bc6889e448aa73b5c46e211a9052dbe4775042 002f44ec 000001fc e1c88f1b72d91dc9bc6889e448aa73b5c46e3f1d8350d7fa475d4b6d4a3a 002f46e8 00000150 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dc8fa7d5a786e40 002f4838 000000d4 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dc8fa7d584270563a71447709e5 002f490c 000003cc e1c88f1b72d91dc9bc6889e448aa73b5c46e2111857dc8fa7d584270563a71447709e5 002f4cd8 000000d4 e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dd4ec474a5e7241 002f4dac 000000dc e1c88f1b72d91dc9bc6889e448aa73b5c46e3511857dd4fd766150754d3b 002f4e88 000000dc e1c88f1b72d91dc9bc6889e448aa73b5c46e2111857dd4fd766150754d3b 002f4f64 0000032c e1c88f1b72d91dc9bc6889e448aa73b5c46e33008543dbe0474d4963542c 002f5290 00000138 e1c88f1b72d91dc9bc6889e448aa73b5c46e31189443cad77b51497645367b7e6b 002f53fc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002f5404 0000036c e1c88f1b72d916cfb1548bfa72af6ea3 002f5770 00000114 e1c88f1b72d916cfb1548ced7bab6ea3 002f5884 000000dc e1c88f1b72d916cfb1548fed639179a7df50311d855b 002f5960 00000130 e1c88f1b72d916cfb1548fed639177a7d76e3e10ae51d1f27d 002f5a90 00000060 e1c88f1b72d916cfb1548fed639177aacb6e211d8b47 002f5af0 000000dc e1c88f1b72d916cfb1548fed639175a5cc4422159f41c1 002f5bcc 000000d4 e1c88f1b72d916cfb1548fed639175a5cc4422159f41c1d77057406a 002f5ca0 00000250 e1c88f1b72d916cfb1548fed63916ca9c3443f1182 002f5ef0 000000d4 e1c88f1b72d916cfb1548fed63916ca9c3443f11827ddbe76d5053 002f5fc4 000000d4 e1c88f1b72d916cfb1549bed639175a5cc4422159f41c1d77057406a 002f6098 00000114 e1c88f1b72d916cfb1549aed76aa45abc355 002f61ac 000000e4 e1c88f1b72d916cfb1549ffa7eba7f99c25d36 002f6290 0000030c e1c88f1b72d916cfb1548fed639176a2ce550d1d9f44d7 002f659c 000000d4 e1c88f1b72d916cfb1548fed639169b6ce433707ae41cdfa6a5b4976 002f6670 000000d4 e1c88f1b72d916cfb1548fed639169b6ce433707ae45d7e974 002f6744 000000d8 e1c88f1b72d916cfb1549bed639169b6ce433707ae45d7e974 002f681c 000000d4 e1c88f1b72d916cfb1548fed639179a9c1553b00984dd6 002f68f0 000000d4 e1c88f1b72d916cfb1549aed64a176b0ca6e311b9f46d1fc715149 002f69c4 0000026c e1c88f1b72d916cfb1548bfa72af6ea3f05f3703 002f6c30 000001bc e1c88f1b72d916cfb15489ec73916ca9c3443f1182 002f6dec 00000298 e1c88f1b72d916cfb15484e774af6ea3 002f7084 00000124 e1c88f1b72d916cfb1549ffa7eba7f99c25d362b934ed7eb734d 002f71a8 000000dc e1c88f1b72d916cfb1548fed639176a3d9543e1d9f45e7e1765848 002f7284 000000dc e1c88f1b72d916cfb1548fed639169b4cc6e3f1b9547 002f7360 000002c8 e1c88f1b72d916cfb15484e774af6ea3f0432107 002f7628 000001a4 e1c88f1b72d916cfb1548fed63916ca9c3443f11827dd1e67e51 002f77cc 00000128 e1c88f1b72d916cfb1548fed63917eb4c647372b855bc8ed 002f78f4 000000d4 e1c88f1b72d916cfb1549bed639168a3de4437078547dcd76b4c445d4930717e 002f79c8 0000014c e1c88f1b72d916cfb1549bed639174a7c254 002f7bc8 00000024 d7f3a73172f137e29c45a3d7539f 002f7bec 0000001c d7f3a73172f03cff804eb7cc46 002f7c08 00000010 d7f3a73172fc3ce78154bbd9 002f7c18 00000028 d7f3a73172f436ea8a58b9 002f7c40 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 002f7c6c 00000028 d7f3a73172e233e78154bcc15a8b5e 002f7c94 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 002f7c9c 00000060 fcdd8f1740d602d7 002f7cfc 00000050 deefbd3c62e12de19b47a1c652914992ee6517 002f7d4c 00000070 e1c891115ed42ddea7648bed64bd45b4ca40 002f7dbc 00000108 c1e8b12d5ed601cda66ab7e576a774 002f7ec4 000000ec e1c891115ed42dcaba548bfb76ad7899cd5e261c 002f7fb0 000000d4 e1c891115ed42dcaba548bfb76ad7899cc543e18 002f8084 00000008 e1c891115ed42dc7b866b7ef72ba45a8ca49262b9d46e7e176615370413a 002f808c 00000028 e1c891115ed42dc7a6789ded48a777abf0433d01854bd6ed474c5472 002f80b4 00000078 e1c891115ed42dc7b866b7fd67aa7bb2ca6e26069447 002f812c 00000194 e1c891115ed42dc7b866b7fd67aa7bb2ca6e2117944ed4d7794a537057 002f82c0 00000140 e1c891115ed42dc7b866b7fd67aa7bb2ca6e20119757cbed474e526e4830637e6b 002f8400 000002b8 e1c891115ed42dc7b866b7fd67aa7bb2ca6e3c1b9547e7f86b6148604e00717a6d1b 002f86b8 000001dc e1c891115ed42dc7b866b7fd67aa7bb2ca6e3c1b9547e7ec7c614e667b3b746f78 002f8894 00000078 e1c891115ed42dc7b866b7fd79a76e99df443e189e54ddfa475a486c41 002f890c 00000070 e1c891115ed42dc7b866b7fc72bd6e99d8530d179041d0ed475a467645 002f897c 000000a8 e1c891115ed42dc7b866b7fc72bd6e99da530d129e50e7e6775a42 002f8a24 00000078 e1c891115ed42dc7b866b7fc72bd6e99c3550d069443d4e1625b43 002f8a9c 000000fc e1c891115ed42dc7b866b7fb63af68b2f0443c1d857ddee46d4d4f6b4a38 002f8b98 00000110 e1c891115ed42dc7b866b7fb72ba45b4dc420d079947d4fe7d4d 002f8ca8 000000b8 e1c891115ed42dc7b866b7fb72ba45b4dc420d199845cae96c57486c7b2c617a6d1f 002f8d60 00000230 e1c891115ed42dc7b866b7fb72ba45b4dc420d19944fdaed6a615476452b70 002f8f90 00000034 e1c891115ed42dc7b866b7fb72ba45b6da5d3e1b8747cad77e5f4e6e413b 002f8fc4 000000d0 e1c891115ed42dc7b866b7fb72ba45a8da530d19944fdaed6a61536343 002f9094 000004a8 e1c891115ed42dc7b866b7fb72ba45a8c058362b9050cae96161426c502d6c 002f953c 000004ac e1c891115ed42dc7b866b7fb72ba45a8c055372b8655d6 002f99e8 000000f4 e1c891115ed42dc7b866b7fb72ba45a8c055372b8150ddfe474d5363503a 002f9adc 00000068 e1c891115ed42dc7b866b7fb72ba45aacb42302b9d4ddbe3475d486e483666727614 002f9b44 0000071c e1c891115ed42dc7b866b7fb72ba45aacb42302b9d46e7e96c4a5571 002fa260 00000090 e1c891115ed42dc7b866b7fb72ba45aacb50362b9f43d5ed 002fa2f0 000000e8 e1c891115ed42dc7b866b7fb72ba45aacb50362b9c47d4fc7c51506c7b2c617a6d1f 002fa3d8 000001d4 e1c891115ed42dc7b866b7fb72ba45aacb50362b9056ccfa6b 002fa5ac 000000a0 e1c891115ed42dc7b866b7fb72ba45aedf6e261b814dd4e77f47 002fa64c 000000b4 e1c891115ed42dc7b866b7fb72ba45a2da530d068251e7e1765848 002fa700 000000e0 e1c891115ed42dc7b866b7fb72ba45a2da530d19944fdaed6a615476452b70 002fa7e0 00000214 e1c891115ed42dc7b866b7fb72ba45a2ca532713ae44d4e97f4d 002fa9f4 00000144 e1c891115ed42dc7b866b7fb72ba45b6dd583c00ae44d4e97f4d 002fab38 00000090 e1c891115ed42dc7b866b7fb72ba45a2ce45332b9d4dcbfc47554e614f 002fabc8 000002b4 e1c891115ed42dc7b866b7fb72ba45a5ca5d3e2b8256d9fc7d 002fae7c 00000064 e1c891115ed42dc7b866b7fb72ba45a4ce452611835be7eb795d4f677b2f7a777019ff 002faee0 00000064 e1c891115ed42dc7b866b7fa7aba74a9cb540d018146d9fc7d 002faf44 0000007c e1c891115ed42dc7b866b7fa7aba74a9cb540d049056d0d76b4a4676512c 002fafc0 00000060 e1c891115ed42dc7b866b7fa7aba74a9cb540d109851dbe96a5a 002fb020 0000007c e1c891115ed42dc7b866b7fa7aba74a9cb540d179943d6ef7d61436b573c74697d 002fb09c 000000a0 e1c891115ed42dc7b866b7fa72a345b0c05d0d12834dd5d7745a4666 002fb13c 000001cc e1c891115ed42dc7b866b7e576bd6ea3dd6e21009056cdfb 002fb308 00000064 e1c891115ed42dc7b866b7e4739179a7cc59372b9e44dee47150425d4b2b7d7e6b 002fb36c 00000068 e1c891115ed42dc7b866b7e164bd6fa3f05233189d40d9eb73 002fb3d4 000002fc e1c891115ed42dc7b866b7e179bd7fb4db6e2007827dd5ed755c4270 002fb6d0 000000a4 e1c891115ed42dc7b866b7e1649176a2dc530d199850cae76a5b43 002fb774 000000bc e1c891115ed42dc7b866b7e164917eb4c26e271a9856 002fb830 00000070 e1c891115ed42dc7b866b7e067916fa8de423111ae57d6e16c615370413a4a737609f2 002fb8a0 000000f0 e1c891115ed42dc7b866b7e067916fa8de443b118241ddd76d504e767b377a686d 002fb990 0000008c e1c891115ed42dc7b866b7e067916fa8de443b118241ddd76d504e76 002fba1c 000006a0 e1c891115ed42dc7b866b7e0679169b2ce43262b9d4bd6e3 002fc0bc 00000048 e1c891115ed42dc7b866b7e067917cafc1550d159240d1 002fc104 000000e8 e1c891115ed42dc7b866b7e067917ba2cb6e271a9856e7ed794c4b7b 002fc1ec 00000030 e1c891115ed42dc7b866b7e072af68b2cd543300 002fc21c 000001bc e1c891115ed42dc7b866b7e076b87f99c9433d0e944ce7ec794a46 002fc3d8 0000008c e1c891115ed42dc7b866b7ef72ba45b4ca420d1d9f44d7 002fc464 00000098 e1c891115ed42dc7b866b7ef72ba45b1dd582611854acafd 002fc4fc 0000007c e1c891115ed42dc7b866b7ef72ba45a8dc520d078543cced 002fc578 000000d4 e1c891115ed42dc7b866b7ef72ba45a8c058362b9050cae96161426c502d6c 002fc64c 00000378 e1c891115ed42dc7b866b7ef72ba45a8ca49262b9f4ddced475d46727b3b746f78 002fc9c4 0000007c e1c891115ed42dc7b866b7ef72ba45aacb42302b8057d1ed6b5d425d543a7b7f 002fca40 00000114 e1c891115ed42dc7b866b7ef72ba45aacb42302b9d46d7e1 002fcb54 00000088 e1c891115ed42dc7b866b7ef72ba45aacb42302b924fe7fb6c5f5367 002fcbdc 00000064 e1c891115ed42dc7b866b7ef72ba45aedf6e261b814dd4e77f47 002fcc40 000000c0 e1c891115ed42dc7b866b7ef72ba45aec042262b9046d9f86c5b55 002fcd00 0000005c e1c891115ed42dc7b866b7ee65ab7f99c043221c904ce7e0774d5371 002fcd5c 00000070 e1c891115ed42dc7b866b7ee65ab7f99cc5c3304 002fcdcc 00000150 e1c891115ed42dc7b866b7ee78bc79a3f05333179a47d6ec475a4e714730637e6b03 002fcf1c 000000e0 e1c891115ed42dc7b866b7ed79af78aaca6e3a119050ccea7d5f535d54307977 002fcffc 000000c8 e1c891115ed42dc7b866b7ec65a345b3c1402117947ddffa774b575d493a78797c08f5 002fd0c4 000001bc e1c891115ed42dc7b866b7ec65a345b3c1402117947dc8e17651575d432d7a6e6909 002fd280 00000060 e1c891115ed42dc7b866b7ec65a345b6dd5422158347e7e477597864482a6673 002fd2e0 00000054 e1c891115ed42dc7b866b7ec65a345b6ce453a2b924addeb73 002fd334 000000c0 e1c891115ed42dc7b866b7ec65a345a1ca450d1d9f7dcdfb7d61576d562b 002fd3f4 000000a0 e1c891115ed42dc7b866b7ec7ebd7ba4c3540d1c9443cafc7a5b46767b2f7a7775 002fd494 000001d0 e1c891115ed42dc7b866b7ec72a27fb2ca6e2007827dd5ed755c4270 002fd664 000000d0 e1c891115ed42dc7b866b7ec72ac6fa1f0522015824a 002fd734 00000128 e1c891115ed42dc7b866b7ec72af76aac0520d068251 002fd85c 00000078 e1c891115ed42dc7b866b7ec72af76aac0520d189551da 002fd8d4 000000bc e1c891115ed42dc7b866b7ec72af76aac0520d189543dc 002fd990 000000f4 e1c891115ed42dc7b866b7eb7bab7bb4f0553300907dd4e76b4a78694d3c7e 002fda84 00000280 e1c891115ed42dc7b866b7eb7bab7bb4f05f3d1d957dd9fa6a5f5e5d4131616960 002fdd04 00000070 e1c891115ed42dc7b866b7eb7bab7bb4f042261b817dd4e77f61546a56367b70 002fdd74 00000080 e1c891115ed42dc7b866b7eb7fab79adf05d362b8347cbfc774c42 002fddf4 000000bc e1c891115ed42dc7b866b7eb7fab79adf0583c1b817dd5ed755c427057 002fdeb0 000000dc e1c891115ed42dc7b866b7eb7fab79adf0523d04887dcbfc794a5271 002fdf8c 0000009c e1c891115ed42dc7b866b7eb7faf74a1ca6e2117827ddee479595430 002fe028 00000244 e1c891115ed42dc7b866b7eb7faf74a1ca6e2117827ddee4795954 002fe26c 00000090 e1c891115ed42dc7b866b7eb7faf74a1ca6e2011825bd6eb474c42647b3c7a6e770e 002fe2fc 00000090 e1c891115ed42dc7b866b7eb7faf74a1ca6e3e1195 002fe38c 000000c0 e1c891115ed42dc7b866b7eb7faf74a1ca6e3e108240e7ee745f4071 002fe44c 00000064 e1c891115ed42dc7b866b7eb7faf74a1ca6e3a1b8256e7e5775a42 002fe4b0 00000068 e1c891115ed42dc7b866b7eb7faf74a1ca6e3a1b8256e7e46d50 002fe518 000000e8 e1c891115ed42dc7b866b7eb72a27699cd5e3d009446 002fe600 000000c8 e1c891115ed42dc7b866b7eb76ad72a3f0583c1b8147cae96c575167 002fe6c8 000002c0 e1c891115ed42dc7b866b7ea7ea07e99da530d009e7dd6e77c5b 002fe988 00000540 e1c891115ed42dc7b866b7e97ba275a5f044302b974dcad776514367 002feec8 00000150 e1c891115ed42dc7b866b7e97ba275a5f044302b974dcad7754d786f462d 002ff018 00000124 e1c891115ed42dc7b866b7e97ba275a5f0583c1d857dcafb6b 002ff13c 000000a8 e1c891115ed42dc7b866b7e97ba275a5f0583c1d857dd4ec6b5c 002ff1e4 000001f4 e1c891115ed42dc7b866b7e97ba275a5f0583c1d857dd4ec795a 002ff3d8 000000a0 e1c891115ed42dc7b866b7e973aa45b0c05d0d009e7dd4ec795a 002ff478 00000070 e1c891115ed42dc7b866b7e973aa45aec042262b9046d9f86c5b55 002ff4e8 00000184 e1c891115ed42dcdb46880ed48a16aa3dd50261d8747 002ff66c 000000e0 e1c891115ed42dcdb46880ed48a774a9df542015854bceed 002ff74c 000002c8 e1c891115ed42dcdb96e89fa48ad7ba5c7540d109056d9d774515476 002ffa14 000000c0 e1c891115ed42dcdbd6a86ef72917eb4c647372b9d47dcfb 002ffad4 00000090 e1c891115ed42dcdba6f8dd762be7ea7db540d1b854addfa 002ffb64 00000ad0 e1c891115ed42dcabc7898e476b745abca4221159647 00300634 0000004c e1c891115ed42dcaa7629eed48a87bb3c345 00300680 0000004c e1c891115ed42dcaa7629eed48a275a5ce4537 003006cc 00000120 e1c891115ed42dcaa766b7ef74bd45a5c05c22189456dd 003007ec 000000a0 e1c891115ed42dcaa766b7ef72ba45a1dd5e2704ae51d1f27d 0030088c 00000094 e1c891115ed42dcaa766b7e179b87baac6553300947dd4e77f 00300920 000000fc e1c891115ed42dcaa766b7f865ab6aa7dd540d19944fdaed6a6155674930637e 00300a1c 000000dc e1c891115ed42dcaa766b7f865ab6aa7dd540d06944fd7fe7d61466e48 00300af8 00000104 e1c891115ed42dcaa766b7f962a77fb5cc540d13834dcdf84753426f463a6768 00300bfc 00000054 e1c891115ed42dcaa766b7f962a77fb5cc540d06944fd7fc7d6140704b2a65 00300c50 0000007c e1c891115ed42dcaa766b7f962a77fb5cc540d06944fd7fc7d61526c4d2b 00300ccc 00000098 e1c891115ed42dcaa766b7fa72a375b2ca6e2111857dcbed6c4a4660483a4a727d 00300d64 00000094 e1c891115ed42dcaa766b7fb7fbc73a8c46e3e1b967dcbe1625b 00300df8 00000058 e1c891115ed42dcaa766b7fc72a36a99dc483c17 00300e50 00000050 e1c891115ed42dcaa766b7fd79bf6fafca423111ae50dde5774a425d432d7a6e69 00300ea0 00000078 e1c891115ed42dcaa766b7fd79bf6fafca423111ae50dde5774a425d51317c6f 00300f18 00000090 e1c891115ed42dcaa766b7eb7fab79adf05d3d13ae47d5f86c47 00300fa8 000002b4 e1c891115ed42dc7b866b7ec65a345a1ca450d189e45e7fb6c5f5367 0030125c 0000004c e1c891115ed42dcaa766b7f865a179a3dc423707ae53cde17d4d446740 003012a8 00000148 e1c891115ed42dc8b97e9be048be6fb4c8540d058241ddd76d504e767b30737d75 003013f0 0000003c e1c891115ed42dc8b97e9be048bb74afdb 0030142c 00000068 e1c891115ed42dc8a76e8dd770bd7899c35e311f 00301494 00000060 e1c891115ed42dc9b07fb7ea76ba6ea3dd480d078543cced 003014f4 00000060 e1c891115ed42dc9b07fb7eb7aaf6a 00301554 00000174 e1c891115ed42dc7b866b7ee7bbb69aef0562716ae45d9fc7d61457b543e6668 003016c8 000000e8 e1c891115ed42dc9b07fb7ef64ac45aac05239 003017b0 00000044 e1c891115ed42dc6b06a84d77aab76b2cb5e251a 003017f4 00000094 e1c891115ed42dc6a5548be072ad7199dd5421118354d9fc715149 00301888 00000074 e1c891115ed42dc6a5548df067af74a2f05d271a 003018fc 000000d0 e1c891115ed42dc6a5548ffa78bb6a99c1443f169450e7eb705f496541 003019cc 00000088 e1c891115ed42dc6a55499fd7eab69a5ca6e271a9856 00301a54 00000074 e1c891115ed42dc6a55499fb74ab45b3c158262b994dcbfc475a4264412d677e7d 00301ac8 0000003c e1c891115ed42dc6a55499fb74ab45b3c158262b8550dded4756487150 00301b04 00000074 e1c891115ed42dc6a55498fa48a275a7cb6e34069e4fe7ea775153 00301b78 00000074 e1c891115ed42dc6a5549be163ab45a0ce583e1b8747ca 00301bec 0000009c e1c891115ed42dc6a55486ed72aa45b2c06e20118347dfe16b4a4270 00301c88 00000280 e1c891115ed42dc7bb6498d762a073b2f04127069647 00301f08 0000005c e1c891115ed42dc2b1548be974a67f99c0573418984cdd 00301f64 00000150 e1c891115ed42dc2b1548be974a67f99c05f3e1d9f47 003020b4 0000005c e1c891115ed42dc2b1548be974a67f99c05f3e1d9f47e7e76c564270 00302110 00000090 e1c891115ed42dc2b15485eb65ab69bfc1520d109e4cdd 003021a0 00000090 e1c891115ed42dc2b15485eb71bc7ba5db442011ae46d7e67d 00302230 00000090 e1c891115ed42dc2b15485eb73ab6ea7cc590d109e4cdd 003022c0 000000f8 e1c891115ed42dc2b1549aed64ba75b4ca6e361b9f47 003023b8 00000090 e1c891115ed42dc2b1549de664a67bb4ca6e361b9f47 00302448 00000068 e1c891115ed42ddea76e98e965ab45b3c14120118247d6fc474b496b5000677e781eff 003024b0 00000148 e1c891115ed42ddea76e9bed79ba45aec042262b9d57d6 003025f8 000004a8 e1c891115ed42ddea76e9bed79ba45b3c158262b8347d9ec61 00302aa0 000001e8 e1c891115ed42ddea76e9bed79ba45b3c158262b9f4dccd76a5b46665d 00302c88 00000074 e1c891115ed42ddea0798fed48aa73b4db48 00302cfc 00000170 e1c891115ed42ddfa0628dfb74ab45a2ca473b1794 00302e6c 00000084 e1c891115ed42ddfa0628dfb74ab45b3c158262b9e44dee47150425d4b2b7d7e6b 00302ef0 00000078 e1c891115ed42ddcb06a84e16dab45aacb 00302f68 00000038 e1c891115ed42ddcb06687fe729172a9dc450d159543c8fc7d4c 00302fa0 00000090 e1c891115ed42ddda16498d77ba17d99dc59201d9f49 00303030 00000160 e1c891115ed42ddab07985e179af6ea3 00303190 000000cc e1c891115ed42ddbbb7b9aed64ab74b2f0593d07857dd4fd76 0030325c 00000084 e1c891115ed42ddbbb798de97ba760a3f05d36 003032e0 0000022c e1c891115ed42dddb6799dea48ad7faac36e34069e4fe7e57d53 0030350c 00000084 e1c891115ed42dddbd7e9cec78b97499cd5026009450c1 00303590 000000e4 e1c891115ed42ddda16498d77ea27c99cb58211f 00303674 00000068 e1c891115ed42ddaba6a9bfc48ad7ba5c754 003036dc 00000170 e1c891115ed42ddbbb7b9aed64ab74b2f0443c1d857dcaed795a5e 0030384c 000000f0 e1c891115ed42ddbbb7b9aed64ab74b2f0443c1d857dd6e76c615567453b6c 0030393c 00000250 e1c891115ed42ddbbb7a9de172bd79a3f05537029841dd 00303b8c 00000048 e1c891115ed42dd8b07981ee6e9169a8ce410d06944ed9fc715149714c3665 00303bd4 00000060 e1c891115ed42dd9b4629cd771a16899c95d27079947cbd77b514a72483a617e 00303c34 0000003c e1c891115ed42dd9b4629cd771a16899df433d179451cbd77648 00303c70 00000028 e1c891115ed42ddf8a689be974ac45b2c06e3107907dcaed696156 00303c98 00000028 e1c891115ed42ddf8a689be974ac45b2c06e3102907dcaed696156 00303cc0 00000058 e1c891115ed42ddf8a689be574ac45b2c06e31079c7dddfe7d50535d55 00303d18 00000028 e1c891115ed42ddf8a788bfb74ac45b2c06e31079c7dcaed696156 00303d40 00000058 e1c891115ed42ddf8a689ee574ac45b2c06e31029c7dddfe7d50535d55 00303d98 00000028 e1c891115ed42ddf8a689ee574ac45b2c06e31029c7dcaed696156 00303dc0 00000068 e1c891115ed42ddba16284d774a67fa5c46e35069e57c8d7755b4a60412d4a7d7608d903ddc2042bee424a 00303e28 00000114 e1c891115ed42dcaa766b7eb7fab79adf056201b8452e7ee79574b6d523a67 00303f3c 000000b0 e1c891115ed42ddba16284d774a275b5ca6e3501937ddfe96c5b 00303fec 0000009c e1c891115ed42ddba16284d774a275b5ca6e33189d7dc8e76a4a7865452b7068 00304088 000000d0 e1c891115ed42ddba16284d774a275b5ca6e33189d7ddfe96c5b54 00304158 00000060 e1c891115ed42dc7b866b7eb7ba169a3f0503e18ae45d9fc7d4d 003041b8 00000164 e1c891115ed42dc7b866b7eb7ba169a3f05f3d1d957ddfe96c5b 0030431c 00000074 e1c891115ed42ddba16284d771a26fb5c76e3501937ddfe96c5b 00304390 000000f8 e1c891115ed42dc7b866b7ee7bbb69aef05f3d1d957ddfe96c5b 00304488 00000080 e1c891115ed42ddba16284d77baa45afdc6e2117827dcaed79524e78413b 00304508 00000060 e1c891115ed42dc7b866b7fc72bd6e99c3550d079251e7fa7d5f4b6b5e3a71 00304568 00000128 e1c891115ed42ddba16284d778be7fa8f0562716ae45d9fc7d 00304690 00000090 e1c891115ed42ddba16284d778be7fa8f0503e18ae45d9fc7d4d 00304720 00000060 e1c891115ed42dc7b866b7e767ab7499ce5d3e2b9643cced6b 00304780 000001f0 e1c891115ed42dc7b866b7e767ab7499c15e3b10ae45d9fc7d 00304970 000002b0 e1c891115ed42ddba16284d765ab77a9d9540d1a9e46dd 00304c20 00000074 e1c891115ed42dc7b866b7fa72a375b0ca6e3c1b9547 00304c94 00000124 e1c891115ed42dc7b866b7ec72ad75b3df5d372b8440e7ee6a514a5d4a30717e 00304db8 0000004c e1c891115ed42ddba16284d764ba75b6f05c331d9f56e7fc71534270 00304e04 0000019c e1c891115ed42dc7b866b7ec72af76aac0520d01937ddee76a61496d403a 00304fa0 000000e8 e1c891115ed42dc7b866b7ec72af76aac0520d01937ddee76a614a717b327769 00305088 0000011c e1c891115ed42dc7b866b7eb7faf74a1ca6e3601937dd5e97150535d5036787e6b 003051a4 00000068 e1c891115ed42ddba16284d760af73b2f0573d06ae53cde17d4d44677b386079 0030520c 000000e8 e1c891115ed42dd9b4629cd771a16899de443b118241ddd77f4b45 003063f0 00000024 d7f3a73172f137e29c45a3d7539f 00306414 00000038 d7f3a73172f137ff804eb7cc46 0030644c 00000028 d7f3a73172f436ea8a58b9 00306474 00000028 d7f3a73172e233e78154bcc15a8b5e 0030649c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003064a4 00000060 fcdd8f1740d602d7 00306504 00000050 deefbd3c62e12de79b54bab9489b548bee631931b57df1c6576e784e601e51 00306554 00000050 deefbd3c62e12de19b47a1c652914992ee6517 003065a4 00000044 deefab2166ea3ce18154a7c65b875483f0620635a567 003065e8 00000050 c1e8b12d7ef026f18045a1dc488f4e92fd 00306638 000000b0 deefbd3568e12dfc9058bcc7458b4595fd720d3abe6bfc 003066e8 0000003c c1e8af3b72e13df19658b7da528a4f88eb701c37a8 00306724 00000028 e1c8912d4ad006f1a76e99 0030674c 00000030 e1c8912d4bc717cb8a798df9 0030677c 00000110 e1c891115ed82ddea7648bed64bd45a3d9543c00 0030688c 000000f4 e1c891115ed82ddea7648bed64bd45b4ca40 00306980 00000104 e1c891115ed82dcca06284ec48a66a99cc5735 00306a84 0000006c e1c891115ed82dcdbd6a86ef72916ca9c36e3b1a8257deee 00306af0 00000090 e1c891115ed82dcda366b7fa64bd45abca5c3011837dd1e6774e 00306b80 000003b8 e1c891115ed82dcaa7629eed48bd77a7dd450d118747d6fc 00306f38 00000044 e1c891115ed82dc8a76e8dd770bd7899c35e311f 00306f7c 0000004c e1c891115ed82dc9b07fb7ef64ac45aac05239 00306fc8 000000d0 e1c891115ed82dc9b07fb7fd79a76e99dd5421118354d9fc7151495d572b746f6c09 00307098 00000d44 e1c891115ed82dc0ba6f8dd77ea075b6 00307ddc 0000015c e1c891115ed82dc0ba6585e165bc75b4ca550d12904bd4e76e5b555d403a797a6025e31dccc21a21fc 00307f38 0000004c e1c891115ed82dc0ba6498 00307f84 000002c0 e1c891115ed82ddcb06a84e16dab45aacb6e361b9f47 00308244 00000094 e1c891115ed82ddcb87f86e773ab45a8ca54361195 003082d8 00000040 e1c891115ed82ddcb87f86e773ab45b6da433511ae4cdded7c5b43 00308318 00000314 e1c891115ed82dddb07fb7f8649179a9c1553b00984dd6 0030862c 000000ac e1c891115ed82ddbbb629cd767bb76aac0473706ae50ddf96d5b5476 003086d8 00000414 e1c891115ed82ddba16284d776aa7e99ce5d3e2b994dcbfc475f4363542b70696a 00308aec 00000454 e1c891115ed82ddba16284d776aa7e99cc543e18ae4fdde57a5b55 00308f40 000002f4 e1c891115ed82ddba16284d774af6ab2da43372b9f47c0fc475048664100666f780ee3 00309234 00000358 e1c891115ed82ddba16284d774a67ba8c8540d18957dd7ea72614363503e4a777609f2 0030958c 0000040c e1c891115ed82ddba16284d774a67fa5c46e341b837ddbe77c5b786f452b7673 00309998 000002c4 e1c891115ed82ddba16284d774a67fa5c46e3e1195 00309c5c 00000320 e1c891115ed82ddba16284d774a675a9dc540d1a9455e7f96d515577490071726a11f5 00309f7c 000002e4 e1c891115ed82ddba16284d774bd45aacb6e361b9f47e7eb79524b60453c7e 0030a260 00000118 e1c891115ed82ddba16284d773ab76a3db540d109851d3d77e4c486f7b2e60746b0feb 0030a378 0000057c e1c891115ed82ddba16284d774a67fa5c46e341b837dd5e16b4d4e6c4300646e7608f308e3cf0137f3 0030a8f4 00000124 e1c891115ed82ddba16284d773bc7799cc5937179a7dd1e6774e78655630606b6a 0030aa18 00000428 e1c891115ed82ddba16284d773bc7799df58311fae4edce97c61416d560079747e 0030ae40 000003ac e1c891115ed82ddba16284d773bc7799dd5433189858ddd77f4c4877542c 0030b1ec 000000ec e1c891115ed82ddba16284d773bc7799dc54262b9650d7fd6861406157 0030b2d8 00000c5c e1c891115ed82ddba16284d773bc7799c9583c1d824ae7ef7b4d78614c38 0030bf34 00000058 e1c891115ed82dcaa766b7ee7ea073b5c76e3517827ddbe07f 0030bf8c 00000074 e1c891115ed82ddba16284d773bc7799c852212b9c4bcafa774c7860563a7470 0030c000 00000148 e1c891115ed82ddba16284d773bb6aaac6523300947dd5fb475345707b307b44760eee00ce 0030c148 00000280 e1c891115ed82ddba16284d773bb6aaac6523300947dcee7744b4a677b307b44760eee00ce 0030c3c8 00000094 e1c891115ed82ddba16284d771a774a2f0523d1a974bdfd77d4c556d56 0030c45c 00000158 e1c891115ed82ddba16284d771a168b1ce43362b9251d5eb7a 0030c5b4 00000194 e1c891115ed82ddba16284d770ab6e99c3550d079251e7fa7d5f4b6b5e3a71 0030c748 00000110 e1c891115ed82ddba16284d770ab6e99c3552116ae41d5d76b4a467641007a6f711ff4 0030c858 000000b0 e1c891115ed82ddba16284d770ab6e99c3553310ae4ad1ef70614861472a657a7719ff 0030c908 0000017c e1c891115ed82ddba16284d770ab6e99df440d10834fe7e0715b5563563c7d62 0030ca84 00000210 e1c891115ed82ddba16284d770ab6e99df440d10847dcbeb6e5a786e40 0030cc94 00000168 e1c891115ed82ddba16284d770ab6e99df440d048347cbed764a46764d307b446a0ee711c9d8 0030cdfc 0000003c e1c891115ed82dc9b07fb7f865ab69a3c1453300984dd6d76b4a4676512c 0030ce38 00000140 e1c891115ed82ddba16284d77faf74a2c3540d009e4de7e56d5d4f5d422d7a617c14 0030cf78 0000035c e1c891115ed82ddba16284d77ea075b6f0443c1d857dd7ee7e524e6c41 0030d2d4 000000f4 e1c891115ed82ddba16284d77ea06eb4c65f211d927dd9ec7c61446a413c7e 0030d3c8 00000124 e1c891115ed82ddba16284d77ea06eb4c65f211d9243d4e461614666400065686d15f400 0030d4ec 000002e4 e1c891115ed82dcdba6f8dd77ba17ba2f04337189443cbed 0030d7d0 00000984 e1c891115ed82ddba16284d77ea06eb4c65f211d9243d4e461614666400074777525e41ce3df1134fd 0030e154 0000002c e1c891115ed82ddba16284d77ea06eb4c65f211d9243d4e4616146664000747775 0030e180 00000048 e1c891115ed82dc7bb7f9ae179bd73a5f0523a119249 0030e1c8 000001b0 e1c891115ed82ddba16284d77baa45afc15e222b8157caef7d 0030e378 00000174 e1c891115ed82ddba16284d77aab68a1ca6e200782 0030e4ec 0000027c e1c891115ed82ddba16284d779a17499df433707944ccced7c614b667b3974727515f000cef40b29c75357818758 0030e768 00000378 e1c891115ed82ddba16284d779a17499df433707944ccced7c614b667b3974727515f000cef40b37c75357818746 0030eae0 000001f8 e1c891115ed82ddba16284d778ba72a3dd6e3e119054ddd76d504e767b30737d7513e800 0030ecd8 0000077c e1c891115ed82ddba16284d767bc7fb6ce43372b8150ddfb7d50536350367a756a 0030f454 00000154 e1c891115ed82ddba16284d767bc75a5ca42212b9c41cafa 0030f5a8 00000060 e1c891115ed82ddba16284d765ab7baac64b372b9251d4ec 0030f608 000001d4 e1c891115ed82ddba16284d765ab7baac64b372b9d46cbea474a5567412c 0030f7dc 00000408 e1c891115ed82ddba16284d775bb73aacb6e3d169b7dd5e9684d 0030fbe4 00000250 e1c891115ed82ddba16284d765ab7baac64b372b834fcce6775a4271 0030fe34 000002b0 e1c891115ed82ddba16284d765ab7baac64b372b8547d5f847524363402c 003100e4 00000b58 e1c891115ed82ddba16284d765ab79a9c1523b18947dd5ed6c5f 00310c3c 00000398 e1c891115ed82ddba16284d765ab6aaace52372b9247d4e44753426f463a67 00310fd4 00000548 e1c891115ed82ddba16284d765ab7baac64b372b9e40d2d76b4a467641 0031151c 0000057c e1c891115ed82ddba16284d765ab6aaace52372b9c4bcbfb7150405d552a7a696c17d901d5d803 00311a98 0000035c e1c891115ed82ddfa0649afd7a917eafdc5a0d179947dbe3 00311df4 0000026c e1c891115ed82dcdba6f8dd77ba17ba2f04337079450ceed 00312060 000003f0 e1c891115ed82ddcb07b84e974ab45a2f0523d19814eddfc7d 00312450 00000308 e1c891115ed82ddba16284d765ab77a9d9540d159d4ee7e0774d535d453b746b6d1ff416 00312758 000001a4 e1c891115ed82ddba16284d765ab77a9d9540d199851cbe17659786f462d 003128fc 000004d4 e1c891115ed82ddcb06c8de648ad76a3ce5f2704ae41d7e56852427641 00312dd0 00000228 e1c891115ed82ddba16284d765ab69b2ce43262b9251e7e47c614676503e76734615f6 00312ff8 00000424 e1c891115ed82ddba16284d765ab69b2ce43262b9251e7e47c6148764c3a6744760a 0031341c 00000138 e1c891115ed82ddba16284d765ab69b2c043372b8650d1fc7d5c46614f 00313554 000002d8 e1c891115ed82ddba16284d764ab6e99c3552116ae46cae5475f5376562c 0031382c 000000d0 e1c891115ed82ddba16284d773bc7799df4337049050ddd76b5d516657 003138fc 0000007c e1c891115ed82ddba16284d764ab6e99dd42212b824adde46e5b54 00313978 00000024 e1c891115ed82dddb07fb7fa64bd45b5c7543e029451 0031399c 00000180 e1c891115ed82ddba16284d764ab6e99dc522410ae43ccfc6a 00313b1c 000005fc e1c891115ed82ddba16284d773bc7799cc4337158547e7e4775978774a3661446f4e 00314118 000003e4 e1c891115ed82ddba16284d773bc7799cc4337158547e7e4775978774a3661 003144fc 000003f4 e1c891115ed82ddba16284d764be76afdb6e200782 003148f0 00000618 e1c891115ed82ddca678b7fb67a273b2f05c37069647e7eb7753576e412b70 00314f08 000002ac e1c891115ed82ddba16284d764ba7bb4db6e31079c4fe7ea7f6157704b3c 003151b4 0000015c e1c891115ed82ddba16284d765ab6eb4d66e3415984eddec474c4265413166 00315310 00000064 e1c891115ed82dc2b07d8de47ea07d99cc5e3f049d47cced 00315374 00000140 e1c891115ed82ddba16284d765ab69b2ce43262b9251e7e57d4c406757 003154b4 00000028 e1c891115ed82ddcb0789ce965ba45a5dc6e3f118345ddfb 003154dc 00000140 e1c891115ed82dd8ba67b7fa72be45a2ca5d330dae47c0f8714c4266 0031561c 00000328 e1c891115ed82ddba16284d764b769b2ca5c0d1d9f4dc8ed6a5f536b523a 00315944 000003b4 e1c891115ed82ddba16284d765ab6aa9dd450d179e4cdee17f61427056306768 00315cf8 00000824 e1c891115ed82ddba16284d765ab7baac64b372b9f4dd6d7684c42714131617e7d25ea01d5d80337 0031651c 00000534 e1c891115ed82ddba16284d765ab7baac64b372bb26ff9d84b 00316a50 00000684 e1c891115ed82ddba16284d765ab7baac64b372b9247d4e44758466b4830637e6b 003170d4 00000a7c e1c891115ed82ddba16284d779a179a3c35d0d048347cbed764a7871453c71 00317b50 0000049c e1c891115ed82ddba16284d773bb6aaac6523300947dc8fb6c5155677b307b44760eee00ce 00317fec 000013e8 e1c891115ed82ddba16284d776ad6eafd9502611ae51d4e96e5b 003193d4 00000ad0 e1c891115ed82ddba16284d775bc73a8c86e3c07927dd1e66c517861413379 00319ea4 00000064 e1c891115ed82dc8b678b7eb78a07cafc86e3706834dca 00319f08 00000104 e1c891115ed82ddba16284d763ab69b2f0433710844cdce9765d5e5d4d317a6b 0031a00c 0000088c e1c891115ed82ddba16284d764a27bb0ca6e381b984ce7fb6150445d493667697608 0031a898 00000c70 e1c891115ed82ddba16284d763bc7fa3f057331d9d4dceed6a61446f7b2b7a447a09 0031b508 00000d00 e1c891115ed82ddba16284d763bc7fa3f057331d9d4dceed6a6144717b2b7a447a17 0031c208 00000838 e1c891115ed82ddba16284d762a06ab4ca42371a857dcde6714a786d4a007668 0031ca40 000002a4 e1c891115ed82ddba16284d762a068a3ce5d3b0e947dd6e776615770412c70756d1fe23ad0cf0137f354 0031cce4 00000254 e1c891115ed82ddba16284d762be7ea7db540d169056cced6a477861453c7d7e460ae909d5c811 0031cf38 00000054 e1c891115ed82dccb47f9ced65b745b5db502611ae41d0e976594266 0031cf8c 00000274 e1c891115ed82ddba16284d762be7ea7db540d129f40e7f86a5b515d572b746f7c 0031d200 0000005c e1c891115ed82ddba16284d779be79aef05f2117ae52d7fa6c61446a4531727e7d 0031d25c 00000068 e1c891115ed82ddba16284d779be79aef0553b079a7dc8e76a4a78614c3e7b7c7c1e 0031d2c4 00002098 e1c891115ed82ddba16284d779be79aef0553b079a7dd9f8685b4670413b 0031f35c 00000318 e1c891115ed82ddba16284d779be79aef05f2117ae46d1fb794e5767452d707f 0031f674 000009b0 e1c891115ed82ddba16284d779be79aef0553b079a7ddce16b5f5772413e677e7d 00320024 0000042c e1c891115ed82ddba16284d779be7999e87d211d9f45d4ed475a4e714f0071726a0ae711dfc3 00320450 00000be4 e1c891115ed82ddba16284d779be7999e87d3601904ee7ec714d4c5d4036666b780ee50d 00321034 00000540 e1c891115ed82ddba16284d762be7ea7db540d189551dad7745a7863502b6768 00321574 000006c0 e1c891115ed82ddba16284d762be7ea7db540d189543dcd77b5149664d2b7c7477 00321c34 000005a0 e1c891115ed82ddba16284d765ab7baac64b372b8351cbfb47524363402c 003221d4 0000032c e1c891115ed82ddba16284d77baa45b4ca42261b8347e7ec775042 00322500 00000388 e1c891115ed82dc2b1549aed64ba75b4ca6e361b9f47 00322888 000002d4 e1c891115ed82ddba16284d774a67ba8c8540d18957ddce96c5f786e4b2c6144780ef217 00322b5c 00000078 e1c891115ed82ddba16284d762a073b2f05233179947e7ec794a465d4830666f 00322bd4 00000298 e1c891115ed82ddba16284d77faf74a2c3540d179041d0ed4751496e4d3170447f1bef09 00322e6c 0000067c e1c891115ed82ddba16284d778ba72a3dd6e3e119054ddd76d504e767b307b777014e3 003234e8 00000178 e1c891115ed82ddbbb629cd77baa45a2ce45332b9d4dcbfc4757496d54 00323660 00000f3c e1c891115ed82ddba16284d77baa45a0ce583e1b8747cad77b4d78764b007676 0032459c 00000cf4 e1c891115ed82ddba16284d77baa45a0ce583e1b8747cad77b5378764b007668 00325290 00001cc8 e1c891115ed82ddba16284d767bc7fb5ca5f262b844cd1fc4751495d4732 00326f58 00001854 e1c891115ed82ddba16284d767bc7fb5ca5f262b844cd1fc4751495d472c 003287ac 0000079c e1c891115ed82ddba16284d774a675a9dc540d178550d4fa475f49667b2f677e6a1fe811e3de062dec 00328f48 000001d4 e1c891115ed82ddba16284d767bc7fb5ca5f262b9550d5d76d504e76 0032911c 0000057c e1c891115ed82ddba16284d767bc7fb5ca5f262b904ed4d76d504e7657 00329698 000008e8 e1c891115ed82ddbbb629cd778b87fb4cc5e3f199856e7ec794a465d4830666f4613e80acc 00329f80 000007e4 e1c891115ed82ddba16284d771a774afdc590d008347ddd77e5f4e6e4b2970694619f53ac8c43727f5 0032a764 00000764 e1c891115ed82ddba16284d771a774afdc590d008347ddd77e5f4e6e4b2970694619eb3ac8c43727eb 0032aec8 000015dc e1c891115ed82ddba16284d773bc7799c8433d01817ddee971524874412d 0032c4a4 00000840 c1e8b12d5ed601dcb07ab7e576a774 0032cce4 00000894 e1c891115ed82dcfa07f87ee76a776a4ce52392b844cd1fc6b 0032d578 00000700 e1c891115ed82ddba16284d776bb6ea9c9503b189343dbe3474b496b502c 0032dc78 000000f4 e1c891115ed82dcfa07f87ee76a776a4ce52392b9547d4e96161427a5436677e7d 0032dd6c 00000038 e1c891115ed82dcaa766b7ef65a16fb6f057331d9d4dceed6a 0032dda4 000008b4 e1c891115ed82ddba16284d773a145b2c750252b984cd7f8474b496b502c 0032e658 00000a64 e1c891115ed82ddba16284d764a27bb0ca6e381b984ce7fc6a5f49714d2b7c7477 0032f0bc 00000d4c e1c891115ed82ddba16284d779be79aef05f2117ae43c8f87d5f556740 0032fe08 000003c0 e1c891115ed82ddba16284d779be7999e87d211d9f45d4ed475054617b3b7c68691bf206d4 003301c8 000004d4 e1c891115ed82ddba16284d779be7999e87d3601904ee7e66b5d78664d2c657a6d19ee 0033069c 000003d4 e1c891115ed82ddba16284d779a17ea3f0413d06857ddbe079504067 00330a70 000007b8 e1c891115ed82dcdba658ee170bb68a7db583d1aae41d0ed7b55 00331228 000006ac e1c891115ed82ddbbb7880e965ab45aacb6e361b9f47 003318d4 000004bc e1c891115ed82dddbb6a98d773ab76a3db540d179e4fc8e47d4a42 00331d90 000003a8 e1c891115ed82dc3b6549aed64b774a5f0553d1a94 00332138 00000400 e1c891115ed82dc3b6548efa76ad6eb3dd540d109e4cdd 00332538 000004d8 e1c891115ed82dc3b6548ced63af79aef0553d1a94 00332a10 00000348 e1c891115ed82dc2ba6cb7fa72bd7fb4d9540d179052d9eb714a5e5d40307b7e 00332d58 000004cc e1c891115ed82dc2b1549bed639179a7df50311d855be7ec775042 00333224 00000708 e1c891115ed82dc2b1548ced7bab6ea3f0553d1a94 0033392c 0000034c e1c891115ed82dc2b1549aed64ab68b0ca6e31158143dbe16c4778664b3170 00333c78 000008b0 e1c891115ed82ddba16284d765ab69b2ce43262b9251e7ea795d4c65563060757d25e915cf 00334528 00000454 e1c891115ed82dc2b1548bfa72af6ea3f0553d1a94 0033497c 0000034c e1c891115ed82dc2b1548be472af6899cc5e3c00904bd6ed6a61436d4a3a 00334cc8 00000eb0 e1c891115ed82ddba16284d762be7ea7db540d019f4bccd77b5149664d2b7c7477 00335b78 00000250 e1c891115ed82ddba16284d763a67bb1f0583c1b817dcde6714a54 00335dc8 00000614 e1c891115ed82dcaa7629eed48a37fb4c8540d179e4fc8e47d4a42 003363dc 00000470 e1c891115ed82ddcb06c8de648aa45a5c05c22189456dd 0033684c 000003f0 e1c891115ed82ddca678b7e575bc45b4ca5c3d029446 00336c3c 000000ac e1c891115ed82ddba16284d762a06bb3c6542117947dc8ed6a53786b4a3065447e08e910ccd8 00336ce8 00003724 e1c891115ed82ddba16284d765ab7baac64b372b9247d4e4474a55634a2c7c6f7015e8 0033a40c 000007e4 e1c891115ed82ddba16284d778ba72a3dd6e3e119054ddd76d504e767b3974727515f000ce 0033abf0 0000033c e1c891115ed82ddba16284d764a27bb0ca6e3e119054ddd76c4c466c573661727614 0033af2c 0000125c c1e8b12d5ed601cda666b7e576a774 0033c188 00000870 e1c891115ed82ddba16284d762a06ab4ca42371a857dcde6714a786d4a007676 0033c9f8 00000184 e1c891115ed82ddba16284d762a06ab4ca42371a857dcde6714a 0033cb7c 00000a54 e1c891115ed82ddba16284d762a06ab4ca42371a857dd9e47461526c4d2b66 0033d5d0 0000050c e1c891115ed82ddba16284d773bc7799dd543f1b8747e7e4775978774a3661 0033dadc 00000284 e1c891115ed82ddba16284d771a168a5ca6e25069856ddfc704c52 0033dd60 00000308 e1c891115ed82ddda16a8fef72bc7fa2f0433707884cdb 0033e068 00000038 e1c891115ed82ddab06698ed65af6eb3dd540d078543cced475d4f634a3870 0033e0a0 00001154 e1c891115ed82dccb47f9ced65b745b6c05d3b17887ddbe07950406740 003420f8 0000001c d7f3a73172f03cff804eb7cc46 00342114 00000028 d7f3a73172e233e78154bcc15a8b5e 0034213c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00342144 000000c0 c1e8b12d79f121ea8a5ea9 00342204 000000ac c1e8b12d5ed601cda36ab7e576a774 003422b0 00000090 e1c891115bd82ddea7648bed64bd45a3d9543c00 00342340 00000070 e1c891115bd82ddea7648bed64bd45b4ca40 003423b0 00000108 e1c891115bd82dcfb16fb7fa64bd45abca5c301183 003424b8 000003ac e1c891115bd82dcdb9649bed48bc69b5f05c37069647 00342864 0000042c e1c891115bd82dcdb9649bed48bc69b5f04222189856 00342c90 000000b4 e1c891115bd82dcab067b7fe78a245a9cd5b0d109056d9 00342d44 00000220 e1c891115bd82dc9b07fb7ec739173a2f055330090 00342f64 000001b8 e1c891115bd82dc9b07fb7f8649175a4c56e36158543 0034311c 000000dc e1c891115bd82dc9b07fb7fe78a245a9cd5b0d109056d9 003431f8 00000124 e1c891115bd82dc7bb629cd761a17699c053382b9543cce9 0034331c 000000bc e1c891115bd82ddeba7b9de476ba7f99c3553310ae54d7e447524e7150 003433d8 000000d0 e1c891115bd82ddcb06687fe729168b5dc 003434a8 00000478 e1c891115bd82ddcb06687fe729168b5dc6e3f119c40ddfa 00343920 000001a4 e1c891115bd82dddb07fb7f8649175a4c56e36158543 00343ac4 000006e4 e1c891115bd82dddb07fb7fe78a245a9cd5b0d109056d9 003441a8 00000674 e1c891115bd82dddb07fb7fa64bd45abcd430d078543cced 0034481c 000018e4 e1c891115bd82ddcb06a84e16dab45b4dc42 00346100 00000524 e1c891115bd82ddba16284d773ab6ea3dd5c3b1a947dd5ed755c42707b3270776d1ee912d2f40421ee4254 00346624 000002c8 e1c891115bd82ddba56f89fc729176a2ce550d19944eccec7749495d572b746f7c 003468ec 0000006c e1c891115bd82ddba16284d771a168b1ce43362b9254d5eb7a 00346958 00000108 c1e8b12d5ed601cda366b7e576a774 00346a60 000001f8 e1c891115bd82ddba16284d771bc7fa3d5540d1d9f4dc8d76d504e7657 00346c58 0000020c e1c891115bd82ddba16284d77aaf71a3f04321079c 00346e64 00000d70 e1c891115bd82dc1a56e86d765bd6999dc413e1d85 00347bd4 00000c18 e1c891115bd82dc1a56e86d765bd6999c254201394 003487ec 00000860 e1c891115bd82dc1a56e86d765bd6999c250200688 0034904c 00000098 e1c891115bd82dc7bb629cd765bd69ab 003490e4 000000e0 e1c891115bd82dcfb16fb7fa64bd 003491c4 000000c4 e1c891115bd82ddba16284d767bc75a5ca42212b9846e7ff6a5753677b3b67726f1fd906d4ca0623fd43 00349288 000006d4 e1c891115bd82ddba16284d760bc73b2ca6e3b10ae40d4e77b5554 0034995c 0000051c e1c891115bd82ddba16284d762be7ea7db540d1d957ddae4775d4c71 00349e78 00000a90 e1c891115bd82ddcb06887e674a776a3f05c370090 0034a908 000000d8 e1c891115bd82dddb07fb7ec739173a2f055330090 0034a9e0 000000a0 e1c891115bd82ddcb06887e674a776a3f058362b934ed7eb734d 0034aa80 00000384 e1c891115bd82ddba16284d762be7ea7db540d06825188d7715a7860483076706a 0034ae04 000005cc e1c891115bd82ddcb06687fe729168b5dc010d19944fdaed6a 0034b3d0 00001184 e1c891115bd82ddca678b7e572a378a3dd6e3415984eddec 0034c554 00000064 e1c891115bd82ddcb06887e674a776a3f0432107c1 0034c5b8 00000264 e1c891115bd82dcfb16fb7fa64bd2a99c2543f169450 0034c81c 00000260 e1c891115bd82dcba76a9bed48aa7e99c6550d109056d9 0034cecc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0034ced4 000000ec e1c891115bd816cc8a6a9aed769173a8cb542a2b854de7f87959425d4b3973687c0e 0034cfc0 000001d4 e1c891115bd816cc8a6887e57aa76e99cc473f10937ddbe07950406757 0034d194 0000013c e1c891115bd816cc8a6f81fa63b745a5d95c3616ae52d9ef7d 0034d2d0 0000013c e1c891115bd816cc8a6d9aed729179b0c255302b8143dfed 0034d40c 000002f0 e1c891115bd816cc8a6286e1639179b0c25530 0034d6fc 00000044 e1c891115bd816cc8a7b89ef72916bb5ce 0034d740 00000040 e1c891115bd816cc8a7b89ef729169b7f0402115 0034d780 000000f4 e1c891115bd816cc8a6c8dfc48bd6b99cc473f10937dc8e97f5b 0034d874 000000e8 e1c891115bd816cc8a798de9739169a5dc4320 0034d95c 00000210 e1c891115bd816cc8a798de97ba760a3f05224199540 0034db6c 00000114 e1c891115bd816cc8a7c9ae163ab45b5cc422006 0034dc80 00000154 e1c891115bd816cc8a7c9ae163ab45a5d95c3616ae47d6fc6a47 0034ddd4 0000023c e1c891115bd816cc8a6c8dfc48ad6cabcb530d049045dd 0034e010 00000178 e1c891115bd816cc8a6d84fd64a645a5d95c3616ae52d9ef7d 0034e188 00000038 d7f3a73172f137ff804eb7cc46 0034e1c0 0000001c d7f3a73172f03cff804eb7cc46 0034e1dc 00000028 d7f3a73172f436ea8a58b9 0034e204 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0034e230 00000028 d7f3a73172e233e78154bcc15a8b5e 0034e258 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0034e260 000000c0 c1e8b12d79f121ea8a5ea9 0034e320 00000028 d4e5a02d6ae030 0034e348 00000754 e1c8911649ea1cc1a1628ef148ad69abf04231159f 0034ea9c 00000344 e1c8911649ea02dcb962b7fb74af74 0034ede0 00000210 e1c8911649ea02dcba688dfb64917eb4c647372b8252d1e66d4e 0034eff0 0000007c e1c8911649ea02dcba688dfb64916fa8dc5e3e1d924bcced7c61624e77 0034f06c 000000a8 e1c8911649ea00cbb8649ced48be75b4db6e31069443cced47534e70563067 0034f114 000001c4 e1c8911649ea00cbb8649ced48be75b4db6e31069443cced474d44634a 0034f2d8 00000484 e1c8911649ea02dcba688dfb649176a9c0410d049e50ccd77451406b4a2c 0034f75c 00000084 e1c8911649ea00cba66484fe729177afdd433d06ae52d7fa6c615370453166726d13e90b 0034f7e0 0000009c e1c8911649ea07dabc67b7e979b745a2ca473b17947dc8e76a4a7876563e7b68700eef0ad2 0034f87c 00000420 e1c8911649ea05dcbc7f8dd764ad7ba8 0034fc9c 0000039c e1c8911649ea00cba66e9afe72917eafdc5a21 00350038 000003bc e1c8911649ea00cbb46f91d764ad7ba8 003503f4 00000554 e1c8911649ea1bc0a47e81fa6e9169a5ce5f 00350948 00000624 e1c8911649ea11c2b06a86d762be45b4ca4237068747dcd77c57546957 00350f6c 000000a4 e1c8911649ea07dabc67b7e979b745abc643201b837dc8e76a4a7876563e7b68700eef0ad2 00351010 000001f4 e1c8911649ea02dcba688dfb649177afdd433d06ae52d7fa6c614b6d43367b68 00351204 00000080 e1c8911649ea07dabc67b7eb7fab79adf0573d06ae46cde97461576d562b66 00351284 00000040 e1c8911649ea07dabc67b7eb7fab79adf0563d189547d6d7694b487051324a7f7009ed16 003512c4 00000194 e1c8911649ea07dabc67b7eb7fab79adf0583e12ae51ddfb6b57486c7b2a667e7d 00351458 00000088 e1c8911649ea07dabc67b7eb7fab79adf0433705844bcaed7c61436b573466 003514e0 000001e4 e1c8911649ea07dabc67b7fb72a07e99c25820069e50e7fb6150446a 003516c4 000001c0 e1c8911649ea07dabc67b7fb72a07e99cb550d07884cdbe0 00351884 00000840 e1c8911649ea07dabc67b7fb63af68b2f0583e12ae46d1fb73 003520c4 00000120 e1c8911649ea07dabc67b7fc72bd6e99c0453a11837dd4e77f5942667b367b 003521e4 0000043c e1c8911649ea07dabc67b7eb7fa175b5ca6e3f1d8350d7fa47524e6c4f 00352620 000010e8 e1c8911649ea01d7bb6880d77aa768b4c0430d18984cd3 00353708 000005c0 e1c8911649ea07dabc67b7fb6ebd6ea3c26e3b1a9e52ddfa794a4e7441 00353cc8 00000a90 e1c8911649ea07dabc67b7ee7ea07e99de443d06844fe7ec714d4c71 00354758 000017ec e1c8911649ea21ed984e 00355f44 000002e4 e1c8911649ea07dabc67b7fe76a273a2ce45372b9846e7ea7451446957 00356228 000000b8 e1c8911649ea07dabc67b7fe76a273a2ce45372b984eded7715a786048307670 003562e0 000005f8 e1c8911649ea07dabc67b7e173917ea7db500d009e7ddee67a 003568d8 00000878 e1c8911649ea07dabc67b7fa72bd6fabca6e3b18977ddce16b55 00357150 00000678 e1c8911649ea16dcbc7d8dd77ea073b2f04231159f 003577c8 00000ab8 e1c8911649ea1bca8a788be979 00358280 00000380 e1c8911649ea07dabc67b7fb74bc6fa4 00358600 00000738 e1c8911649ea00cba66484fe729176a9c0410d049e50ccd76c4c466c573661727614 00358d38 00000c7c c1e8b12d5ed601cab15485e97ea0 0035ae7c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0035ae84 00000260 e1c891175bd01cda8a6681ef65af6eafc05f 0035b0e4 000000c8 e1c891175bd01cda8a649ce072bc45a1c05f372b9f4dcce17e 0035b1ac 000000c8 e1c891175bd01cda8a649ce072bc45acc0583c11957dd6e76c5741 0035b274 000002f4 e1c891175bd01cda8a7b87f862a27bb2ca6e371d8112da 0035b568 000000a8 e1c891175bd01cda8a628cd760bc73b2ca6e36069854ddd77b56466c433a71 0035b610 00000048 e1c891175bd01cda8a6f9ae161ab45afc15e22 0035b658 0000006c c1e8b12d5fd002c1a77fb7fa78a66999cc5e3f049d4bd9e67b5b 0035b6c4 0000006c c1e8b12d5fd002c1a77fb7fb63af68b2c057301b9e56 0035b730 00000034 c1e8b12d48c317c0a1548bfb7a9172a7c1560d04834ddbed6b4d4271 0035b764 00000074 c1e8b12d48c317c0a1548ee476a96999cc59331a9647dc 0035b7d8 0000006c c1e8b12d5fd002c1a77fb7ee7baf7db5f0523a159f45ddec 0035b844 000000fc c1e8b12d48c317c0a1549beb72a27699cb543e118547dcd77651536b42 0035b96c 00000024 d7f3a73172f137e29c45a3d7539f 0035b990 0000001c d7f3a73172f03cff804eb7cc46 0035b9ac 00000028 d7f3a73172f436ea8a58b9 0035b9d4 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 0035ba00 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0035ba08 00000028 d4e5a02d6ae030 0035ba30 0000008c e1c891144eea13cdb6548de464 0035babc 0000003c c1e8b12d4bd62dcfb97b89d763a145aac05e222b9846 0035baf8 000000a0 e1c891144eea16c18a6f9ae161ab45afc15826 0035bb98 0000009c e1c891144eea16c18a7f8dfb63916fa8c6450d069443dcf1 0035bc34 000000e8 e1c891144eea16c18a6e84fb 0035bd1c 000000c4 e1c891144eea16c18a788bfb7abd7d99ca5d21 0035bde0 000000cc e1c891144eea16c18a7f8cfb 0035beac 000000e0 e1c891144eea16c18a7f8cfb48b97bafdb 0035bf8c 00000040 c1e8b12d4bd62dc8ba798bed48a275a9df6e3b1a9856 0035bfcc 00000098 e1c891144eea19c7b967b7e763a67fb4 0035c064 00000048 c1e8b12d4bd62dc2ba6483fd679174a9cb540d16887dd6e77c5b786c453270 0035c0ac 00000048 c1e8b12d4bd62dc2ba6483fd679174a9cb540d16887dc8e76a4a786b40 0035c0f4 00000070 e1c891144eea00c4a1548de464 0035c164 00000048 e1c891144eea00de8a6285f87ba779afdb6e22069e41e7e47759487750 0035c1ac 00000094 e1c891144eea00de8a6787ef70ab7e99c65f0d00984fddfa475b5f724d2d707f 0035c240 00000044 e1c891144eea00de8a6787e77cbb6a99cd480d049e50ccd7715a 0035c284 000001cc e1c891144eea00de8a6a8ce164ad45b4ca52371d8747dc 0035c450 00000064 e1c891144eea00de8a6787e77cbb6a99cd480d049e50ccd7765f4a67 0035c4b4 0000004c e1c891144eea00de8a7b8ce164ad45b4ca52371d8747dc 0035c500 000000e0 e1c891144eea00de8a7b87fa63916ea9f0413e1b964be7fb7d50535d572b746f7c 0035c5e0 000000f4 e1c891144eea00de8a689aed76ba7f 0035c6d4 000000e4 e1c891144eea00de8a7b87fa63916ea9f0443c1f9f4dcfe6474d5363503a 0035c7b8 000000d8 e1c891144eea00de8a7b84e770a745b2c65c371b8456 0035c890 000001b8 e1c891144eea00de8a7b84e770a745b4c5450d069441dde16e5b43 0035ca48 000000dc e1c891144eea00de8a6498ed79917ca7c65d3710 0035cb24 000001d0 e1c891144eea00de8a6787ef789168a3cc543b029446 0035ccf4 00000118 e1c891144eea00de8a6f8de472ba7f 0035ce0c 000000c4 e1c891144eea00de8a7b9ae161af6ea3f05d3d1b817df4c148 0035ced0 0000007c e1c891144eea06cba67fb7e678aa7f99df430d189e45dfed7c614e6c 0035cf4c 00000550 e1c891144eea07deb16a9ced48a874a4f04226158547 0035d49c 00000060 e1c891144eea00de8a7b87fa63916ea9f05d3d139647dcd771507871503e617e 0035d4fc 000001d8 e1c891144eea00de8a7b84e770a745a7cc520d069441dde16e5b43 0035d6d4 0000058c e1c891144eea00de8a7b84e770a745b4ca52371d8747dc 0035dc60 000002c4 e1c891144eea0ac3b368b7eb7aaa 0035df24 000001d0 e1c891144eea0ac3b368b7eb7aaa45b4cc4736 0035e0f4 000000bc e1c891144eea0ac3b368b7fa64be 0035e1b0 00000090 e1c891144eea0ac3b368b7fa64be45a7cc5a0d17904ed4ea795d4c 0035e240 0000007c e1c891144eea0ac3b368b7fa64be45a0c35e25 0035e334 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0035e33c 0000016c e1c8911a4fea07dabc67b7fb72a07e99c75433068540dde96c 0035e4a8 00000670 e1c8911a4fea07dabc67b7f878a27699cb433b029451 0035eb18 0000036c c1e8b12d5ed601c6b75485e97ea0 0035ef80 0000000c d7f3a73172fc3ce78154acd9 0035ef8c 00000010 d7f3a73172fc3ce78154bbd9 0035ef9c 00000028 d7f3a73172f436ea8a58b9 0035efc4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0035efcc 000008a0 c1e8b12d44db1bda 0035f86c 00000050 c1e8b12d44db1bda8a788bfb74ac 0035f8bc 000000a8 c1e8b12d44db1bda8a788fe963ab 0035f964 000000c8 c1e8b12d44db1bda8a7c9fe664 0035fa44 00000028 d7f3a73172e233e78154bcc15a8b5e 0035fa6c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0035fa74 00000c2c c1e8b12d5ed601c2b66fb7e576a774 00360920 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00360928 00000504 e1c8911f4fea07dabc67b7ea65ab7badf05c3b06834dca 00360e2c 00000194 c1e8b12d5ed601c3b75485e97ea0 003610a8 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 003610d4 00000028 d7f3a73172e233e78154bcc15a8b5e 003610fc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00361104 00000098 e1c8910255cc2dc0ba7f81ee6e9179b5c26e3d12ae52cde47451516756 0036119c 00000090 e1c8910255cc2dcaa069b7fd79b973a8cb 0036122c 00000538 c1e8b12d5ed601dead72b7e576a774 00361784 00000028 d7f3a73172e233e78154bcc15a8b5e 003617ac 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003617b4 00000100 c1e8b12d5fd003dbb0789cd773bc7799cc59331a9647e7e57946786e4b384a78780ae706d5df11 003618b4 000000d4 c1e8b12d5fd003dbb0789cd773bc7799cc59331a9647e7fa7d5f435d4b317962 00361988 00000124 c1e8b12d5fd003dbb0789cd773bc7799cc59331a9647e7fa775242 00361aac 00000170 c1e8b12d5fd003dbb0789cd773bc7799cc4337158547e7ef6a515272 00361c1c 00000204 c1e8b12d5fd003dbb0789cd773bc7799cc4337158547e7ef6a5152727b2921 00361e20 000001e8 c1e8b12d49c71ff1b46f8cd773ab69b2f05c37199347ca 00362008 0000009c c1e8b12d5fd003dbb0789cd773ab7ca3dd6e311b815b 003620a4 00000108 c1e8b12d5fd003dbb0789cd773bc7799cb542100834dc1d77f4c487754 003621ac 00000154 c1e8b12d5fd003dbb0789cd773bc7799cb542100834dc1d77f4c4877540062726d12d908d9c60a21ea54 00362300 000001a0 c1e8b12d5fd003dbb0789cd773bc7799c8433d01817ddee971524874412d 003624a0 000000a4 c1e8b12d5fd003dbb0789cd773bc7799dd543f1b8747e7fd765753 00362544 0000006c c1e8b12d5fd003dbb0789cd773bc7799dd5422069451dde66c61526c4d2b66 003625b0 00000118 c1e8b12d5fd003dbb0789cd773bc7799dc483c17ae41d9f8795d4e765d 003626c8 000001f8 c1e8b12d5fd003dbb0789cd773bc7799dc483c17ae4fd1fa6a5155 003628c0 00000200 c1e8b12d5fd003dbb0789cd773bc7799dc483c17ae51d7fd6a5d42 00362ac0 000000dc c1e8b12d5fd003dbb0789cd772a07ba4c3540d12904bd4fb795842 00362b9c 00000128 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817dd9fd6c517871512c657e771e 00362cc4 000000d8 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817ddced6b4a7872563a667e770e 00362d9c 00000144 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817ddee971525463423a 00362ee0 000001c8 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817dd7f87d4c46764d307b 003630a8 0000012c c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817dd5e77c5b 003631d4 00000190 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817dc8fa7d584270563a71447709e5 00363364 00000130 c1e8b12d5fd003dbb0789cd764ab6e99dc522410ae41d9f8795d4e765d 00363494 00000128 c1e8b12d5fd003dbb0789cd764ab6e99c8433d01817ddced7e5b555d47306562 003635bc 000003dc c1e8b12d5fd003dbb0789cd773bc7799dc483c17ae41d7e67e5740 00363998 000000dc c1e8b12d5fd003dbb0789cd773bc7799da4136158547e7e477597870412c70696f1f 00363a74 0000016c e1c8911d4fdf2dcdb4678bd770bc75b3df6e3e1b967dcbe1625b 00363be0 000000a0 e1c8911d4fdf2dcda76e89fc72917db4c044222b954dd6ed 00363c80 000003a4 e1c8911d4fdf2dcaa766b7e973aa45abca5c3011837ddee971527861483a74756c0a 00364024 0000007c e1c8911d4fdf2dcaa766b7e973aa45abca5c3011837dcce7475a427150007269760ff63adaca0128ed555d 003640a0 000003dc e1c8911d4fdf2dcaa766b7fa72be68a3dc543c00ae57d6e16c4d 0036447c 000006a0 e1c8911d4fdf2dcaa766b7eb7bab7ba8da41 00364b1c 0000031c e1c8911d4fdf2dcaa766b7fd79bf6fafca423111ae51d1fc7d4d 00364e38 0000007c e1c8911d4fdf2dc9b07fb7ef65a16fb6f0523d199c47d6fc 00364eb4 00000104 e1c8911d4fdf2dc9b07fb7ec65a345abca5c30118351 00364fb8 0000007c e1c8911d4fdf2dc9b07fb7ef65a16fb6f05c331a9045dde57d5053 00365034 00000048 e1c8911d4fdf2dc9b07fb7ef65a16fb6f05f331994 0036507c 00000150 e1c8911d4fdf2dc9b07fb7ef65a16fb6f0413711837dcbeb7d524b71 003651cc 0000007c e1c8911d4fdf2dc9b07fb7ef65a16fb6f0442111837dd6e9755b 00365248 000001c4 e1c8911d4fdf2dc9b07fb7fb74ab76aaf0523d1a9f47dbfc7151495d572b746f6c09 0036540c 000000f8 e1c8911d4fdf2dc9b07fb7fb74b87e99df54370682 00365504 000000c4 e1c8911d4fdf2dddb07fb7ef65a16fb6f05c331a9045dde57d5053 003655c8 00000864 e1c8911d4fdf2dddb07fb7ef65a16fb6f04227078147d6ec475f4b6e 00365e2c 000003c0 e1c8911d4fdf2dddb07fb7ef65a16fb6f04227078147d6ec47504875 003661ec 00000100 e1c8911d4fdf2dddb07fb7e473917eb4c26e3b1aae52cae77f4c427157 003662ec 000008b8 e1c8911d4fdf2dddb07fb7fb74b87e99cc502215924bccf1475a486c41 00366ba4 000005ec e1c8911d4fdf2dddb07fb7fb74b87e99cc502215924bccf1475248614533 00367190 00000e38 e1c8911d4fdf2dcfb16fb7fb74b87e99db5e0d079e57caeb7d6140704b2a65 00367fc8 00000774 e1c8911d4fdf2dcfb16fb7fb74b87e99db5e0d109451ccd77f4c487754 0036873c 00001474 e1c8911d4fdf2dddb07fb7fb74b87e99c8433d01817dd6e7765b 00369bb0 0000003c e1c8911d4fdf2dddac658bd765ab69a3db 00369bec 00000170 e1c8911d4fdf2dddb07fb7e478a945b4ca4237068747 00369d5c 000001d0 e1c8911d4fdf07dabc67b7eb7fab79adf05c37199347cafb475848707b3b70686d08e91c 00369f2c 000000e8 e1c8911d4fdf07dabc67b7eb7fab79adf0442111837dd6e9755b 0036a014 00000034 e1c8911d4fdf07dabc67b7eb78bb74b2f0552019ae4fdde57a5b5571 0036a048 00000040 e1c8911d4fdf07dabc67b7eb65ab7bb2ca6e3506817dd9e47451506740 0036a088 00000140 e1c8911d4fdf07dabc67b7ec7ebd79a7dd550d189551e7e1766157704b38677e6a09 0036a1c8 0000092c e1c8911d4fdf07dabc67b7ec72bd6eb4c0480d13834dcdf8475d4b674531606b 0036aaf4 00000390 e1c8911d4fdf07dabc67b7ec72ba7ba5c76e311b9c52d4ed6c5b 0036ae84 0000039c e1c8911d4fdf07dabc67b7ec72ba7ba5c76e22069452d9fa7d 0036b220 00000a44 e1c8911d4fdf2dcaa766b7fa72a375b0ca6e271a9856 0036bc64 000015cc e1c8911d4fdf2dcab0789cfa78b745a1dd5e2704 0036d230 00000214 e1c8911d4fdf07dabc67b7ee65ab7f99cb503c139d4bd6ef475954607b337a787209 0036d444 000001cc e1c8911d4fdf07dabc67b7ee65ab7f99c842302b9d4ddbe36b 0036d610 000001b8 e1c8911d4fdf07dabc67b7ef72ba45a1dd5e2704ae41d7e6765b44764d307b446a0ee711c9d8 0036d7c8 00000628 e1c8911d4fdf2dcab0789cfa78b745a1dd5e2704ae4bd6e16c 0036ddf0 000000fc e1c8911d4fdf07dabc67b7ef72ba45a1dd5e2704ae46ddfb6c614e6c403a6d 0036deec 00000280 e1c8911d4fdf2dc9b07fb7fb74b87e99cb433f2b9056ccfa 0036e16c 00000254 e1c8911d4fdf2dc9b07fb7ef65a16fb6f05c3b07927dd9fc6c4c 0036e3c0 0000095c e1c8911d4fdf07dabc67b7ef72ba45a1dc530d189e41d3fb 0036ed1c 00000138 e1c8911d4fdf07dabc67b7ef72ba45abce490d189e45e7fb714442 0036ee54 00000300 e1c8911d4fdf2dc9b07fb7eb76be7ba5c6452b2b974dcad7745140654d3172 0036f154 00000f48 e1c8911d4fdf07dabc67b7ef72ba45a1dd5e2704ae4bd6ee77 0037009c 00000094 e1c8911d4fdf2dc9b07fb7ef65a16fb6f0583c129e 00370130 00000398 e1c8911d4fdf2dc9b07fb7ef65a16fb6f05d3d13ae51cce96c5b 003704c8 000000d8 e1c8911d4fdf07dabc67b7ef72ba45abca5c3011837dd6e7715a54 003705a0 000002ec e1c8911d4fdf07dabc67b7fb72ba45a1dd5e2704ae46ddfb6c615770412c70756d 0037088c 000002ec e1c8911d4fdf07dabc67b7fb72ba45a1dd5e2704ae50dde97c61486c4826 00370b78 000003a4 e1c8911d4fdf07dabc67b7fb72ba45a1dd5e2704ae51d1fc7d6141634d337a6d7c08 00370f1c 00000118 e1c8911d4fdf07dabc67b7fb72ba45abca5c30118351e7eb794e46614d2b6c 00371034 000001ec e1c8911d4fdf07dabc67b7fb72ba45abca5c30118351e7e96c4a55 00371220 00000220 e1c8911d4fdf07dabc67b7fb72ba45abca5c30118351e7fb6c5f5367 00371440 000001fc e1c8911d4fdf2dcaa766b7eb7faf74a1ca6e20119046e7e776525e 0037163c 000001fc e1c8911d4fdf2dcaa766b7eb7faf74a1ca6e36118256e7f86a5b54674a2b 00371838 0000011c e1c8911d4fdf07dabc67b7fb72ba45abca5c30118351e7ff68 00371954 000003a4 e1c8911d4fdf07dabc67b7fb72ba45b5cc47362b9243c8e97b57537b7b3c66447f1bef09c9d90d 00371cf8 0000085c e1c8911d4fdf2dddb07fb7fb74b87e99cc502215924bccf147524865 00372554 000007f0 e1c8911d4fdf2dddb07fb7fb74b87e99cc502215924bccf1475a427150 00372d44 000001a8 e1c8911d4fdf07dabc67b7eb76ad72a3f0553300907dd4e76b4a 00372eec 00000dfc e1c8911d4fdf2dcaa766b7e973aa45abca5c3011837dcce7475a427150007269760ff6 00373ce8 00000020 e1c8911d4fdf07dabc67b7eb76ad72a3f05333008547caf147514c 00373d08 0000011c e1c8911d4fdf2dddb07fb7ef65a16fb6f0442111837dd6e9755b 00373e24 00000364 e1c8911d4fdf2dddb07fb7ef65a16fb6f05537129450e7eb774e5e5d4830767a75 00374188 00000210 e1c8911d4fdf2dddb07fb7ef65a16fb6f05537129450e7eb774e5e5d4d317c6f 00374398 00000b40 e1c8911d4fdf2dddb07fb7ef65a16fb6f04227078147d6ec 00374ed8 00000130 e1c8911d4fdf2dddb07fb7ef65a16fb6f0433715957dd7e67447786e4b3c7477 00375008 00000318 e1c8911d4fdf2dddb07fb7ef65a16fb6f0433715957dd7e67447786b4a3661 00375320 0000014c e1c8911d4fdf2dddb07fb7ef65a16fb6f0553707857dc8fa7d4d426c500079747a1bea 0037546c 00000260 e1c8911d4fdf2dddb07fb7ef65a16fb6f0553707857dc8fa7d4d426c50007c75700e 003756cc 00001258 e1c8911d4fdf2dddb07fb7ef65a16fb6f05e22118343cce17750786e4b3c7477 00376924 000001e0 c1e8b12d5fd003dbb0789cd773bc7799c95e2017947dcbf1765d 00376b04 00000194 c1e8b12d5fd003dbb0789cd773bc7799c95e2017947dcbf1765d786e4b3c7477 00376c98 00000474 e1c8911d4fdf2dcaa766b7eb7faf74a1ca6e201b9d47 0037710c 00000c3c e1c8911d4fdf2dddb07fb7ef65a16fb6f05e22118343cce17750786b4a3661 00377d48 000008a4 e1c8911d4fdf2dddb07fb7ef65a16fb6f05c3d10947dd4e77b5f4b 003785ec 0000039c e1c8911d4fdf2dddb07fb7ef65a16fb6f05c3d10947dd1e6714a 00378988 000006e8 e1c8911d4fdf2dddb07fb7ef65a16fb6f057331d9d51d9ee7d614b6d473e79 00379070 00000308 e1c8911d4fdf2dddb07fb7ef65a16fb6f057331d9d51d9ee7d614e6c4d2b 00379378 000000f8 e1c8911d4fdf2dddb07fb7ef65a16fb6f0523d199c47d6fc 00379470 00000364 e1c8911d4fdf2dddb07fb7ef65a16fb6f05027009e7dcbfd6b4e426c400079747a1bea 003797d4 00000210 e1c8911d4fdf2dddb07fb7ef65a16fb6f05027009e7dcbfd6b4e426c40007c75700e 003799e4 000002a8 e1c8911d4fdf2dc7bb7d89e47eaa7bb2ca6e3e1b96 00379c8c 00000700 e1c8911d4fdf2dcaa766b7fa72a375b0ca6e211b8450dbed4758556d4900717e6a0e 0037a38c 00000db4 e1c8911d4fdf2dcaa766b7e973aa45abca5c3011837dcce74759556d512f 0037b140 000003d0 e1c8911d4fdf2dddb07fb7e576b645aac0560d079858ddd771504e76 0037b510 00000744 e1c8911d4fdf2dddb07fb7e576b645aac0560d079858dd 0037bc54 00000178 e1c8911d4fdf07dabc67b7fa72a27bb2c65e3c2b924addeb73 0037bdcc 00000790 e1c8911d4fdf2dcda76e89fc72917db4c044222b8716 0037c55c 00000318 e1c8911d4fdf2dcda76e89fc72917db4c044222b984cd1fc474813 0037c874 00000664 e1c8911d4fdf2dcda76e89fc72917db4c04422 0037ced8 00000230 e1c8911d4fdf2dcda76e89fc72917db4c044222b984cd1fc 0037d108 00000230 e1c8911d4fdf07dabc67b7fd67aa7bb2ca6e36069c7ddffa774b5771 0037d338 00000110 e1c8911d4fdf07dabc67b7fb72ba45b5da4222119f46e7e77661546b503a4a7d7813ea0acace1a 0037d448 00000fd0 e1c8911d4fdf2dddb07fb7ef65a16fb6f0423b00947ddee971524874412d 0037fbf0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0037fbf8 00000300 e1c8911d4fdf2dcda76e89fc72917eb3 0037fef8 000001dc e1c8911d4fdf2dcab0789cfa78b745a2da 003800d4 00000158 e1c8911d4fdf2dc9b07fb7ec62917ea3d96e3b10944ccc 0038022c 00000070 e1c8911d4fdf2dc9b07fb7ec629177afdc520d158556ca 0038029c 000001d0 e1c8911d4fdf2dc9b07fb7ec62916ab3 0038046c 00000184 e1c8911d4fdf2dc9b07fb7ec62916ab3f0523d019f56 003805f0 0000007c e1c8911d4fdf2dc9b07fb7ec629169a5d955 0038066c 00000180 e1c8911d4fdf2dc9b07fb7ec629169a3db4533169d47e7e17c 003807ec 00000570 e1c8911d4fdf2dddb07fb7ec629169a3db4533169d47e7e17c 00380d5c 000006ac e1c8911d4fdf2dddb07fb7ec62916db4c645372b8150d7fc7d5d53 00381408 00000058 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e3601 00381460 00000028 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d1084 00381504 00000028 d7f3a73172e233e78154bcc15a8b5e 0038152c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00381534 000000dc d4e5a02d79fa2dfa944c 00381610 000003c8 e1c8911d4fdf2dcab0789cfa78b745b6ce43261d904ee7e47c5f43 003819d8 000001ec e1c8911d4fdf2dcab0789cfa78b745b2ca5c222b9d46d9ec 00381bc4 0000093c e1c8911d4fdf2dcab0789cfa78b745aacb5036 00382500 00001834 e1c8911d4fdf2dcda76e89fc729176a2ce55 00383d34 000002c0 e1c8911d4fdf2dc9b07fb7e473af7e99c2582117ae43ccfc6a 00383ff4 00000198 e1c8911d4fdf2dc9b07fb7e473af7e99d95e3e07 0038418c 00000280 e1c8911d4fdf2dc9b07fb7e473af7e99d95e3e07ae4bd6ee77 0038440c 000000c4 e1c8911d4fdf2dc9b07fb7e473af7e99d95e3e2b924dcde66c 003844d0 0000068c e1c8911d4fdf2dc2b16a8cd763a145a9c9573e1d9f47e7fb6c5f5367 00384b5c 000019dc e1c8911d4fdf2dc2b16a8cd763a145a9c15d3b1a947dcbfc794a42 00386538 00001e70 e1c8911d4fdf2ddcb07887e461ab45aacb50362b924dd6ec714a4e6d4a 003883a8 00000340 e1c8911d4fdf2dddb07fb7e473af7e99c1503f11 003886e8 000003b8 e1c8911d4fdf2dddb07fb7e473af7e99c0523101817dd0e16f5f536756 00388aa0 00000544 e1c8911d4fdf2dddb07fb7e473af7e99c05f3e1d9f47e7fb6c5f5367 00388fe4 000003b0 e1c8911d4fdf2dddb07fb7e473af7e99dc4133069451e7ef775f4b 00389394 0000045c e1c8911d4fdf2dddb07fb7e473af7e99dc43312b9c4ddced 003897f0 00000210 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e3e109046 00389a00 000000e8 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d189543dc 00389cc8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00389cd0 00000044 deefab2166ea3ce18154a7c65b875483f0620635a567 00389d14 0000003c c1e8af3b72e13df19658b7da528a4f88eb701c37a8 00389d50 00000704 e1c8911d4fdf2dcda76e89fc729176a2 0038a454 00000b34 e1c8911d4fdf2dddbb6a98fb7fa16e99c355 0038af88 000000c0 e1c8911d4fdf2dc9b07fb7e473917cafdd42262b8157e7e46d50 0038b048 00000074 e1c8911d4fdf2dc9b07fb7e4739176a2ce55 0038b0bc 00000040 e1c8911d4fdf2dc9b07fb7e4739168a3dc5420029056d1e776615476452b6068 0038b0fc 000000b4 e1c8911d4fdf2dc9b07fb7e4739169a5d955 0038b1b0 000000b0 e1c8911d4fdf2dc9b07fb7e4739169a8ce41211c9e56e7e96c4a55 0038b260 00000088 e1c8911d4fdf2dc9b07fb7e473916db1c655 0038b2e8 000006dc e1c8911d4fdf2dc2b1548be472af6899cc5e3c00904bd6ed6a 0038b9c4 000008f8 e1c8911d4fdf2dddb07fb7e473917db4c044222b9056ccfa 0038c2bc 00000404 e1c8911d4fdf2dddb07fb7e4739175a8c3583c11ae51cce96c5b 0038c6c0 00000360 e1c8911d4fdf2dddb07fb7e473916db1c655 0038ca20 00000660 e1c8911d4fdf07dabc67b7e963ba7ba5c76e211a9052e7ec775042 0038d080 00000278 e1c8911d4fdf07dabc67b7e963ba7ba5c76e211a9052e7ee79574b77563a 0038d2f8 00000034 e1c8911d4fdf07dabc67b7eb7bab7bb4f052212b9d46e7ec794a465d4830666f 0038d32c 000007c8 e1c8911d4fdf07dabc67b7eb7bab7bb4f05d362b9543cce94752487150 0038daf4 000003b0 e1c8911d4fdf07dabc67b7eb7bab7bb4f05d362b9543cce94752487150007174771f 0038dea4 000000c4 e1c8911d4fdf07dabc67b7eb7bab7bb4f05d362b9543cce9475248715000637e6b13e01c 0038df68 00000b0c e1c8911d4fdf2dcdb96e89fa48a27e99cb502615ae4ed7fb6c 0038ea74 00000134 e1c8911d4fdf07dabc67b7ef72ba45aacb6e311b9f46d1fc715149 0038eba8 000001cc e1c8911d4fdf2dc9b07fb7e4739177afdc520d158556ca 0038ed74 00000928 e1c8911d4fdf2dcab0789cfa78b745aacb 0038f69c 000002f4 e1c8911d4fdf07dabc67b7e4739177afdd433d06ae41d4e7765b78644536796e6b1f 0038f990 0000007c e1c8911d4fdf07dabc67b7e4739168a3dc453d06947ddbe07d5d4c717b397472751fe2 0038fa0c 0000030c e1c8911d4fdf07dabc67b7e4739168a3dc453d06947ddee97152527041 0038fd18 000005cc e1c8911d4fdf07dabc67b7e4739168a3dc453d06947dcbfc794c53 003902e4 000001ec e1c8911d4fdf07dabc67b7e4739168a3dc453d06947dcbfc774e78675c36666f7014e1 003904d0 00000a28 e1c8911d4fdf2dc2b1549aed64ba75b4ca 00390ef8 000002f0 e1c8911d4fdf07dabc67b7fb72ba45aacb6e3f1d8241e7e96c4a55 003911e8 00000058 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e3e10 00391240 00000028 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d1895 00391268 000008d4 e1c8911d4fdf2dcdbd60b7fb79af6a99c355 00391b3c 00000b8c e1c8911d4fdf2dc2b15485e165bc75b4f0523e1b9f47 003926c8 000010c8 e1c8911d4fdf2dcfa17f89eb7f9169a8ce4121 00393b78 00000028 d7f3a73172e233e78154bcc15a8b5e 00393ba0 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 00393ba8 00000060 fcdd8f1740d602d7 00393c08 00000070 e1c8911d4fdf2dcda76a9be048a069a5 00393c78 00000430 e1c8911d4fdf2dc8bc73b7ec65a76ca3 003940a8 0000006c e1c8911d4fdf2dc9b07fb7e664ad45a0cc6e3100897dd1ec 00394114 000000d8 e1c8911d4fdf2dc9b07fb7e664ad45a0cc6e221b8356e7e1765848 003941ec 000000f4 e1c8911d4fdf2dc9b07fb7e664ad45aece4336039050ddd77150416d 003942e0 000000bc e1c8911d4fdf2dc9b07fb7e664ad45aedf6e261b814dd4e77f47 0039439c 00000060 e1c8911d4fdf2dc9b07fb7e664ad45afcb6e33008550 003943fc 000001a4 e1c8911d4fdf2dc9b07fb7e664ad45aac05e222b814dcafc475749644b 003945a0 00000200 e1c8911d4fdf2dc9b07fb7e664ad45aac05e222b8151cce76a5b54 003947a0 00000064 e1c8911d4fdf2dc9b07fb7e664ad45aac05e222b8151e7eb774b4976 00394804 0000005c e1c8911d4fdf2dc9b07fb7e664ad45abc642312b9056ccfa 00394860 000000c4 e1c8911d4fdf2dc9b07fb7e664ad45a9db593706ae51cce96c5b 00394924 00000044 e1c8911d4fdf2dc9b07fb7e664ad45b5cc543e18 00394968 000000a4 e1c8911d4fdf2dc8a76e8dd779bd7999da5f3307824bdfe67d5a786a542c 00394a0c 00000190 e1c8911d4fdf2dc9b07fb7e664ad45b3c15021079845d6ed7c614f7257 00394b9c 00000120 e1c8911d4fdf2dc9b07fb7e664ad45b3c15021079845d6ed7c614f72570076746c14f2 00394cbc 000001f4 e1c8911d4fdf2dc9b07fb7e664ad69 00394eb0 000000d0 e1c8911d4fdf2dc9b07fb7e664ad6999cc5e271a85 00394f80 000003e0 e1c8911d4fdf2dc9b07fb7e664ad45b6c748211d9243d4d76b4a4870412c4a72771ce9 00395360 00004de4 e1c8911d4fdf2dc3b46286fc48a774b0f0523d199c43d6ec 0039a144 00001184 c1e8b12d42d718f1a5798df876bc7f99c142312b824acdfc7c51506c 0039b2c8 00000210 e1c8911d4fdf2dddb07fb7e664ad45a1c35e30159d7dd0f8474a48724b337a7c60 0039b4d8 000000d8 e1c8911d4fdf2dddb07fb7e664ad45aedf6e261b814dd4e77f47 0039b5b0 00000264 c1e8b12d42d718f1a6639dfc73a16da8f05f2117 0039b814 00000030 e1c8911d4fdf2dddbd7e9cec78b97499dc5937188747cbd77b5f4b6e463e7670 0039b844 000001d0 e1c8911d4fdf2dc0a668b7fb7fbb6ea2c0463c2b824adde47e614563502b706960 0039ba14 0000002c e1c8911d4fdf2dcdbd60b7e576a774b2f0583c029e49dd 0039ba40 00000024 e1c8911d4fdf2dcdbd60b7e478a16a99c1443f169450 0039c7f4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0039c7fc 000000dc d4e5a02d79fa2dfa944c 0039c8d8 0000027c e1c8911d4fdf2dcdb96e89fa48be6999c9503b189446 0039cb54 0000021c e1c8911d4fdf2dc9b07fb7f864917ea9d85f3e1b9046e7eb7750436b50367a75 0039cd70 000000bc e1c8911d4fdf2dc9b07fb7f8649176b3c1 0039ce2c 0000017c e1c8911d4fdf2dc9b07fb7f8649177afdc520d158556ca 0039cfa8 000000c0 e1c8911d4fdf2dc9b07fb7f8649173a8de6e36158543 0039d068 00000108 e1c8911d4fdf2dc9b07fb7f864916aa2 0039d170 0000010c e1c8911d4fdf2dc9b07fb7f864916ca9c3 0039d27c 000000bc e1c8911d4fdf2dc9b07fb7f864916ca9c36e3e109046 0039d338 000000c0 e1c8911d4fdf2dc9b07fb7f864916ca9c36e2117944ed4 0039d3f8 000000d0 e1c8911d4fdf2dc9b07fb7f864916ca9c36e2117944ed4d7765f4a67 0039d4c8 00000410 e1c8911d4fdf2ddea6549beb65bb7899d95e3e 0039d8d8 00000518 e1c8911d4fdf07dabc67b7f8649179aaca50202b9c43d1e66c5b49634a3c70447415e200 0039ddf0 00000904 e1c8911d4fdf2dddb07fb7f8649177a7c65f26119f43d6eb7d614a6d403a 0039e78c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0039e794 00000a98 e1c8911d4fdf2dcda76e89fc72916ab3 0039f22c 000002c8 e1c8911d4fdf2dcab0789cfa78b745b6da 0039f4f4 0000007c e1c8911d4fdf2dc9b07fb7f862917eb3 0039f570 00000088 e1c8911d4fdf2dc9b07fb7f8629176a2 0039f5f8 00000078 e1c8911d4fdf2dc9b07fb7f8629177afdc520d158556ca 0039f670 0000007c e1c8911d4fdf2dc9b07fb7f8629169a5cc5d 0039f6ec 0000073c e1c8911d4fdf2dddb07fb7f8629176b3c1 0039fe28 00000058 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e2201 0039fe80 00000028 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d0484 0039ff4c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 0039ff54 0000055c e1c8911d4fdf2dcda76e89fc729168abdb5f3d1094 003a04b0 00000684 e1c8911d4fdf2dcab0789cfa78b745b4c2453c1b9547 003a0b34 0000009c e1c8911d4fdf2dc9b07fb7fa7aba74a9cb540d199851dbd7794a5370 003a0bd0 000000f4 e1c8911d4fdf2dc9b07fb7fa7aba74a9cb540d049056d0d76b4a4676512c 003a0cc4 00000318 e1c8911d4fdf2ddcb87f86e773ab45b6da433511 003a0fdc 00000450 e1c8911d4fdf2dddb07fb7fa7aba74a9cb540d049e50ccd7684c4264 003a14b4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003a14bc 0000089c e1c8911d4fdf2dcfb16fb7fb74ad7699df5e2000ae55cfe6 003a1d58 000000ec e1c8911d4fdf2dcda76e89fc729169a5cc5d 003a1e44 000003d8 e1c8911d4fdf2dcab0789cfa78b745b5cc523e 003a221c 00000458 e1c8911d4fdf2dc9b07fb7fb74ad7699cc5d3b119f56e7eb77504971 003a2674 00000224 e1c8911d4fdf2dc9b07fb7fb74ad7699cc5d3b119f56e7eb775049717b3c7a6e770e 003a2898 000000b0 e1c8911d4fdf2dc9b07fb7fb74ad7699cc5d3b119f56e7e5775a42 003a2948 0000008c e1c8911d4fdf2dc9b07fb7fb74ad7699c1503f11 003a29d4 00000114 e1c8911d4fdf2dc9b07fb7fb74ad7699df5e2000ae55cfe66b 003a2ae8 00000050 e1c8911d4fdf2dc9b07fb7fb74ad7699df5e2000ae55cfe66b61446d513161 003a2b38 000005d8 e1c8911d4fdf2ddcb06687fe729169a5cc5d0d049e50ccd76f4949 003a3110 000004a0 e1c8911d4fdf2ddcb06687fe729169a5cc5d0d049e50ccd77a4778755331 003a35b0 000004dc e1c8911d4fdf2dddb07fb7fb74ad7699cc5d3b119f56e7e5775a42 003a3a8c 000000a8 e1c8911d4fdf2dddb07fb7fb74ad7699c1503f11 003a3d00 00000028 d7f3a73172e233e78154bcc15a8b5e 003a3d28 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003a3d30 00000210 e1c8911d4fdf2dcfb96787eb76ba7f99db5035 003a3f40 0000003c e1c8911d4fdf2dcdb96e89e648bd79a3c35d0d00944fc8d7775c4d 003a3f7c 00002420 e1c8911d4fdf2dcda76e89fc729169a5ca5d3e 003a639c 0000079c e1c8911d4fdf2dcab0789cfa78b745b5cc543e18 003a6b38 00000018 e1c8911d4fdf2dc9b07fb7fb74ab76aaf052332b974ee7fc7153426d512b 003a6b50 00000024 e1c8911d4fdf2dc9b07fb7fb74ab76aaf0553702ae43ccfc6a 003a6b74 00000208 e1c8911d4fdf2dc9b07fb7fb74ab76aaf056201b8452e7e1765848 003a6d7c 000001e0 e1c8911d4fdf2dc9b07fb7fb74ab76aaf05d3d139841d9e4475a4e714f2c4a72771ce9 003a6f5c 00000060 e1c8911d4fdf2dc9b07fb7fb74ab76aaf05c3b07927dd9fc6c4c 003a6fbc 00000120 e1c8911d4fdf2dc9b07fb7fb74ab76aaf05f3319947dcbfc6a574965 003a70dc 00000080 e1c8911d4fdf2dc9b07fb7fb74ab76aaf0423317957dcbed6c4a4660483a4a727d 003a715c 00000068 e1c8911d4fdf2dc9b07fb7fb74ab76aaf05c33078547cad7764d44 003a71c4 00000050 e1c8911d4fdf2dc9b07fb7fb74ab76aaf0453b1994 003a7214 0000005c e1c8911d4fdf2dc2ba6483fd679175a4c5 003a7270 00000050 e1c8911d4fdf2dc2ba6483fd679175a4c56e311b844ccc 003a72c0 000000ac e1c8911d4fdf2dc0ba628cd763a145b2ce56 003a736c 000003f8 e1c8911d4fdf2dddb07fb7fb74ab76aaf052332b974ee7fc7153426d512b 003a7764 000003e4 e1c8911d4fdf2dddb07fb7fb74ab76aaf0523d199c43d6ec475248614f007c757f15 003a7b48 00000410 e1c8911d4fdf2dddb07fb7fb74ab76aaf05537129057d4fc474d5561 003a7f58 0000043c e1c8911d4fdf2dddb07fb7fb74ab76aaf0553702ae43dcec474e486e 003a8394 0000025c e1c8911d4fdf2dddb07fb7e664ad45b6ce4221039e50dc 003a85f0 000003c8 e1c8911d4fdf2dddb07fb7fb74ab76aaf0573f2b984cdee7 003a89b8 000003c8 e1c8911d4fdf2dddb07fb7fb74ab76aaf0593d07857dd5e77c5b78614b3161697616 003a8d80 000005a4 e1c8911d4fdf2dddb07fb7fb74ab76aaf05f3319947dcbfc6a574965 003a9324 000003e8 e1c8911d4fdf2dddb07fb7fb74ab76aaf0423317957dcbed6c4a4660483a4a727d 003a970c 00000040 e1c8911d4fdf2dddb07fb7fb74ab76aaf0453b1994 003a974c 000003c8 e1c8911d4fdf2dddb07fb7fb74ab76aaf0473d18ae50ddf8475a426e4526 003a9b14 0000030c e1c8911d4fdf2ddba56f89fc729169a5ca5d3e2b9e40d2d76b4a467641 003a9e20 00000180 e1c8911d4fdf2ddba0628cd763a145b2ce56 003a9fa0 00000104 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e2117944ed4 003aa0a4 0000008c e1c8911d4fdf2dcdbd60b7f048bd79a3c35d0d0c 003aa130 00000040 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d079247d4e4 003aa170 000001cc e1c8911d4fdf2dd8b46781ec76ba7f99cc4337158547 003aa590 00000028 d7f3a73172e233e78154bcc15a8b5e 003aa5b8 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003aa5c0 00000168 e1c8911d4fdf2dcda76e89fc729169a5d955 003aa728 00000150 e1c8911d4fdf2dcab0789cfa78b745b5cc4736 003aa878 0000035c e1c8911d4fdf2dcabc7889ea7bab45b5cc4736 003aabd4 00000384 e1c8911d4fdf2dcbbb6a8ae4729169a5d955 003aaf58 000001d0 e1c8911d4fdf2dc9b07fb7fb74b87e99cb4421 003ab128 00000170 e1c8911d4fdf2dc9b07fb7fb74b87e99cb44212b924dcde66c 003ab298 00000074 e1c8911d4fdf2dc9b07fb7fb74b87e99c355 003ab30c 000000c8 e1c8911d4fdf2dc9b07fb7fb74b87e99c2582117ae43ccfc6a 003ab3d4 00000a00 e1c8911d4fdf2dddb07fb7fb74b87e99cc50311c947dc8e77457447b 003abdd4 000001c8 e1c8911d4fdf2dddb07fb7fb74b87e99c355 003abf9c 000000ac e1c8911d4fdf2dddb07fb7fb74b87e99c1503f11 003ac048 00000094 e1c8911d4fdf07dabc67b7fb74b87e99c6420d048347cbed764a4266 003ac0dc 00000268 e1c8911d4fdf07dabc67b7fb72ba45b5cc47362b9243c8e97b57537b7b297069701cff 003ac344 0000108c e1c8911d4fdf2dddb07fb7fb74b87e99cc502215924bccf1 003ad3d0 00000058 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e21178746 003ad428 00000028 e1c8911d4fdf2dcdbd60b7ec72bd6eb4c0480d079254dc 003ad544 00000024 d7f3a73172f137e29c45a3d7539f 003ad568 00000028 d7f3a73172f436ea8a58b9 003ad590 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003ad598 00000140 e1c8911d4fdf2dcfb96787eb76ba7f99cb4430 003ad6d8 00000140 e1c8911d4fdf2dcab06a84e478ad7bb2ca6e360193 003ad818 00000074 e1c8911d4fdf07dabc67b7ea62a36a99dc5237189d7ddbfc60614e66 003ad88c 00000214 e1c8911d4fdf07dabc67b7eb7fab79adf05d3d13ae41d9f8795d4e765d 003adaa0 00000074 e1c8911d4fdf07dabc67b7eb7bab7ba8f0453719817dcce97f4d 003adb14 000004a4 e1c8911d4fdf07dabc67b7eb65ab7bb2ca6e2615967dd4e16b4a7863512b7a 003adfb8 000000f8 e1c8911d4fdf07dabc67b7eb78a36ab3db540d068251e7e177614a635734 003ae0b0 0000053c e1c8911d4fdf07dabc67b7ec72a27fb2ca6e3c118647cad76b50467257 003ae5ec 00000108 e1c8911d4fdf07dabc67b7ec72bd6eb4c0480d049050cce17952786e40 003ae6f4 00000140 e1c8911d4fdf07dabc67b7ec72bd6eb4c0480d049050cce179527871473a7977 003ae834 000001d0 e1c8911d4fdf07dabc67b7ec72ba7fb4c2583c11ae40ddfc6c5b555d562c66447f13f2 003aea04 000000e0 e1c8911d4fdf07dabc67b7ec72ba7fb4c2583c11ae50ddec6d5043634a3c6c447014e915 003aeae4 00000224 c1e8b12d42d718dba16284d773ab6ea3dd5c3b1a947ddbe4794d545d543e677a741ff200ced8 003aed08 000002a4 e1c8911d4fdf07dabc67b7ec72ba7fb4c2583c11ae51d0e76a4a7861483e6668460ae717ddc60d30fd554b 003aefac 00000054 e1c8911d4fdf07dabc67b7ef72ba45a7c95737178547dcd7715048727b2f677e7d 003af000 00000038 e1c8911d4fdf07dabc67b7ef72ba45a7c95737178547dcd7715048727b2c60787a 003af038 000002b8 e1c8911d4fdf07dabc67b7ef72ba45aacb50362b8250dbd76b4a467641 003af2f0 00000440 e1c8911d4fdf07dabc67b7eb7fab79adf0422017ae41d7e66b57547641317662 003af730 00000418 e1c8911d4fdf07dabc67b7e973aa45b0c05d0d009e7dd4ec795a 003afb48 0000030c e1c8911d4fdf07dabc67b7e179b87baac6553300947dd6ed6f5b555d5731746b6a 003afe54 00000b20 e1c8911d4fdf07dabc67b7e473916ea9f05f3715834ed1e67d615476452b70 003b0974 00000278 e1c8911d4fdf07dabc67b7e473916ea9f05e3c18984cddd76b4a467641 003b0bec 00000120 e1c8911d4fdf07dabc67b7e576a57f99c65f3b009843d4d76a4d54 003b0d0c 00001378 e1c8911d4fdf07dabc67b7eb65ab7bb2ca6e3b1a9856d1e974615571572c 003b2084 0000073c e1c8911d4fdf07dabc67b7e973aa45abda5d262b874dd4fb474a485d483b747f 003b27c0 000000fc e1c8911d4fdf07dabc67b7e576a57f99d95e3e019c47 003b28bc 00000e10 e1c8911d4fdf07dabc67b7e576bc68bff0523a119249 003b36cc 000000c0 c1e8b12d42d718dba16284d779a173a2f0453d2b9e40d2d77b52467157 003b378c 000005a8 e1c8911d4fdf07dabc67b7eb7fab79adf0453313 003b3d34 0000009c e1c8911d4fdf07dabc67b7eb7fab79adf0453313ae4cd7d76b5d546146 003b3dd0 0000045c e1c8911d4fdf07dabc67b7eb7fab79adf04231079240 003b422c 0000023c e1c8911d4fdf07dabc67b7fa72be75b4db6e271a9856e7ee79574b6d523a67 003b4468 000009ec e1c8911d4fdf07dabc67b7f865a179a3dc420d069441d7fe7d4c5e5d563a76746b1e 003b4e54 00000080 e1c8911d4fdf07dabc67b7f8649169a3ca5f0d1b9f7ddae76c56 003b4ed4 000000d8 e1c8911d4fdf07dabc67b7fa72a375b0ca6e3601937ddefa7753786f4132 003b4fac 00000128 e1c8911d4fdf07dabc67b7fa72a375b0ca6e3c01937ddefa7753786f4132 003b50d4 00000068 e1c8911d4fdf07dabc67b7fa72a375b0ca6e2207ae44cae775615461573b77 003b513c 000000cc e1c8911d4fdf07dabc67b7fa72a375b0ca6e26119c52e7fc7959 003b5208 0000016c e1c8911d4fdf07dabc67b7fa72a375b0ca6e241b9d7ddefa77537871472c7179 003b5374 000007fc e1c8911d4fdf07dabc67b7fa64bd45a2dd503400 003b5b70 00000b00 e1c8911d4fdf07dabc67b7fb72a27fa5db6e3c11867ddcfa7148425d562c66 003b6670 00000270 e1c8911d4fdf07dabc67b7fb72ba45a2dd582411ae40cae7735b49 003b68e0 000000ec e1c8911d4fdf07dabc67b7fb72ba45b4dc420d1d9e7dd5e96b55 003b69cc 0000015c e1c8911d4fdf07dabc67b7fb6ea079aedd5e3c1d8b47e7fc7d53575d503e72 003b6b28 00000228 e1c8911d4fdf07dabc67b7fc72bd6e99dd42212b974dcad7755b55654100672a461fe816c9d90d 003b6d50 00000234 e1c8911d4fdf07dabc67b7fc72bd6e99dd42212b974dcad7755b556541 003b6f84 00000180 e1c8911d4fdf07dabc67b7fe72bc73a0d66e211a9052e7fa7d5246764d307b687113f616 003b7104 000001b0 e1c8911d4fdf07dabc67b7f272bc7599cd53202b8256d9fc7d615363463370 003b72b4 00000078 e1c8911d4fdf07dabc67b7f272bc7599c3550d1b9348 003b7650 00000028 d7f3a73172e233e78154bcc15a8b5e 003b7678 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003b7680 000000dc d4e5a02d79fa2dfa944c 003b775c 000000cc e1c8911d4fdf2dcdbd6a86ef72916ca9c36e3b1a8257deee 003b7828 000000b8 e1c8911d4fdf2dcdb96e89fa48b875aaf057331d9d7dc8fa7d5a 003b78e0 00001188 e1c8911d4fdf2dcda76e89fc72916ca9c3 003b8a68 0000000c e1c8911d4fdf2dc8b46284d761a17699c2582107984cdfd77a524c71 003b8a74 00000090 e1c8911d4fdf2dc9b07fb7fe78a245aacb5036 003b8b04 000000a8 e1c8911d4fdf2dc9b07fb7fe78a245b6dc 003b8bac 000001d0 e1c8911d4fdf2dc9b07fb7fe78a245abc642312b9056ccfa 003b8d7c 00000fcc e1c8911d4fdf2dc7bb788dfa639177b3c3450d029e4ecb 003b9d48 000017f8 e1c8911d4fdf2dddb07fb7fe78a245b4ca400d018243dfed 003bb540 00000228 e1c8911d4fdf2dcdbd60b7eb65ab7bb2ca6e241b9d 003bb768 000000f4 e1c8911d4fdf2dcdbd60b7e179bd7fb4db6e3f019d56e7fe775254 003bb85c 00000134 e1c8911d4fdf2dcdbd60b7fb72ba45b0c05d0d069453e7fd6b5f4067 003bba74 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003bba7c 0000036c e1c891014ec616cc8a6a9aed769173a8cb542a2b854de7f87959425d4b3973687c0e 003bbde8 000001fc e1c891014ec616cc8a6887e57aa76e99dc522110937ddbe07950406757 003bbfe4 0000014c e1c891014ec616cc8a6887e663bc7ba5db6e21178246dad77b5f446a41 003bc130 0000013c e1c891014ec616cc8a6f81fa63b745b5cc423616ae52d9ef7d 003bc26c 00000164 e1c891014ec616cc8a6d9aed729169a5dc55302b8143dfed 003bc3d0 0000002c e1c891014ec616cc8a6c8dfc48be7ba1ca6e3d129751ddfc 003bc3fc 00000314 e1c891014ec616cc8a6286e1639169a5dc5530 003bc710 00000084 e1c891014ec616cc8a7b89ef72916bb5ce 003bc794 00000080 e1c891014ec616cc8a7b89ef729169b7f0402115 003bc814 000000cc e1c891014ec616cc8a6c8dfc48bd6b99dc522110937dc8e97f5b 003bc8e0 000000bc e1c891014ec616cc8a798de9739179b5c24320 003bc99c 000000bc e1c891014ec616cc8a7c9ae163ab45a5dc5c2006 003bca58 0000015c e1c891014ec616cc8a7c9ae163ab45b5cc423616ae47d6fc6a47 003bcbb4 00000280 e1c891014ec616cc8a6c8dfc48bd79b5cb530d049045dd 003bce34 00000314 e1c891014ec616cc8a6a84e478ad7bb2ca6e261596 003bd148 00000158 e1c891014ec616cc8a6887fd79ba45b5cc423616ae4ddae26b 003bd2a0 00000264 e1c891014ec616cc8a6d8dfc74a645b5cc423616ae56d9ef6b 003bd504 00000178 e1c891014ec616cc8a6d84fd64a645b5cc423616ae52d9ef7d 003bd67c 0000021c e1c891014ec616cc8a7f9ae979bd7ca9dd5c0d02c41388b847514568413c6168 003bd898 00000570 e1c891014ec616cc8a7f9ae979bd7ca9dd5c0d02c4128ab847514568413c6168 003bde08 00000550 e1c891014ec616cc8a7f9ae979bd7ca9dd5c0d02c27dd7ea725b447657 003be358 000001b4 e1c891014ec616cc8a7e98ef65af7ea3f04231079540 003be50c 00000378 e1c891014ec616cc8a798de97ba760a3f04231079540 003be884 000000d0 e1c891014ec616cc8a7f8de567916ea7c86e261bae52ddfa755f49674a2b 003be954 000000c8 e1c891014ec616cc8a798de578b87f99db5035 003bea1c 000002c0 e1c891014ec616cc8a798de578b87f99ce5d3e2b8547d5f8474a466557 003bef18 00000024 d7f3a73172f137e29c45a3d7539f 003bef3c 0000001c d7f3a73172f03cff804eb7cc46 003bef58 00000028 d7f3a73172f436ea8a58b9 003bef80 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 003befac 00000028 d7f3a73172e233e78154bcc15a8b5e 003befd4 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003befdc 00000060 fcdd8f1740d602d7 003bf03c 00000028 d4e5a02d6ae030 003bf064 000000dc c1e8b12d4cd91ec1b65481e67eba45b5cc423116 003bf140 0000007c c1e8b12d4cc006c1b36a81e475af79adf0443c1d8551 003bf1bc 00000088 c1e8b12d4fd406dab07991d764ba7bb2ca6e311c904cdfed7c 003bf244 00000064 c1e8b12d59d01fdeb07989fc62bc7f99dc453300947ddbe079504067 003bf2a8 00000094 c1e8b12d4edd13c0b26eb7fe78a245afc142271297 003bf33c 00000094 c1e8b12d4edd17cdbe548ee7659173a8dc45331a857dcaed6b4a487041 003bf3d0 00000090 c1e8b12d4edd17cdbe549afb649177a3c2533706ae44d9e1745b43 003bf460 0000009c c1e8b12d4eda16cb8a6787e9739168a3c3543307947ddcfa714842 003bf4fc 00000190 c1e8b12d4eda16cb8a6787e9739168a3dc542002947ddcfa714842 003bf68c 00000088 c1e8b12d4eda16cb8a6787e9739168a3dc542002947dd1e6474e556d432d70686a 003bf714 00000088 c1e8b12d4eda16cb8a6787e973916fb5ce5637 003bf79c 00000050 c1e8b12d49d013c2b9648bd764ad69a5cd 003bf7ec 000000e8 c1e8b12d4cd91ec1b6549ce970 003bf8d4 00000108 c1e8b12d49c704f1bc6581fc48ad7baac35333179a 003bf9dc 00000348 c1e8b12d49c71bd8b05481e678be 003bfd24 000004f4 c1e8b12d48d901f1b16486ed48ad7baac35333179a 003c0218 00000110 c1e8b12d4fd901f1a76e8bed7eb87fa2 003c0328 0000007c c1e8b12d4fd901f1a77898d773a174a3f05233189d40d9eb73 003c03a4 00000100 c1e8b12d48d901f1a77898d773a174a3f05233189d40d9eb73 003c04a4 00000058 c1e8b12d49c71bd8b05484ed739179a7c35d30159249 003c04fc 00000048 c1e8b12d48d817dcb26e86eb6e917ea0d86e25159856 003c0544 000000a4 c1e8b12d4bd907ddbd549de67eba45a7dc483c17997ddbe9745245634734 003c05e8 00000044 c1e8b12d4bda00cdb0548ae974a57fa8cb6e361d8241d7fe7d4c5e 003c062c 000000e0 c1e8b12d4ad01ccba76a9ced48bb6fafcb 003c070c 000000a4 c1e8b12d4ad406cb8a6889e47bac7ba5c4 003c07b0 000000d4 c1e8b12d4ad006f1a27c86d767a173a2 003c0884 0000009c c1e8b12d4ad006f1b46798e948a96fa4 003c0920 00000044 c1e8b12d4ad006f1b3658ad770bb78 003c0964 00000014 c1e8b12d4ad006f1b96fb7f865ab7e 003c0978 00000014 c1e8b12d4ad006f1b96fb7fb62ad79 003c098c 00000100 c1e8b12d4bd907ddbd549de67eba45a7dc483c17997dd5fd744a4e5d473e79777b1be50e 003c0a8c 000000d0 c1e8b12d4ad006f1bb648ced79af77a3f0562716 003c0b5c 00000050 c1e8b12d4ad006f1bb788bd774a174a2c6453b1b9f 003c0bac 0000005c c1e8b12d4ad006f1bb788bd77ba175b6f05836 003c0c08 00000050 c1e8b12d4ad006f1bb788bd767af68b2c6523b049056d1e776 003c0c58 0000005c c1e8b12d4ad006f1bb788bd763a16aa9c35e350d 003c0cb4 00000010 c1e8b12d4ad006f1a5649afc48a774a2ca49 003c0cc4 0000002c c1e8b12d4ad006f1a16a9aef72ba45afcb 003c0cf0 000001f8 c1e8b12d4ad006f1a06581fc48a37bb5db5420 003c0ee8 000000d8 c1e8b12d41d401da8a6c89fb679168a5d955 003c0fc0 00000170 c1e8b12d41d616f1a6689afd759168a3de44370785 003c1130 00000094 c1e8b12d41d12dcdb96e89fa48ad75a8db503b1a9450e7ec775042 003c11c4 00000094 c1e8b12d41d12dcda76e89fc72917ea9c154 003c1258 00000074 c1e8b12d41d12dcda76e89fc729169bfc1523a2b954dd6ed 003c12cc 00000094 c1e8b12d41d12dcab0678dfc72917ea9c154 003c1360 000000b4 c1e8b12d41d12ddcb0789ce765ab45a2c05f37 003c1414 00000094 c1e8b12d41d12dddb07fb7eb76be7ba5c6452b2b954dd6ed 003c14a8 00000220 c1e8b12d41d11c 003c16c8 00000084 c1e8b12d41d004cbb96286ef48ad77b6c345 003c174c 00000204 c1e8b12d41da1dde8a6d89e17b 003c1950 000000dc c1e8b12d46dc1ec28a649ce072bc45b4cc4736 003c1a2c 000000c4 c1e8b12d41c002 003c1af0 000000f8 c1e8b12d40d62dcab07f89eb7f917ea9c154 003c1be8 000000a4 c1e8b12d40d62dc8a76a8bfc62bc7f99cb5e3c11 003c1c8c 00000094 c1e8b12d40d62ddcb07891e674917ea9c154 003c1d20 000000c0 c1e8b12d40d000c9b0548be567a26e 003c1de0 0000016c c1e8b12d43da1bca8a7f87d763af7d 003c1f4c 00000028 c1e8b12d43da06c7b372b7ec65a76ca3f05c33048147dc 003c1f74 000004a0 c1e8b12d42c11acba7548be779ba68a9c35d3706ae45d7e67d 003c2414 00000078 c1e8b12d41d401da8a6c89fb679168a5d9550d05844bddfb7b5b43 003c248c 00000cbc c1e8b12d48d901f1a76e8bed7eb87fa2 003c3148 000001f4 c1e8b12d5dda1ec28a6984e774a5 003c333c 00000080 c1e8b12d5dc71bc0a15481e471917eafdc5a0d189e41d9fc715149 003c33bc 00000080 c1e8b12d5dc01ec2ba7d8dfa48bb74afdb 003c343c 0000009c c1e8b12d5cc01bcba6688dd773ab6cafcc54 003c34d8 0000013c c1e8b12d5cc01bcba6688dd77aa879b5 003c3614 00000088 c1e8b12d5cc01bcba6688dd762a073b2f05c3b06834dcad77b5f4b6e463e7670 003c369c 000000b0 c1e8b12d5fd013ca8a659beb48be7bb5dc463d0695 003c374c 000001d8 c1e8b12d5fd016c7a66887fe72bc45a2dd582411 003c3924 00000094 c1e8b12d5fd015cbbb548be472af74b3df6e3119814ecc 003c39b8 000000c0 c1e8b12d5fd015cbbb548cd774a36aaadb 003c3a78 000000d0 c1e8b12d5fd002c2b4688dd7739179abdf5d26 003c3b48 00000044 c1e8b12d5fd001dab4799cd774bd45abca43351182 003c3b8c 000000bc c1e8b12d5fd806c0ba6f8dd779ab7fa2ca55 003c3c48 00000064 c1e8b12d5fd806c0ba6f8dd767bb68a1ca6e3c119446ddec 003c3cac 0000010c c1e8b12d5fc601f1b86e9aef729169b6c358262b924fc8e46c 003c3db8 00000104 c1e8b12d5ed601cdb7548efd79ad 003c3ebc 000000cc c1e8b12d45c52dddb07fb7fb74ab76aaf0423317957dcbed6c4a4660483a4a727d 003c3f88 000000c0 c1e8b12d45c52dc9b07fb7fb74ab76aaf0423317957dcbed6c4a4660483a4a727d 003c4048 00000144 c1e8b12d5ed006f1b17981fe729178b4c05a37 003c418c 000000ac c1e8b12d5ed006f1a578b7eb78a07eafdb583d1a 003c4238 00000054 c1e8b12d5ed006f1b366b7e179a875 003c428c 000000c4 c1e8b12d5ed813dca1548dfe72a06e 003c4350 00000084 c1e8b12d5edb13de8a6f8de472ba7f99cc5c221885 003c43d4 00000074 c1e8b12d5ec113c9b26e9aed739168a3dc483c17 003c4448 00000114 c1e8b12d59d101f1b16486ed48ad7baac35333179a 003c455c 000000ec c1e8b12d59d101f1a26a81fc48aa75a8ca6e31159d4edae97b55 003c4648 00000088 c1e8b12d59c606f1a76e89ec6e9179a7c35d30159249 003c46d0 000000e8 c1e8b12d58db1bda8a678cd773af6ea7f05d3d07857dd1e6774e 003c47b8 000000d8 c1e8b12d58db1bda8a649eed65ad75abc258262b9543cce94752487150007c75760a 003c4890 0000009c c1e8b12d58db03dbbc6e9beb72917ea3d9583111 003c492c 000000e0 c1e8b12d58db03dbbc6e9beb729177a0cc42 003c4a0c 00000084 c1e8b12d58db01c6b4798dd77baa45a2c05f37 003c4a90 00000134 c1e8b12d5ac71bdab05486fb74916aa7dc42251b8346 003c4bc4 00000158 e1c8912d4fd91bc0be548cfa7eb87f 003c4d1c 00000264 e1c8912d4fd91bc0be5499fd78bc6fab 003c4f80 00001ea8 e1c8912d5fd011c1a36e9ad771bc75abf04231068440 003c6e28 00000038 e1c8912d4ad006f1b169 003c6e60 000000a0 e1c8912d40dc01c8bc7fb7eb65af69ae 003c6f00 00000134 e1c8912d40dc01c8bc7f 003c7034 00000020 e1c8912d5edd1dd98a6787ef 003c7054 00000340 c1e8b12d49c71ff1b16e8afd70 003c7394 000001bc e1c8912d5dc71bc0a15484ec64ac 003c7550 00000058 e1c8912d5dc71bc0a15484ec64ac45aecb43 003c75a8 000000bc e1c8912d5edd1dd98a678cfd63 003c7664 00000094 e1c8912d5edd1dd98a678cfb 003c76f8 00000118 e1c8912d5edd1dd98a6887e671a77d 003c7810 00001aa4 e1c8912d49d010dbb2 003c92b4 0000002c e1c8912d40d400c58a689be548af79b2c64737 003c92e0 00000034 e1c8912d40d400c58a689be548a774a7cc453b0294 003cb44c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cb454 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cb45c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cb464 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cb46c 00000038 d7f3a73172f137ff804eb7cc46 003cb4a4 00000028 d7f3a73172e233e78154bcc15a8b5e 003cb4cc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cb4d4 000000e4 e1c8910759dc1ef1b46784e7749173a8c6450d178243dbea 003cb5b8 000000e4 e1c8910759dc1ef1b46784e7749173a8c6450d17824fdbea 003cb69c 000000e4 e1c8910759dc1ef1b46784e7749173a8c6450d17874fdbea 003cb780 00000044 e1c8910759dc1ef1b6649de663917eb3cd42 003cb7c4 00000118 e1c8910759dc1ef1b6649de6639176a9c8563710ae4bd6d77c57546957 003cb8dc 00000028 e1c8910759dc1ef1b6649de663917eb7 003cb904 00000028 e1c8910759dc1ef1b6649de6639169b7 003cb92c 000000b0 e1c8910759dc1ef1b67889eb759179abcb 003cb9dc 00000050 e1c8910759dc1ef1b67885eb759179abcb 003cba2c 00000050 e1c8910759dc1ef1b67d85eb759179abcb 003cba7c 0000005c e1c8910759dc1ef1b16fb7e1649168b3c15f3b1a96 003cbad8 00000050 e1c8910759dc1ef1b16e89e47ba17999cc42331793 003cbb28 00000050 e1c8910759dc1ef1b16e89e47ba17999cc423f1793 003cbb78 00000050 e1c8910759dc1ef1b16e89e47ba17999cc473f1793 003cbbc8 0000006c e1c8910759dc1ef1b06f8bd724fc 003cbc34 0000001c e1c8910759dc1ef1b26e9cd77ea27c99df5020009856d1e77661546b5e3a 003cbc50 000001d4 e1c8910759dc1ef1bc6581fc7eaf76afd5540d1d9d44e7e17c61456e4b3c7e 003cbe24 0000019c e1c8910759dc1ef1a5649afc48ad75a8c958352b8643cae6715040 003cbfc0 00000208 e1c8910759dc1ef1a57981e663916db1c1 003cc1c8 000000c8 e1c8910759dc1ef1a57981e663916ea7c8 003cc290 000000c0 e1c8910759dc1ef1a57981e663917cb3dc583d1aae57cde17c 003cc350 000003d0 e1c8910759dc1ef1a57981e663917eafdc5a0d179e4cdee17f 003cc720 00000378 e1c8910759dc1ef1a6689afd759178a7cc5a371a957ddbe776584e657b3967747425eb00d1 003cca98 00000050 e1c8910759dc1ef1a6689beb759179abcb 003ccae8 00000278 e1c8910759dc1ef1a16e9ae57ea07bb2ca 003ccd60 0000007c e1c8910759dc1ef1a76e89ec48a379b4dd 003ccddc 0000008c e1c8910759dc1ef1b16e89e47ba17999d7492a1793 003cce68 00000188 e1c8910759dc1ef1b4789be170a045aac0523318ae56dde56861496d4d3b 003ccff0 000000ec e1c8910759dc1ef1a16e9ae57ea07bb2ca6e220083138bbd2a0678644536796e6b1f 003cd0dc 00000120 e1c8910759dc1ef1a26a81fc48a875b4f05536 003cd1fc 000000f0 e1c8910759dc1ef1a27981fc729177a5dd43 003cd890 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003cd898 00000100 d1f8bd1f4cdc1cda8a789dfb67ab74a2 003cd998 00000100 d1f8bd1f4cdc1cda8a798dfb62a37f 003cda98 00000258 d1f8c63f6cfc3cfa8a59bbcc5a915e83ee7d1e3bb2 003cdcf0 00000138 d1f8bd1f4cdc1cda8a799bec48af76aac052 003cde28 00000080 d1f8bd1f4cdc1cda8a799bec48a868a3ca 003cdea8 00000098 d1f8bd1f4cdc1cda8a6286fb63af74b2f0433707854dcaed475243 003cdf40 00000414 d1f8bd1f4cdc1cda8a7b9ae179ba45b5c15022008347ddd76a4d42657b2c77726d09 003ce354 0000016c d1f8bd1f4cdc1cda8a7b9ae179ba45afdd533b0082 003ce4c0 00000150 d1f8bd1f4cdc1cda8a7b9ae179ba45a8d85f28169856cb 003ce610 00000404 d1f8bd2d60f43be08154afcd598b488fec 003cea14 00000214 d1f8bd3f6cfc3cfa8a4da7da548b4594ea73073dbd66e7d8596c6e567d 003cec28 000009d8 d1f8bd3f6cfc3cfa8a5fbac959915689ec70063dbe6c 003d0600 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003d0608 0000000c ffcf972d4fd206cfa6609bd764bb69b6ca5f362bae67e0dc5d6c694368004a 003d0614 0000000c ffcf972d4fd206cfa6609bd776ad6eafd9502611ae7dfdd04c7b754c65134a44 003d0620 00000028 d7f3a73172e233e78154bcc15a8b5e 003d0648 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003d0650 00000014 f1ca811a48ea14dcb06ea6de55bb7ca0ca43 003d0664 000000b4 c1f2b12d44db1bda 003d0718 00000034 e1d2912d5dc71bc0a13a 003d074c 00000124 c1f2b12d4fc000c08a6889fa73916da9dd55 003d0870 00000280 c1f2b12d4fc000c08a6889fa73916aa9dd453b1b9f 003d0af0 0000006c c1f2b12d4edd17cdbe548ee7659179a9cb540d189e43dc 003d0b5c 000002f4 e1d2912d5dc71bc0a1548df072ad45a0c3503507 003d0e50 0000012c c1f2b12d4eda02d78a6285e970ab 003d0f7c 000000d4 c1f2b12d4eda1fdeb47fb7e076bc7eb1ce4337 003d1050 00000098 c1f2b12d4bda00cdb0548be773ab76a9ce55 003d10e8 0000004c c1f2b12d4ad006f1bd6a9aec60af68a3f0452b0494 003d1134 00000128 c1f2b12d4ad006f1bc6689ef729172a2d86e260d8147 003d125c 00000114 c1f2b12d4ad006f1b2679ded48b87fb4dc583d1a82 003d1370 000000f0 c1f2b12d4ad006f1b2679ded48b87fb4dc583d1ac2 003d1460 00000148 c1f2b12d4ad006f1bc6689ef72916ca3dd423b1b9f 003d15a8 000000dc c1f2b12d4ad006f1bc6689ef729173a8f0442111 003d1684 000001ac c1f2b12d44d813c9b0548afd71a845a3cb520d179947dbe3 003d1830 000000cc c1f2b12d44d813c9b0548dec749179aeca5239 003d18fc 00000054 c1f2b12d44db04cfb9628ce963ab45aac652392b9243dbe07d614577423970696a 003d1950 000001ac e1d2912d44db04cfb9628ce963ab45b6df520d179041d0ed 003d1afc 0000014c c1f2b12d42d602f1b366b7fa72be75b4db 003d1c48 000003e4 c1f2b12d4ad006f1bc6689ef72 003d202c 00000360 c1f2b12d4ad006f1a0658be77abe68a3dc423710ae4bd5e97f5b 003d238c 00000308 c1f2b12d4fc000c08a6889fa73917fb4ce4237 003d2694 000000c8 c1f2b12d42d602f1b366b7fa72be75b4db03 003d275c 00000158 c1f2b12d42d602f1bd7cb7fd67aa7bb2ca6e3f1b9547 003d28b4 00000044 c1f2b12d5dc000c9b05481e576a97f99cd443b1895 003d28f8 0000028c c1f2b12d5dc000c9b05481e576a97f 003d2b84 000001e0 c1f2b12d5dc006f1bc6689ef72 003d2d64 0000011c c1f2b12d7ff033ea8a48a9da53915382 003d2e80 0000003c c1f2b12d4ad006f1b66a9aec48bd73bcca 003d2ebc 00000150 c1f2b12d4eda16cb8a6787e9739175a5df 003d300c 0000031c c1f2b12d4fc000c08a6889fa73 003d3328 000000ec c1f2b12d5fd01ecbb4788dd77ea37ba1ca 003d3414 000012e8 c1f2b12d4eda16cb8a6787e973 003d46fc 00000978 c1f2b12d4eda16cbb96489ec48a275a5ce5d 003d5074 000000a0 c1f2b12d5fd001dab4799cd770a26fa3 003d5114 000000d4 c1f2b12d5ed01cca8a6285e970ab45a4da583e10 003d51e8 000000b8 c1f2b12d5ed01cca8a6285e970ab45a7cc5a 003d52a0 000000e8 c1f2b12d5ed01cca8a6285e970ab 003d5388 00000038 c1f2b12d5ec113dca1548afd65a045a4da583e10 003d53c0 00000054 c1f2b12d5ec113dca1548afd65a045a7cc5a 003d5414 000000d8 c1f2b12d5ec113dca1548afd65a045a9db593706 003d54ec 00000038 c1f2b12d5ec113dca1549dfb729178b3c65d36 003d5524 00000054 c1f2b12d5ec113dca1549dfb72917ba5c4 003d5578 0000006c c1f2b12d5ec113dca1549dfb729175b2c75420 003d55e4 0000005c c1f2b12d58c516cfa16eb7ef72ba45a2ce45332b9357d1e47c 003d5640 00000070 c1f2b12d58c516cfa16eb7ef72ba45a2ce45332b9041d3 003d56b0 000000c0 c1f2b12d58c516cfa16eb7fb72a07e99cb502615ae40cde1745a 003d5770 00000034 c1f2b12d58c516cfa16eb7fb72a07e99cb502615ae43dbe3 003d57a4 0000004c c1f2b12d5ad41bda8a699dfa799175b2c75420 003d57f0 000010c0 c1f2b12d41da13ca8a6285e970ab 003d68b0 0000004c c1f2b12d5ad41bda8a7e9bed48a16eaeca43 003d68fc 0000079c c1f2b12d58c617f1bc6689ef72 003d7098 000002ac c1f2b12d58c516cfa16eb7e763a67fb4 003d7344 00000038 c1f2b12d5ad419cb8a7884e174a545b1ce58261183 003d737c 0000020c e0ce8e1d4ed406cb8a6f8deb78a36ab4ca4221 003d8b28 00000028 d7f3a73172f436ea8a58b9 003d8b50 00000044 d7f3a73172e527fa8a4abbd1598d5299fe6417 003d8b94 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003d8b9c 00000034 c1f2b12d49d813f1b2649cd774aa78b5 003d8bd0 00000034 c1f2b12d49d813f1b16486ed 003d8c04 000000ec c1f2b12d49d813f1b8649eed48a868a9c26e351b85 003d8cf0 000000fc c1f2b12d49d813f1b8649eed48a868a9c26e3115924add 003d8dec 000000ec c1f2b12d49d813f1b8649eed48ba7599c85e26 003d8ed8 000000fc c1f2b12d49d813f1b8649eed48ba7599cc50311c94 003d8fd4 00000124 c1f2b12d49d813f1af6e9ae748a975b2 003d90f8 000000f4 c1f2b12d49d813f1af6e9ae748ad7ba5c754 003d91ec 0000010c c1f2b12d57d000c18a6889eb7fab 003d92f8 0000002c c1f2b12d40da04cb8a6d9ae77a9179a7cc5937 003d9324 0000002c c1f2b12d40da04cb8a7f87d774af79aeca 003d9350 0000001c d7f3a73172f03cff804eb7cc46 003d936c 00000028 d7f3a73172e233e78154bcc15a8b5e 003d9394 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003d939c 00000044 c1f2b12d49d305f1a07b8ffa76aa7f99ce5239 003d93e0 00000064 c1f2b12d49d305f1a07b8ffa76aa7f99c0453a1183 003d9444 00000038 c1f2b12d49d305f1a07b8ffa76a97f99cd443b1895 003d947c 00000264 c1f2b12d49c71bd8b05484e776aa45a5c05c22189456dd 003d96e0 000001f8 c1f2b12d48d817dcb26e86eb6e917ea0d86e25159856 003d98d8 000000f8 c1f2b12d4bdc1cca8a6a8cee60a77e 003d99d0 00000264 e1d2912d4bdc1cca8a6f8eff73 003d9c34 00000b98 c1f2b12d4fc01bc2b1548cee60aa 003da7cc 0000030c c1f2b12d49c71bd8b0548be773ab76a9ce550d19904bd6 003daad8 000001b0 c1f2b12d4ad006f1b37cb7e17aaf7da3 003dac88 000002e0 c1f2b12d49da2dcab37cb7e17aa37fa2c6502611 003daf68 00000254 c1f2b12d48d817dcb26e86eb6e917ea0d86e27049650d9ec7d 003db1bc 00000100 c1f2b12d58c516cfa16eb7ec64a245b3cb42302b9357d1e47c 003db2bc 00000100 c1f2b12d58c516cfa16eb7ec74a245b3cb42302b9357d1e47c 003db3bc 00000a80 c1f2b12d5edd1dd98a6887e671a77d 003dbe3c 0000012c c1f2b12d4cd71ddca1548be773ab76a9ce55 003dbf68 000000f8 c1f2b12d40dc15dcb47f8dd764ba7baac36e311c9441d3 003dc060 000001f8 c1f2b12d4eda16cbb96489ec48ad76a3ce5f2704 003dc258 000000cc c1f2b12d4edd17cdbe548cfa7eb87f99c946 003dc324 0000005c e1d2912d4bdc1cca8a7d9ae97eaa2a 003dc380 0000006c ffce8f115dcc2dccac7f8dfb 003dc3ec 00000038 c1f2b12d44db04cfb9628ce963ab45a7cb5725 003dc424 000003e8 c1f2b12d58c516cfa16eb7e973a86da2cd 003dc80c 00000680 e1d2912d43d017ca8a6f8ee1 003dce8c 0000004c ffce8f0148c12dccac7f8dfb 003dced8 000005cc c1f2b12d58c516cfa16eb7fd73bd78 003dd4a4 0000069c c1f2b12d49c71bd8b05484e776aa7fa2 003ddb40 00000504 e1d2912d49da2dcdba6f8de478af7e 003de044 000002a0 c1f2b12d41da13ca8a6f9ae161ab 003de2e4 0000014c e1d2912d4edd17cdbe5485e170bc7bb2ca6e21049041dd 003dee18 00000024 d7f3a73172f137e29c45a3d7539f 003dee3c 0000001c d7f3a73172f03cff804eb7cc46 003dee58 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003dee60 00000018 c1f2b12d40d311f1b76a8cd761ab79b2c043 003dee78 000000a8 c1f2b12d55d814cd8a6a8be3 003def20 00000088 c1f2b12d55d814cd8a6a8ae765ba45b1ce58262b8347cbf87750546757 003defa8 0000007c c1f2b12d55d814cd8a699de17baa 003df024 00000068 c1f2b12d55d814cd8a7f80e164917caac046 003df08c 00000068 c1f2b12d55d814cd8a7f80e164917caac0460d36a872f9db4b 003df0f4 000000a4 c1f2b12d55d814cd8a7f80e164917caac0460d079251e7ea614e467157 003df198 00000060 c1f2b12d55d814cd8a7f80e164916da7c645 003df1f8 00000060 c1f2b12d55d814cd8a7f80e164916da7c6450d168852d9fb6b 003df258 00000060 c1f2b12d55d814cd8a7f80e164916da7c6450d079251e7ea614e467157 003df2b8 000000d4 c1f2b12d55d814cd8a6689fb63ab6899c95d3d03 003df38c 000000ac c1f2b12d55d814cd8a6689fb63ab6899c95d3d03ae40c1f8794d54 003df438 000000ec c1f2b12d55d814cd8a6689fb63ab6899c95d3d03ae51dbfb475c5e72452c66 003df524 00000080 c1f2b12d55d814cd8a6689fb63ab6899db43331a824bcce1775078664b3170 003df5a4 00000060 c1f2b12d55d814cd8a6689fb63ab6899d8503b00 003df604 00000060 c1f2b12d55d814cd8a6689fb63ab6899d8503b00ae40c1f8794d54 003df664 00000060 c1f2b12d55d814cd8a6689fb63ab6899d8503b00ae51dbfb475c5e72452c66 003df6c4 0000008c c1f2b12d55d814cd8a798de578ba7f99cb583710 003df750 0000004c c1f2b12d55d814cd8a798de578ba7f99c95d3d03 003df79c 00000050 c1f2b12d55d814cd8a798de578ba7f99c95d3d03ae40c1f8794d54 003df7ec 00000090 c1f2b12d55d814cd8a798de578ba7f99c95d3d03ae51dbfb475c5e72452c66 003df87c 00000060 c1f2b12d55d814cd8a798de578ba7f99d8503b00 003df8dc 00000060 c1f2b12d55d814cd8a798de578ba7f99d8503b00ae40c1f8794d54 003df93c 00000060 c1f2b12d55d814cd8a798de578ba7f99d8503b00ae51dbfb475c5e72452c66 003df99c 00000108 c1f2b12d55d814cd8a798dfb67a174b5ca 003dfaa4 0000008c c1f2b12d55d814cd8a798dfb67a174b5ca6e34189e55 003dfb30 0000008c c1f2b12d55d814cd8a798dfb67a174b5ca6e34189e55e7ea614e467157 003dfbbc 0000008c c1f2b12d55d814cd8a798dfb67a174b5ca6e34189e55e7fb7b4d78605d2f74686a 003dfc48 000000a4 c1f2b12d55d814cd8a798dfb67a174b5ca6e25159856 003dfcec 000000a4 c1f2b12d55d814cd8a798dfb67a174b5ca6e25159856e7ea614e467157 003dfd90 000000a4 c1f2b12d55d814cd8a798dfb67a174b5ca6e25159856e7fb7b4d78605d2f74686a 003dfe34 00000030 c1f2b12d55d814cd8a788de673ac6b 003dfe64 00000064 c1f2b12d40dc00dcba79b7e973a86da2cd6e3001984edc 003dfec8 00000044 c1f2b12d40dc00dcba79b7e973a86da2cd6e33179a 003dff0c 00000064 c1f2b12d40dc00dcba79b7e973a86da2cd 003dff70 00000048 c1f2b12d40dc00dcba79b7ea62bc74b2f053271d9d46 003dffb8 0000002c c1f2b12d40dc00dcba79b7ea62bc74b2f050311f 003dffe4 00000120 c1f2b12d40dc00dcba79b7ea62bc74b2 003e0104 00000048 c1f2b12d40dc00dcba79b7fd64ab7e99cd443b1895 003e014c 0000002c c1f2b12d40dc00dcba79b7fd64ab7e99ce5239 003e0178 00000048 c1f2b12d40dc00dcba79b7fd64ab7e 003e01c0 00000130 c1f2b12d42c11acba7548ee97ea27fa2 003e0370 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e0378 00000088 c1f2b12d49d014c7bb6eb7f875ac 003e0400 00000030 c1f2b12d49d014c7bb6eb7f875ac45a4da57341183 003e0430 00000260 c1f2b12d5bd41ec7b16a9ced48bb6fafcb6e20159f45dd 003e0690 00000158 c1f2b12d43d00ada8a7e9de1739168a7c15637 003e07e8 00000078 c1f2b12d43d00ada8a7e9de173 003e0860 00000098 c1f2b12d4bc717cb8a6d85eb74917ca3cb 003e08f8 000000b8 c1f2b12d4ad006f1a6788fe4 003e09b0 00000080 c1f2b12d4ada06f1a6788fe4 003e0a30 00000054 c1f2b12d40da04cb8a6a86ec48ba68afc2 003e0a84 0000003c c1f2b12d5dd710f1a26a81fc72bc45a7cc5a 003e0ac0 00000098 c1f2b12d5ed414cb8a6687ec72 003e0b58 00000260 e1d2912d5fd002c1a77fb7f865a179a3dc420d109e4bd6ef474948704f 003e0db8 0000014c c1f2b12d4bdc1cca8a7b9ae774ab69b5ca420d109e4bd6ef474948704f 003e0f04 0000008c c1f2b12d4ad006f1b76a9bed7bab6ca3c36e3b10ae51ccfa715040 003e0f90 000000d0 c1f2b12d4ad006f1b77e81e473916eafc2540d078550d1e67f 003e1060 00000020 c1f2b12d4ad006f1b06e98fa78a345a2ce4533 003e1080 00000034 c1f2b12d5ed006f1b06e98fa78a345a2ce4533 003e10b4 0000006c c1f2b12d48d1119de7 003e1120 00000428 c1f2b12d4edd17cdbe548ee7659179b2dd5d0d179943ca 003e1548 00000074 c1f2b12d4edd17cdbe548ee765917bb5d65f312b924ad9fa 003e15bc 0000010c c1f2b12d5dc71bc0a15498fa72a873be 003e16c8 00000024 d7f3a73172e233e78154a5c1549c5595 003e1978 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e1980 0000033c f6ce811d40c500cba678b7ee65a17799cd4434129450e7e4714d53 003e1ca0 00000000 f6ce811d40c500cba678b7ee65a17799cd4434129450e7e4714d535d413171 003e1cbc 00000028 d7f3a73172e233e78154bcc15a8b5e 003e1ce4 00000038 d7f3a73172f03ffe8152b7c944975485e76e0321b4 003e1d1c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e1d24 00000060 fcdd8f1740d602d7 003e1d84 00000294 c1f2b12d49c71ff1a76e9bf179ad45a8c0453b1288 003e2018 00000098 c1f2b12d4bd401da8a7f81e572bc 003e20b0 000001e8 c1f2b12d5fd001d7bb68 003e2298 00000170 c1f2b12d5fd001d7bb68b7eb72a27699ce5239 003e2408 00000198 c1f2b12d5fd001d7bb68b7eb72a27699cd443b1895 003e25a0 00000048 c1f2b12d5fd001d7bb68b7e179a875b4c254362b9041d3 003e25e8 0000012c c1f2b12d5fd001d7bb68b7e179a875b4c254362b9357d1e47c 003e2714 000000b8 c1f2b12d5fd001d7bb68b7e179a875b4c25436 003e27cc 000006a4 c1f2b12d5fd001d7bb68b7e678b9 003e2e70 00000180 c1f2b12d5fd001d7bb68b7ee7ea073b5c7 003e2ff0 000002e4 c1f2b12d5fd001d7bb68b7e576a774 003e32d4 000001e0 c1f2b12d5fd001d7bb68b7e763a67fb4 003e34b4 00000138 c1f2b12d5fd001d7bb68b7e763a67fb4f050311f 003e35ec 0000012c c1f2b12d5ec113dca15481e671a168abf053271d9d46 003e3718 00000178 c1f2b12d5ec113dca15481e671a168abf050311f 003e39cc 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e39d4 000000b0 e1df900159c7 003e3a84 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e3a8c 000000a4 f6c9852d40da1cf1bc6581fc 003e3b30 0000005c e0ce911759ea06dcb27f 003e3b8c 00000038 ffd8852d4ad91dc0b2 003e3bc4 00000028 ffd8852d4ac21ddcb1 003e3bec 00000014 ffd8852d4ad70bdab0 003e3c00 00000030 ffd8852d5dd91dc0b2 003e3c30 00000020 ffd8852d5dc21ddcb1 003e3c50 00000014 ffd8852d5dd70bdab0 003e3c64 00000940 f1c6861e42da02 003e45a4 00000070 f6c9852d40da1cf1a67f89fa63 003e4614 000000b4 faca8c1641d000f1a67f87f8 003e494c 000000a8 ffce8f2d58c516cfa16e 003e49f4 00000150 e0c6871f 003e4b44 000001a8 e5c6871f 003e4cec 00000124 e1c6871f 003e4e10 00000234 f1c6871f 003e5044 000000a0 e1ce96105fde 003e50e4 0000008c f1c790105fde 003e5228 00000104 e0ce831672c602dc 003e532c 00000070 e0ce831672c110dc 003e539c 00000090 e0ce831672d111dc 003e542c 00000088 e0ce831672d302dc 003e54b4 00000128 e5d98b0648ea01dea7 003e55dc 000000b4 e5d98b0648ea16cda7 003e5690 0000006c e5d98b0648ea14dea7 003e56fc 00000480 e0d98715 003e5b7c 000003f0 e5d98715 003e5fa4 00000074 ffc48c2d40c615 003e6018 00000068 ffc48c2d40c615f1b4679fe96ebd 003e6080 000000cc ffc48c2d44d11fddb2 003e614c 00000110 ffc48c2d49c01fde8a7b83fc 003e627c 000000c8 ffd8852d40c617daa07b 003e6344 00000024 ffd8852d4fd416dda16a8be3 003e63d4 00000298 ffdbbd1548c1 003e666c 00000138 ffdbbd055fdc06cb 003e67a4 00000024 ffd8852d40db17d6a1628c 003e682c 000000ec ffd8852d5dd01cca 003e697c 0000007c ffd8852d5fd003dbb0789c 003e69f8 000000b0 ffd8852d5fd013ca 003e6aa8 00000070 ffd8852d5fd011cbbc7d8d 003e6b18 00000050 ffd8852d4cd619 003e6b68 00000028 ffd8852d4cd71ddca1 003e6bd0 00000050 ffd8852d5edc15c0b467 003e6c20 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e6c28 00000040 f6c9852d4edd17cdbe548bfc65a245bc 003e6c68 000000ac f6c9852d58d400da8a6286e163 003e6d14 00000068 f6c9852d58d400da8a7b87e47b 003e6d7c 00000064 f6c9852d58d400da8a7881e567a27f99df5e3e18 003e6de0 00000064 f6c9852d58d400da8a6c8be076bc 003e6e44 00000070 f6c9852d58d400da8a7b8be076bc 003e6edc 00000000 f1ca811a48ea1ec7bb6e9be16dab 003e6ee4 00000000 fbc58b0672c606cba5 003e6ef8 00000000 f1c787135fea01dab07b 003e6f24 00000000 bcce9a1b59ea11dd 003e6f28 00000000 e6d9850672d801dc 003e6f40 00000000 e6ca901548c12dddbc6c 003e6f44 00000000 fbc58b0672c113dcb26e9c 003e6f94 00000000 fbc58b0672d110c98a789ce974a5 003e6fb8 00000000 f0ca860159d411c5 003e6fc4 00000000 f0d88e1d42c5 003e6fd0 00000000 f0d88e1d42c540 003e6fe0 00000000 e7d8902d44c703f1b06589ea7bab 003e6ff8 00000000 e1ce961f5ec7 003e7008 00000000 cdcf801572d81dc08a6889e47b 003e7028 00000000 f6c9852d45d41ccab96e9a 003e70b8 00000000 e1df8d0272c113dcb26e9c 003e7134 00000000 e1df830059ea1fc1bb629ce765 003e7188 00000000 f7d3871158c117 003e7204 00000000 f1c48f1f4cdb16f1b36a81e462bc7f 003e7260 00000000 f5ce962d5dc71dcd 003e7268 00000000 f5ce962d4bc501cda7 003e7284 00000000 e2de962d4bc501cda7 003e72a0 00000000 f5ce962d5ed015dcb06c 003e72ac 00000000 e2de962d5ed015dcb06c 003e72c0 00000000 f1ca811a48ea07deb16a9ced 003e72d8 00000000 f1ca811a48ea14c2a07880 003e72f0 00000000 f6c9852d45d41ccab96eb7ed6fad7fb6db583d1a 003e7350 00000140 ffd8852d4fc01bc2b1 003e7490 0000006c ffd8852d4edd19dda066 003e74fc 00000034 ffd8852d43d61ac5a67e85 003e7530 00000070 ffd8852d48db11c1b16e 003e75a0 0000007c ffd8852d49d011c1b16e 003e761c 0000024c ffd8852d43da00c3 003e78a0 00000010 d7f3a73172fc3ce78154bbd9 003e78b0 00000028 d7f3a73172f436ea8a58b9 003e78d8 0000002c d7f3a73172e737e39a5dadd7449f458eea7016 003e7904 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e790c 00000014 f1ca811a48ea14dcb06eaafd71a87fb4 003e7920 000000f4 d6f3c62179f420fa 003e7a14 0000008c d6f3c62179fa22 003e7aa0 000000cc d6f3c62168e12dea8059a9dc5e8154 003e7b6c 00000084 d6f3c63568e12dfd8046a5c94597 003e7bf0 00000190 f6d3bd1642ea14dbb967b7ff65a76ea3 003e7d80 000000fc f6d3bd145fd017f1ad6fb7fa72bd75b3dd523707 003e7e7c 000000c0 f6d3bd145fd017f1a76e9be762bc79a3dc 003e7f3c 00000144 f6d3bd1548c12dd9a77fb7ea62a87ca3dd42 003e8080 00000390 f6d3bd1548c12dd6b178 003e8410 0000013c f6d3bd1548c12ddcb07887fd65ad7fb5 003e854c 000000a0 f6d3bd1542c12dd6b178 003e85ec 00000068 f6d3bd1542c12dc8b06f9b 003e8654 00000050 f6d3bd1542c12dddb267 003e86a4 00000028 f6d3bd004cdb16 003e86cc 00000378 f6d3bd1642ea00cfbb6f87e548a775 003e8a44 00000224 f6d3bd1642ea06cba67f 003e8c68 00000114 d6f3c63664f92a 003e8d7c 00000184 f6d3bd075dd113dab05480e965aa45a3dd433d06 003e8f00 000001b8 f6d3bd1642ea11c3a5 003e90b8 0000011c f6d3bd075dd113dab0549be771ba45a3dd433d06 003e91d4 000001cc f6d3bd0048d416f1b16486ed 003e93a0 000001a8 f6d3bd055fc12dcaba658d 003e964c 00000008 f8de910672c61bc2b972b7ee78bc45a5c05c221d9d47cad76f5f556c4d317268 003e9654 00000098 d6e2a33572d11bdda56789f148aa7fa4da560d129d43dffb 003e96ec 00000098 d6e2a33572d11bdda56789f148be68afc1450d129d43dffb 003e9784 0000005c f1c787135fea1bc0a57e9c 003e97e0 00000108 f3df8d16 003e98e8 000000b4 f3df8d1a 003e999c 00000074 f1ca8e1e72d307c0b67f81e779 003e9a10 0000003c f1ca8e1e72dd02f1b16e8afd70 003e9a4c 0000003c f1ca8e1e72c616f1b16e8afd70 003e9a88 00000028 f6c2912d48d002dcba66 003e9ab0 000001bc ffdb901b43c12dc6b073b7ea6eba7f99db50301894 003e9c6c 00000078 f6c2912d4fcc06cb 003e9ce4 0000008c f6c2912d5edd1ddca1 003e9d70 000000ac f6c2912d49c010f1a2649aec 003e9e1c 0000007c f6c2910241d40bf1b16e8afd70917caace5621 003e9e98 00000104 f6c4bd1648d707c98a6d84e970bd 003e9f9c 00000040 f6c4bd1644c602c2b472b7fb76 003e9fdc 00000028 f6c4bd1b41d32dddb07fb7e478a945a5c05c221b9f47d6fc475346714f 003ea004 0000002c f6c4bd1b41d32dddb07fb7e478a945a5c3502107ae4fd9fb73 003ea030 00000064 f6c2910241d40bf1a57981e663917caace5621 003ea094 00000104 f6c4bd025fdc1cda8a6d84e970bd 003ea198 000000c8 f6c4bd0545d406dd8a7e98 003ea260 00000124 f6c4bd144ec62ddda17e8eee 003ea384 000000c0 f4c28e1e4fcc06cb 003ea444 000000cc f4c28e1e5ada00ca 003ea510 00000074 f4c28c1658d9 003ea584 00000074 f4c28c1658c6 003ea5f8 00000074 f4c28c1658c1 003ea66c 00000028 f5ce962d5ec113cdbe 003ea694 00000134 f5ce962d5ada00caa6 003ea7c8 00000824 face8e0242c006 003eafec 00000028 fece862d59d001da 003eb014 000000d0 fec48d1958c52dcdb86f 003eb0e4 000000cc ffc28c1654ea11cd8a7b9ae179ba7c 003eb1b0 00000200 f6c4bd1f4cdc1cda8a6286fe78a57f 003eb3b0 0000055c ffc28c1654ea02cfa7788d 003eb90c 000000e0 ffc4862d4fcc06cb 003eb9ec 00002344 ffc4862d5fd015c7a67f8dfa 003edd30 000000b8 f6c2912d5ada00ca 003edde8 0000013c ffc4862d5ada00ca 003edf24 00000728 e2d98b1c59ea01dab46883d764ba6fa0c9 003ee64c 000000fc e0ce831641dc1ccb 003ee748 00000708 e0ce851b5ec117dca6 003eee50 00000020 e0ce911759 003eee70 00000010 e1dc8b064edd2dd8b0798ae764ab 003eee80 000003ac e6ce910672d817c3ba7991 003ef22c 00000044 e4ce900144da1c 003ef270 00000058 f6c2831572d81bc0b172b7e578a073b2c043 003ef2c8 00000028 f1c48c0142d917f1ba7e9ce47ea07f99db42 003f2724 00000028 e1df901145c7 003f274c 0000005c e1df90004edd00