topic Read Cache Disable bit has been enabled in Disk Enclosures

Read Cache Disable bit has been enabled

Printaporn_1 — Mon, 22 Oct 2001 02:53:18 GMT

I got following EMS message,
-----------
Array at hardware path 0/5/0/0.8.0.5.0.0.0, path : The controller in slot B has
the Read Cache Disable bit enabled.
Associated OS error log entry id(s):
0000000000000000000

Latest information on this event:
http://docs.hp.com/hpux/content/hardware/ems/fc60mon.htm#28

Description of Error:
This event message is displayed when the Read Cache Disable
bit has been enabled.

Probable Cause / Recommended Action:
Execute the command to reset all the cache bits.
---------------
what to do next , by the way no LED fault , mstm export tool don't report any problem , in sam also no warning , but EMS state for array is down.
and one more question 0/5/0/0.8.0.5.0.0.0 is controller A , why EMS say it's controller B ?

thanks in advance,

Re: Read Cache Disable bit has been enabled

Rita C Workman — Mon, 22 Oct 2001 11:58:22 GMT

Hi Printaporn,

Apparently this has been enabled on your drive.
The question I would have to ask is...WHAT KIND OF DRIVE DO YOU HAVE?

To reset the the bit you might need to flip a dipswitch on the scsi device -OR- you may need to enter some parameter in some form of SCSI Mode Command like some IBM devices.

Example:
On IBM UltraStar, command entry:
http://www.storage.ibm.com/hdd/support/dgvs/dgvsmso.htm
Resetting by dipswitch:
http://www.maxoptixeurope.com/support/switchsettings/star.htm

Rgrds,
Rita

Re: Read Cache Disable bit has been enabled

Bill McNAMARA_1 — Mon, 22 Oct 2001 14:21:06 GMT

I'm not sure what array it is, but it looks like an FC60..

on the autoraid the read/write cache is set by arraymgr (I'm sure it's the same for the FC60)

If you look at that man, it describes that the caching is always on, and the only reason you'd turn either off is if you're using the array on an nt server.. who doesn't like the array to do caching.. so the array will pretend not to do caching even though it always does.
Don't ask me why..

Another thing to look out for is equal memory config on both controllers from arraydsp -c (amdsp -c).. just incase something failed.

Later,
Bill

Re: Read Cache Disable bit has been enabled

Printaporn_1 — Thu, 25 Oct 2001 01:51:25 GMT

thanks ,
they array is FC60 that I try to check manual but I don't find information about read cache , just enable write cache.
So How ?