<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic XP12000 cache memory and shared memory in Disk Enclosures</title>
    <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462184#M31995</link>
    <description>Please answer the following questions:&lt;BR /&gt;1)What is the difference between cache memory and shared memory on XP12000?.&lt;BR /&gt;2)Please explain the detailed write operation on XP12000.&lt;BR /&gt;3)Please explain the detailed read opearation on XP12000.&lt;BR /&gt;4)What read and write policies are used for the cache memory?.&lt;BR /&gt;&lt;BR /&gt;Thanks</description>
    <pubDate>Fri, 17 Jul 2009 20:27:19 GMT</pubDate>
    <dc:creator>white221g</dc:creator>
    <dc:date>2009-07-17T20:27:19Z</dc:date>
    <item>
      <title>XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462184#M31995</link>
      <description>Please answer the following questions:&lt;BR /&gt;1)What is the difference between cache memory and shared memory on XP12000?.&lt;BR /&gt;2)Please explain the detailed write operation on XP12000.&lt;BR /&gt;3)Please explain the detailed read opearation on XP12000.&lt;BR /&gt;4)What read and write policies are used for the cache memory?.&lt;BR /&gt;&lt;BR /&gt;Thanks</description>
      <pubDate>Fri, 17 Jul 2009 20:27:19 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462184#M31995</guid>
      <dc:creator>white221g</dc:creator>
      <dc:date>2009-07-17T20:27:19Z</dc:date>
    </item>
    <item>
      <title>Re: XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462185#M31996</link>
      <description>Hi,&lt;BR /&gt;this could help you:&lt;BR /&gt;&lt;A href="http://h71028.www7.hp.com/ERC/downloads/4AA0-7923ENW.pdf?jumpid=reg_R1002_USEN" target="_blank"&gt;http://h71028.www7.hp.com/ERC/downloads/4AA0-7923ENW.pdf?jumpid=reg_R1002_USEN&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;CACHE MEMORY page 18&lt;BR /&gt;Cache memory is used to transfer data between the host CHIP processors and the ACP disk controllers. In fact, cache memory is an integral part of the data path, as all data is transferred through cache before being transferred between the disk and the host server. Cache is also mirrored, allowing all write data to be written in cache twice, one time each on two separate battery-backed-up cache platform boards.&lt;BR /&gt;&lt;BR /&gt;SHARED MEMORY page 20&lt;BR /&gt;&lt;BR /&gt;Shared memory is independent of the cache memory and is used to store tables and other information used for disk management, thus freeing up the cache memory for user data. Shared memory is also used to store system configuration information. The configuration information includes system component mapping, LUN maps, cache pointers, and RAID levels.&lt;BR /&gt;&lt;BR /&gt;Sequential and Random IO workloads from page 9&lt;BR /&gt;...&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Sat, 18 Jul 2009 03:32:26 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462185#M31996</guid>
      <dc:creator>IBaltay</dc:creator>
      <dc:date>2009-07-18T03:32:26Z</dc:date>
    </item>
    <item>
      <title>Re: XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462186#M31997</link>
      <description>Thank you for your response. I had already read that document. It does not explain in detail, how a read or write opearation is done.I have read all possible documents from HP website, but still didnt get a clear answer. I need to know in detail how a read/write opeartion is done.Eg what is the role of CHIP, Cache memory, &amp;amp; ACP in the read and write process. What gets written into the cache and when. How a block of data sent to the CHIP gets written to the disk and how a block of data requested from the disk is provided to the CHIP. How is a sequential read and write processed different than a random read and write.&lt;BR /&gt;Thanks again.</description>
      <pubDate>Sat, 18 Jul 2009 14:53:19 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462186#M31997</guid>
      <dc:creator>white221g</dc:creator>
      <dc:date>2009-07-18T14:53:19Z</dc:date>
    </item>
    <item>
      <title>Re: XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462187#M31998</link>
      <description>&lt;!--!*#--&gt;Hi,&lt;BR /&gt;XPs are cache centric storages&lt;BR /&gt;&lt;BR /&gt;Writes and Reads&lt;BR /&gt;the CHIP (Front end controller) writes data into both cache areas (duplex) to avoid that data will be lost if a cache error occurs when it is not yet written on the disk.&lt;BR /&gt;The shared memory is used to classify and control the data in cache according to its attributes (enqueue/dequeue)&lt;BR /&gt;&lt;BR /&gt;Write data (new data) and read data (old data) are handled in separate segments, thus not overwritten - write penalty compensation.&lt;BR /&gt;&lt;BR /&gt;Read data (parity included) is&lt;BR /&gt;staged into either cache A or cache B&lt;BR /&gt;&lt;BR /&gt;If the write data causes a cache miss, the data of the target record up to the end of the track is staged into a read data slot&lt;BR /&gt;and the write data is transferred.&lt;BR /&gt;If there is a cache miss of the parity data, the old parity is staged into a read parity slot.&lt;BR /&gt;When all necessary data for generating new parity is there, it is transferred to the memory of the DKA (disk controller)&lt;BR /&gt;After the new parity completion, the DKA memory duplexes it into both write parity slots of the cache and it is ready for the destage&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Sat, 18 Jul 2009 16:34:01 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462187#M31998</guid>
      <dc:creator>IBaltay</dc:creator>
      <dc:date>2009-07-18T16:34:01Z</dc:date>
    </item>
    <item>
      <title>Re: XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462188#M31999</link>
      <description>&lt;BR /&gt;pp 11-15 of the below document are dedicated to Cache Memory and Shared memory on the XP24000.  The principles are the same on the XP1200 although max cache installed etc will be lower on the XP12K.&lt;BR /&gt;&lt;BR /&gt;This covers ,uch of what IBalty has said but may be in more detail.  Anything more than what is included in my doc and what IBalty has said is probably Hitachi confidential.&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://blogs.rupturedmonkey.com/wp-content/uploads/2009/04/usp-v-unofficial-manual-v0003.pdf" target="_blank"&gt;http://blogs.rupturedmonkey.com/wp-content/uploads/2009/04/usp-v-unofficial-manual-v0003.pdf&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;PS.  Its a bit rude not to assign points to the responses above.&lt;BR /&gt;&lt;BR /&gt;Nigel&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 20 Jul 2009 13:41:25 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462188#M31999</guid>
      <dc:creator>Nigel Poulton</dc:creator>
      <dc:date>2009-07-20T13:41:25Z</dc:date>
    </item>
    <item>
      <title>Re: XP12000 cache memory and shared memory</title>
      <link>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462189#M32000</link>
      <description>Fantastic Nigel!!&lt;BR /&gt;Thanks a million.&lt;BR /&gt;&lt;BR /&gt;P.S: I never knew there was a point system. I thought the moderator assigns the points. Please pardon my ignorance.&lt;BR /&gt;&lt;BR /&gt;thanks again.</description>
      <pubDate>Mon, 20 Jul 2009 15:26:21 GMT</pubDate>
      <guid>https://community.hpe.com/t5/disk-enclosures/xp12000-cache-memory-and-shared-memory/m-p/4462189#M32000</guid>
      <dc:creator>white221g</dc:creator>
      <dc:date>2009-07-20T15:26:21Z</dc:date>
    </item>
  </channel>
</rss>

