topic Re: Vector Processor in Operating System - OpenVMS

Vector Processor

FOX MULDER_2 — Wed, 19 Mar 2008 14:00:22 GMT

Can a Alpha processor be used in Vector processing as well?

If so can anyone please write a code how it can be utilized.

please let me know the answer.

Thanks

Re: Vector Processor

Robert Gezelter — Wed, 19 Mar 2008 14:34:33 GMT

FOX,

As a RISC architecture, there is no "vector processing" instruction set as distinct from the regular instruction set.

That said, carefully written and well tuned code can achieve very high vector performance on an Alpha. It does require care, as optimizing code for pipelined execution can be a complex task.

Depending on what one is doing, there may already be well-optimized routines for the operations available.

- Bob Gezelter, http://www.rlgsc.com

Re: Vector Processor

Hoff — Wed, 19 Mar 2008 17:51:10 GMT

Yes, Alpha configurations can utilize vector processing. The appropriate solution depends on the application, and the code will vary. Some background details on the environment and the application, please?

Conversely, should this be a test-, homework- or customer-support-related question and not an application implementation question, please let us know about that as the answer to that question can differ from my (admittedly generic) answer above; the wording of the particular question is critical here.

Re: Vector Processor

John Gillings — Wed, 19 Mar 2008 20:23:23 GMT

FOX,

"vector processing" is really just the execution of the same instruction on a vector of values. In the past there were some specialised (and expensive!) vector engines which could execute parallel operations.

There were a few VAX models released with implementations of the optional vector instruction set (VAX9000?). There were also special directives for the FORTRAN compiler to code vector operations. For C there are various vector processing libraries.

The very concept of vector instructions (kind of "extreme CISC") is the exact opposite of the philosophy of Alpha RISC architecture, so it doesn't make sense to have a vector processing Alpha.

In practice, todays processors are so fast and cheap you can easily beat the vector engines with serial code, especially using highly optimised libraries and multiple processors/cores/threads.

Get yourself a good quality numerical library (Google IMSL for a start), and write code to use their vector operations. If it ever finds its way on a "true" hardware vector platform (unlikely), it will automagically exploit those capabilities. On other platforms the vector operations will be implemented serially.

Re: Vector Processor

Hoff — Wed, 19 Mar 2008 22:18:49 GMT

The VAX systems with integrated SIMD were (all?) Rigel-class boxes. The associated VVIEF is available on other VAX boxes.

As for more recent SIMD options, they're quite viable for some applications and apparently successful in the market; there are quite familiar configurations with RISC processors with multiple SIMD engines, and more are in the planning stages.

All of which can be gotten to work on Alpha, depending on the application.

Re: Vector Processor

Robert Gezelter — Thu, 20 Mar 2008 06:12:25 GMT

FOX,

The Alpha architecture was also extended on the 21164 with the MVI series instructions to enable high performance processing of image and other multimedia data. I do not have the time at this instant to produce the citations, but there were quite a few papers published in various journals on this addition to the architecture.

The performance enhancing capabilities of these instructions would likely mean writing code directly in MACRO, quite possibly MACRO-64 (I do not recall if there is any support in the MACRO-32 compiler for MVI), which needless to say, would not be portable.

So, in a sense, ALPHA did, in the end, have some additions to enhance vector processing.

- Bob Gezelter, http://www.rlgsc.com

Re: Vector Processor

Bojan Nemec — Thu, 20 Mar 2008 07:37:43 GMT

FOX,

Some compilers (I am shure for C and CXX) have a qualifier for generating the code for a specific type of Alpha chip. This will speed up the program on Alphas with the same chip and probably slow down on others but you can recompile the programs for a specific Alpha.

If you have C or C++ compiler see HELP CC /ARCHITECTURE or HELP CXX /ARCHITECTURE.

Bojan

Re: Vector Processor

FOX MULDER_2 — Thu, 20 Mar 2008 07:58:49 GMT

Thanks to all.

It was merely a generic question,does not have anything to do with any application.

I have one more question to ask :
What are the techniques to do parallel computing..I mean how should a code be written to do a parallel computing.
An example will be very helpful.

Thanks

Re: Vector Processor

Peter_364 — Thu, 20 Mar 2008 10:32:26 GMT

FOX,

The best thing, to my knowledge, on Alpha and Itanium is using the pthread-library on an SMP-machine.
Search for pthread and you'll find a lot interresting examples.

Re: Vector Processor

Hoff — Thu, 20 Mar 2008 18:29:15 GMT

On OpenVMS, parallel processing can be achieved via KP threads APIs (available on recent OpenVMS Alpha, and available on OpenVMS I64), via POSIX threads, via ASTs ("sort of"), via processes operating across multiple servers, or via multiple processes on one multicore or multiprocessor server, or by a combination of these techniques.

Older OpenVMS application environments used the PPL library, though that OpenVMS library has largely been retired.

In terms of parallel processing capabilities, the OpenVMS tool-set is fairly limited and arguably fairly primitive in this regard, and implementations and environments including Erlang (including Mnesia), MPI, OpenMP, Xgrid, or other such are generally considered more advanced.

OpenVMS does provide the basics of parallel processing with its clustering and SMP and multiprocessing support, though you'll likely find more applications around that are using grids or Beowulf or other such.

As for a generic discussion of multicore, SMP and SMT as related to OpenVMS, see:

http://64.223.189.234/node/13

Synchronization and locking:

http://64.223.189.234/node/638
http://64.223.189.234/node/492

Alpha processor caching, shared memory, and memory barriers:

http://64.223.189.234/node/407

For an application that performs parallel processing on many platforms, the Apache web server is a wide-spread example. Apache is often configured with a herd of processes that can service incoming web requests, and the web server passes off these web requests to these processes.

I would tend to recommend a semi-recent college-level textbook covering introductory computer programming, as parallel processing, SIMD, MIMD, NUMA and such are all core concepts. For a more established but very valuable view, Knuth has a well-regarded series of books on core computing algorithms, the multi-volume Art of Computer Programming.

Various colleges also now have their courses and course materials on-line. You might check MIT or Harvard or such.

If you seek source code to solidify your knowledge of parallel processing and of synchronization algorithms, available search tools such as Google can be your friend. http://code.google.com or http://www.google.com. If you want to aim http://www.Google.com at a web repository of code for OpenVMS, do use the Google site keyword, and pick a repository site as a target such as "site:mvb.saic.com".

As for other sources for OpenVMS source code, the OpenVMS Frequently Asked Questions (FAQ) (http://www.hoffmanlabs.com/vmsfaq/) has a long list of sites where you can pick up source code related to OpenVMS. One site that's not indexed by Google (part of the dark web) but that has piles of OpenVMS source examples is accessible via the ITRC James search engine:

http://www11.itrc.hp.com/service/james/CPQhome.do

Re: Vector Processor

Dennis Handly — Sat, 22 Mar 2008 06:24:38 GMT

>Bob: As a RISC architecture, there is no "vector processing" instruction set as distinct from the regular instruction set.

>carefully written and well tuned code can achieve very high vector performance

Exactly. This is typically done by software pipelining. A loop can be doing multiple stages at once.

The IPF architecture has special branch instructions to set up these loops. It also has rotating registers.