<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: high CPU utilization on STEP/RET in Operating System - OpenVMS</title>
    <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215999#M97326</link>
    <description>Willem,&lt;BR /&gt;&lt;BR /&gt;an even better workaround would be to explicitly set a temporary breakpoint on the RETURN instruction source code line from this subroutine with:&lt;BR /&gt;&lt;BR /&gt;DBG&amp;gt; SET BREAK/TEMP %line x&lt;BR /&gt;&lt;BR /&gt;According to help, STEP/RETURN is the same as SET BREAK/TEMPORARY/RETURN;GO&lt;BR /&gt;&lt;BR /&gt;It may be a simple problem of how this functionality has been implementated on Itanium.&lt;BR /&gt;&lt;BR /&gt;Volker.</description>
    <pubDate>Fri, 25 Dec 2009 08:19:18 GMT</pubDate>
    <dc:creator>Volker Halle</dc:creator>
    <dc:date>2009-12-25T08:19:18Z</dc:date>
    <item>
      <title>high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215991#M97318</link>
      <description>OpenVMS 8.3-1H1, Intergity rx2620; System has not been patched since installation. &lt;BR /&gt;PASCAL (using RDO), RdB:&lt;BR /&gt;@@2:WGR&amp;gt; pascal/vers&lt;BR /&gt;HP Pascal I64 V6.1-116 on OpenVMS I64 V8.3-1H1&lt;BR /&gt;@@2:WGR&amp;gt; rdo sho ver&lt;BR /&gt;Current version of RDO is:  Oracle Rdb V7.2-200&lt;BR /&gt;&lt;BR /&gt;It concerns an interactive program, using SMG 'windowing' under_the_hood. Main program and one module build sources /DEB/NOOPT, rest ob objects from library, built without debug.&lt;BR /&gt;The compilation strings used (for all modules) is:&lt;BR /&gt;PAS*CAL == "PASCAL/G_FLOATING/ALIGN=VAX/USAGE=NOVOLATILE/ENUM=BYTE"&lt;BR /&gt;G_FLOATING since that is a recommendation from the RMDL pre-compiler.&lt;BR /&gt;Linked execuatble using /DEB.&lt;BR /&gt;No warnings or worse have been issued in any step of image creation.&lt;BR /&gt;&lt;BR /&gt;Run program, set breakpoint in module; on breakpoint: set mode screen, ^W to be able to step thrtough code. Now step/ret will cause excessive CPU utilization causing stalling other processes.&lt;BR /&gt;All database access has been executed before breakpoint; the program is wordking on an internal array (quite heavily and resursively).&lt;BR /&gt;&lt;BR /&gt;Other debug actvities show no problem at all. It's just that STEP/RET causes this problem.&lt;BR /&gt;&lt;BR /&gt;I won't rule out that bad allignment may be part of the problem, but I don't unerstand why that would be exposed so severely in step/return only.&lt;BR /&gt;&lt;BR /&gt;Can this be explained - adn, if possible, solved?</description>
      <pubDate>Wed, 23 Dec 2009 12:05:13 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215991#M97318</guid>
      <dc:creator>Willem Grooters</dc:creator>
      <dc:date>2009-12-23T12:05:13Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215992#M97319</link>
      <description>Willem,&lt;BR /&gt;&lt;BR /&gt;I think I can also reproduce this with a very small FORTRAN example. It seems to behave as expected on Alpha, but causes major CPU consumption on I64:&lt;BR /&gt;&lt;BR /&gt;        Program ITRC_1395846&lt;BR /&gt;        CALL SUB&lt;BR /&gt;        E N D&lt;BR /&gt;        SUBROUTINE SUB&lt;BR /&gt;        INTEGER*4       j /0/&lt;BR /&gt;        DO I=1,100000000&lt;BR /&gt;        J = j + 1&lt;BR /&gt;        END DO&lt;BR /&gt;        TYPE *,'J=',J&lt;BR /&gt;        RETURN&lt;BR /&gt;        E N D&lt;BR /&gt;&lt;BR /&gt;I tried DBG&amp;gt; SET BR SUB and DBG&amp;gt; GO, then DBG&amp;gt; STEP/RET. It takes a little while (depending on CPU speed of Alpha) and then reaches the breakpoint at the RET.&lt;BR /&gt;&lt;BR /&gt;If I run the same on OpenVMS I64, it uses vast amount of CPU (check with CTRL-T), before it finally reaches the RET breakpoint - it still hasn't, but I think it will...&lt;BR /&gt;&lt;BR /&gt;Let me guess: the implementation of I64 may cause a trap after executing each instruction and check, whether the RET has been reached, whereas the implementation on Alpha may just 'know' where the RET is and set a breakpoint directly.&lt;BR /&gt;&lt;BR /&gt;Volker.&lt;BR /&gt;</description>
      <pubDate>Wed, 23 Dec 2009 12:40:42 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215992#M97319</guid>
      <dc:creator>Volker Halle</dc:creator>
      <dc:date>2009-12-23T12:40:42Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215993#M97320</link>
      <description>Willem,&lt;BR /&gt;&lt;BR /&gt;if I look at the PCS (PC-sampling) data on the Itanium, most of the samples are in DEBUG.EXE, not in the original executing image. So my assumption about the implementation of STEP/RETURN on I64 may be right...&lt;BR /&gt;&lt;BR /&gt;Volker.</description>
      <pubDate>Wed, 23 Dec 2009 12:45:06 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215993#M97320</guid>
      <dc:creator>Volker Halle</dc:creator>
      <dc:date>2009-12-23T12:45:06Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215994#M97321</link>
      <description>Willem,&lt;BR /&gt;&lt;BR /&gt;to reduce the impact of this, just lower the priority of your process before starting to debug this piece of code with STEP/RETURN&lt;BR /&gt;&lt;BR /&gt;Volker.</description>
      <pubDate>Wed, 23 Dec 2009 12:48:54 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215994#M97321</guid>
      <dc:creator>Volker Halle</dc:creator>
      <dc:date>2009-12-23T12:48:54Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215995#M97322</link>
      <description>I wonder if this is related to the slower exception handling on I64?</description>
      <pubDate>Wed, 23 Dec 2009 17:22:42 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215995#M97322</guid>
      <dc:creator>Ian Miller.</dc:creator>
      <dc:date>2009-12-23T17:22:42Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215996#M97323</link>
      <description>Put it this way: the Itanium processor has its limitations where it comes to interruption handling - in general. Something to keep in mind....Lowering priority could be a workaround, in some cases. But wouldn't it be better if a real solution was offered?</description>
      <pubDate>Wed, 23 Dec 2009 20:41:52 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215996#M97323</guid>
      <dc:creator>Willem Grooters</dc:creator>
      <dc:date>2009-12-23T20:41:52Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215997#M97324</link>
      <description>&amp;gt;&amp;gt;&amp;gt;  I wonder if this is related to the slower exception handling on I64?&lt;BR /&gt;&lt;BR /&gt;Maybe, but unlikely: Volker would have reported to have seen PCs in LIBRTL.EXE or EXCEPTION.EXE.</description>
      <pubDate>Thu, 24 Dec 2009 12:20:58 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215997#M97324</guid>
      <dc:creator>H.Becker</dc:creator>
      <dc:date>2009-12-24T12:20:58Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215998#M97325</link>
      <description>Itanium is a batch engine, offloading instruction scheduling and predictive tasks to the compilers, and to Ispike where it's available.  The processor design goes through straight code very fast.  Branches and calls, and exceptions and traps tend to hammer Itanium performance.  And the debugger is close to the nadir of this design.  Now whether HP can determine how to speed this particular debugger case, that's another question, and one that only HP can answer.&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://www.cgo.org/cgo2004/papers/01_82_luk_ck.pdf" target="_blank"&gt;http://www.cgo.org/cgo2004/papers/01_82_luk_ck.pdf&lt;/A&gt;</description>
      <pubDate>Thu, 24 Dec 2009 13:55:58 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215998#M97325</guid>
      <dc:creator>Hoff</dc:creator>
      <dc:date>2009-12-24T13:55:58Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215999#M97326</link>
      <description>Willem,&lt;BR /&gt;&lt;BR /&gt;an even better workaround would be to explicitly set a temporary breakpoint on the RETURN instruction source code line from this subroutine with:&lt;BR /&gt;&lt;BR /&gt;DBG&amp;gt; SET BREAK/TEMP %line x&lt;BR /&gt;&lt;BR /&gt;According to help, STEP/RETURN is the same as SET BREAK/TEMPORARY/RETURN;GO&lt;BR /&gt;&lt;BR /&gt;It may be a simple problem of how this functionality has been implementated on Itanium.&lt;BR /&gt;&lt;BR /&gt;Volker.</description>
      <pubDate>Fri, 25 Dec 2009 08:19:18 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5215999#M97326</guid>
      <dc:creator>Volker Halle</dc:creator>
      <dc:date>2009-12-25T08:19:18Z</dc:date>
    </item>
    <item>
      <title>Re: high CPU utilization on STEP/RET</title>
      <link>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5216000#M97327</link>
      <description>Willem,&lt;BR /&gt;&lt;BR /&gt;I, for one, would like to hear the results of whether there were large numbers of faults resulting from unaligned data.&lt;BR /&gt;&lt;BR /&gt;While the DEBUGGER is admittedly a bad case for exceptions and branches, I would like to confirm that the problem is not correctable before settling for that conclusion. If the exceptions are for unaligned data, that is eminently correctable without a major redesign.&lt;BR /&gt;&lt;BR /&gt;- Bob Gezelter, &lt;A href="http://www.rlgsc.com" target="_blank"&gt;http://www.rlgsc.com&lt;/A&gt;</description>
      <pubDate>Sat, 26 Dec 2009 16:12:52 GMT</pubDate>
      <guid>https://community.hpe.com/t5/operating-system-openvms/high-cpu-utilization-on-step-ret/m-p/5216000#M97327</guid>
      <dc:creator>Robert Gezelter</dc:creator>
      <dc:date>2009-12-26T16:12:52Z</dc:date>
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  </channel>
</rss>

