topic Re: CHIPS port balancing in XP Storage

CHIPS port balancing

ionic_tease — Mon, 03 Sep 2007 11:28:04 GMT

When attaching hosts to the XP1024 front-end CHIP ports through a fabric switch, having four or more hosts from the switch mapped to one CHIP port would technically be overloading the ports? I'm also trying to understand the naming convention of the CHIP pairs in CV..C1 and C2 equals one CHIP pair?

Re: CHIPS port balancing

Amar_Joshi — Mon, 03 Sep 2007 12:07:12 GMT

Slotwise you have 2 slots occupied for a single CHIP pair (in slots 1x and 2x).

The first pair will have starting ports, depends upon CHIP configuration:

e.g. 16 Port CHIP board will have port: 1A 3A 5A 7A 1C 3C 5C 7C 1E 3E 5E 7E 1G 3G 5G 7G

In above example alternate ports are shared by a single microprocessor (MP0.. thru MP7)
MP0 shared be 1A & 5A
MP1 shared by 3A & 7A
MP2 shared by 1C & 5C
...
...
MP7 shared by 3G & 7G

So when you are populating the CHIP ports, there are simple guidelines:

-Always have dual path connectivity (1A/2A... 7G/8G)
-spread applications across multiple CHIP pairs (if you have more than single CHIP pair), this is to avoid any situation when there are multiple CHIP port failures and special cases need forcible replacement of XP parts.
-Keep the MP sharing in mind and not to put cluster servers on the shared CHIP ports (e.g. Host1 to 1A/2A and Host2 to 5A/6A)
-A total of hosts per MP should be balanced on all the MPs.
-Try NOT to mix various OS types on single CHIP port(say HPUX & Windows on 3C/4C)
-If you have performance numbers from applications, keep a max of 6000 IOPS per MP.

Hope this is enough for you to start learning about load balancing.

Re: CHIPS port balancing

ionic_tease — Mon, 03 Sep 2007 12:51:50 GMT

This is still confusing...CV has listed CHA-1P,
CHA-1Q, CHA-1R, CHA-1S, CHA-2V, CHA-2W, CHA-2X, and CHA-2Y. Each "CHA" has four ports associated with it.

Ex: CHA-1P ports: CL1-A, CL1-B, CL1-C, CL1-D

So are the "CHA" listed in CV are really the my CHIPs? CHA-1P and CHA-2V are a pair?

Re: CHIPS port balancing

Nigel Poulton — Tue, 04 Sep 2007 07:17:13 GMT

CHA-1P refers to a physical board that has multiple front-end ports on it. These may be
1A/5A
3A/7A
1C/5C
3C/7C
(the above are port numbers that physically reside on CHA-1P)

I have grouped two ports together on each line as on some boards a pair of ports share a single MP (micro processor).

The "CHA" part of the name indicates it is a CHAnnel package (contains front end ports). The "1P" part of the name is the physical slot number in the XP that it sits in.

These channel boards are purchased and installed in pairs. On board per cluster on the XP. When you buy a 16 port feature there will be 8 front-end ports on one baord installed in one cluster and 8 front-end ports on another board installed in the other cluster to make the pair. Clsuter here does not refer to OS or Application clsuter but the two clusters that comprise the XP.

Hmmmm this could be even more confusing if you are not familiar with the XP architecture..... so hope Im not making it more difficult for you.

Basically CHA-1P, CHA-1Q ,CHA-1R..... are not your CHIPs, they are the boards that your CHIPs sit on and there are multiple CHIPs per CHA...

HTH :-D

Re: CHIPS port balancing

ionic_tease — Tue, 04 Sep 2007 11:18:08 GMT

This is confusing...so the chips are CL1-A, CL1-B, CL1-C, CL1-D??

Re: CHIPS port balancing

Nigel Poulton — Wed, 05 Sep 2007 02:44:00 GMT

Yes the CHIPs (Channel Host Interface Processors) are CL1-A, CL1-B......

You have multiple CHIPs on each CHAnnel package such as CHA-1P

Re: CHIPS port balancing

ionic_tease — Wed, 05 Sep 2007 12:21:10 GMT

On the XP1024 is it good practice to segment different types of hosts (Sol,HP, AIX) on separate CHIP ports? For redundancy, could one map a ldev from one CHIP port on cluster1 to host1(hba0) and on a separate CHIP port on cluster2 to host1(hba1)?? This way if a cluster failed there would be a backup back to the lun on the second hba.

Re: CHIPS port balancing

Nigel Poulton — Wed, 05 Sep 2007 13:13:03 GMT

What you are asking about mapping and LDEV as a LUN on two CHIP ports for dual pathing is actually a best practice - i.e. CL1-A and CL2-A. You must make sure for redundancy that if you map the LUN on two ports that one port is in cluster 1 and the other in cluster 2. This is exactly what the cluster are for - redundancy. Also, you can map an LDEV to a LUN on as many ports as you want.....

As for separating different host OS's onto different ports I would suggest that this is overkill. You can do it but I do not think you will see any benefit to this (I have never seen it suggested as a performance enhancing practice). Although I suppose if a CHIP was only running in a single mode, e.g. HP then it might put less overhead on the MP. But I doubt this is noticeable.

The XP1024 is designed to be able to handle different host types on the same physical port using Host Storage Domains.

Re: CHIPS port balancing

ionic_tease — Thu, 06 Sep 2007 07:41:06 GMT

So to sum up that I've learnt from this thread, the "CHA" stands for "channel boards" that contain the front-end CHIP ports. The XP array has two clusters containing the channel boards.

When purchasing a channel board you must buy them in pairs (one for cluster 1 and the other for cluster 2).

So looking in CV, I have four pairs of channel boards.

CLUS_1 CLUS_2
===============
CHA-1P CHA-2V
CHA-1Q CHA-2W
CHA-1R CHA-2X
CHA-1S CHA-2Y

There are four CHIP ports per channel board.

CHA-1P CHA-1Q CHA-1R CHA-1S
=================================
CL1-A CL1-E CL1-J CL1-N
CL1-B CL1-F CL1-K CL1-P
CL1-C CL1-G CL1-L CL1-Q
CL1-D CL1-H CL1-M CL1-R

So using the above data, where are my microprocessors located at then and how should I avoid over utilizing one micro-port?

Re: CHIPS port balancing

Nigel Poulton — Fri, 07 Sep 2007 02:29:25 GMT

Hmmmm cant remember for 100% and I dont have my notes for the XP1024 with me but if you only have 4 ports per Channel package (8 across the pair) then you probably have 1 MP per port, no ports sharing MPs. In fact Im fairly certain of that.

Re spreading the load. This is very specialised and depends on workload characterisitics, random vs sequential etc.

Re: CHIPS port balancing

Amar_Joshi — Fri, 07 Sep 2007 16:23:05 GMT

For assigning 1, 2, 3 & 4 points, you can learn that much only... :) (joking, as you joked with people who took pain and wrote long paras for you and you assigned peanuts)...

Anyways, you are right with all the numbering for cluster, board and ports.

I haven't seen any of the 4 port card in my career but they are not sharing the MPs. Each port uses dedicated MP, so you don't need to be worried about overloading MPs.

Re: CHIPS port balancing

ionic_tease — Sat, 08 Sep 2007 21:07:03 GMT

Nigel,

Thanks! You've been most helpful and patience with me on this.

Amar,

Thnks for your comments. Here's a couple of beans for ya! :)