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Gen-Z: Core Specification 1.0 released

 

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By Curt Hopkins, Managing Editor, Hewlett Packard Labs

In February, the Gen-Z Consortium, formed to develop open-source solutions to processing and analysing huge amounts of data in real time, released Core Specification 1.0.

According to the press release, this specification will “will enable microchip designers and fabricators to begin the development of products enabling Gen-Z technology solutions.”

In October 2016, HPE joined other industry leaders in founding Gen-Z in an effort to develop a new universal interconnect that would enable simpler and more powerful computer architectures. The goal was to develop a new standard interconnect and protocol – one single, open, high-performance interconnect.

“Making a custom silicon chip is a significant investment in time and resources. Clearly, an established specification enables companies to invest with confidence and will accelerate Gen-Z to market,” says Alain Andreoli, Senior Vice President and General Manager of HPE’s Hybrid IT Group.

In other words, while launching the consortium was a gesture of possibility that laid the groundwork for a more welcoming road to market, Specification 1.0 opens that road.

Andreoli describes 1.0 as a “memory-semantic protocol” which “will allow any component – processing, memory, accelerators, networking – to talk to any other component as if it were communicating with its own local memory using simple commands.”  

The implications of taking this open road are, according to Ian Brooks, HPE’s European Head of Innovation, significant.

“The eventual deployment of GenZ based solutions, alongside workload specific compute engines and non-volatile memory will allow help us to make ever more realistic simulations of the real world and accelerate progress on some of society’s greatest computational challenges.”

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Curt_Hopkins

Managing Editor, Hewlett Packard Labs