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HPE partnered with Mentor to launch the LightSuite photonic compiler: here’s why

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By Ashkan Seyedi, Research Scientist, Hewlett Packard Labs

Editor’s note. Mentor, a Siemens company, has announced the launch of the first automated photonics compiler, created in cooperation with Hewlett Packard Labs.

This new tool enables companies designing the world’s largest integrated photonic devices to describe designs in the Python language. The compiler then automatically generates designs that are ready for fabrication. The resulting design is “Correct by Calibre” – with the implementation precisely guided by Mentor’s Calibre RealTime Custom verification tool.

This tool enables designers to generate and update large photonics layouts in minutes versus weeks.

Hewlett Packard Labs photonics research scientist Ashkan Seyedi explains why this tool is important to the future of computer design beyond Moore’s Law.

Analog, digital, and photonic

Today’s electronics design world is primarily divided into two domains: analog and digital electronics, collectively referred to as mixed-signal design. By moving silicon photonics into the commercial space to solve the technical challenges that exist, we are also adding a third domain: optical.

This, then, causes a snag. The current field of expert circuit designers that drive the massive volume of components in the electronics market (think cell phones, processors, data center switches, and GPUs) don’t know the difference between a fermion (electron) and a boson (photon). To reach global adoption of photonics (moving data with light), we have to solve this problem at scale. We could do this by enrolling each and every mixed-signal designer in classes and essentially get them a Master’s in photonics. Or, we can make the optical components look like the well-known electronics components that the mixed-signal design folks know, love, and use daily.

The current design cycle for a pure electronics chip starts in the schematic world. Think back to high school where resistors were represented by a jagged line of consummate V’s, capacitors were two parallel lines and inductors were squiggly swirls. These symbols represent “ideal” devices from which complicated circuits that enable logic, communication, and timing are derived. Due to the 40-plus years of industry maturity, today a designer hardly ever deals with the physical representation of these devices, which look nothing like their schematic counterparts.

The design cycle stays in the schematic world for many iterations, where the circuits are simulated, tweaked, re-simulated and optimized until all the required metrics of performance for that specific design are met. From there, a simple button is clicked where those schematics, and their abstract connections, are converted to a physical layout and real-life connections that will be fabricated in the actual semiconductor material.

This “translation” is done behind the scenes by the design automation and placement/routing algorithms that come from a PDK – product design kit – that a designer gets from a specific foundry like TSMC, GlobalFoundries, or Samsung. This translation is also very specific to the design and process rules of that specific foundry to which the PDK belongs. These rules and algorithms follow Manhattan rules, just like the grid structure formed in NYC by its streets and avenues. This property is leveraged to simplify the geometry of devices by taking advantage of a grid of vertices on which the polygons fall. For example, you can define a rectangle with only one coordinate pair for a corner, length and width. The regular, grid-like nature of Manhattan structures makes the placement and routing a straightforward process.

In contrast, optical devices in silicon on insulator (SOI) wafers are like stand-up basses – big and curvy. A waveguide, the device used to route the optical signal on-chip, often has to make complex curves and bends in order to optimally connect various optical components. These curves create polygons whose vertices may not fall on the square grid, thus creating challenges for the traditional automated algorithms developed for the electronics industry.

Furthermore, the connections between the optical ports of various devices like waveguides, optical filters, modulators, etc., require precise alignment of the geometry down to the single nanometer scale; a requirement roughly 10x smaller than that of electronics components. This, then, places even more stringent requirements on the digitization and routing algorithms used for optical devices.


The Hewlett Packard Labs integrated photonics research team worked with a global team of developers at Mentor to develop a tool that solves these exact problems. Labs provided device and photonic circuit examples that are used for high-bandwidth optical interconnects, optical switching, and even optical computing.

Using these examples, along with feedback from Labs on the software workflow, inputs, and behind-the-scenes implementation, Mentor’s team of developers iterated many versions of this tool to enable a smooth workflow.

The tool that we’ve developed in a collaboration with Mentor solves this problem of automated placement and routing of the optical devices without requiring the designer to know the nuances of photonics or to ever really do any physical layout by hand.

Thanks to this exciting new offering, the mixed-signal designer need not ever see any­ physical photonics components until the very end of the design cycle. This solution is significantly more cost-effective and scalable than sending all of those designers back to grad school!

As we produce more and more extraordinary solutions to the obstacles facing computing, like speed limits and exponential increases in energy use, expect eccentric solutions to increasingly be the norm. And expect those solutions – like photonics and the LightSuite compiler – to be increasingly packaged in easier-to-use forms, making it easier to do the harder things the end of Moore’s Law will demand.

Photo by Chris Arock on Unsplash

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Managing Editor, Hewlett Packard Labs