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Jessica_Visser

Silicon Innovation Brings Technology to Life at Hewlett Packard Labs


Hewlett Packard LabsHewlett Packard Labs

There’s no doubt that the future is bright for silicon innovation at Hewlett Packard Labs.  The chip design teams at Labs have a long history of leadership designs, dating all the way back to the 1980s with PA-RISC processor design and progressing through Itanium processors, Superdome systems, iLO systems management chips, Memory-Driven Computing architectures, Gen-Z memory fabrics, and a new system prototype demonstrating massively parallel computing capabilities.

Why is there a pressing need for continuous advancements in silicon design?

While there has always been an insatiable demand for more computing horsepower, the consumption patterns have changed.  The explosion of data, the expectation of nearly instantaneous response, and the maturation of Moore’s Law have placed a renewed emphasis on silicon design.  We can no longer expect general-purpose processors to provide large annual increases in per-core performance, nor can we expect these processors to excel at some of the newer applications such as machine learning, inference at the edge, and vision-aided navigation. Specialized processing is required, and Hewlett Packard Labs has chips such as the Dot Product Engine (neuromorphic computing accelerator) with innovative analog circuits that excel at machine learning applications.

Beyond computation, there is also an exponential growth in communication required between devices.  As the bandwidth increases, the distance that can be supported decreases when using traditional copper-based solutions.  Most people are familiar with the optical fibers connecting continents, cities, or datacenters, but future data rates will make photonics-based communication necessary even within a single rack of computing equipment or within a standalone server.  The challenge is finding photonic solutions that are not only capable of covering long distances, but are also cost-effective when replacing traditional short-haul interconnects such as copper cables or traces on a printed circuit board.

At Hewlett Packard Labs, our mission is to drive new technologies that create disruptive innovations for solving the toughest customer problems. Without a great silicon design team, it is impossible to bring to market innovations such as emerging accelerator technologies or new photonic devices. Within Labs, silicon engineers partner with researchers to design and verify circuits, algorithms, functionality, and firmware that bring advanced technologies to life and solve the most complex computing challenges.

What are some examples of silicon innovation at HPE?

Silicon to secure every HPE Server

Labs has created multiple generations of the iLO (Integrated Lights Out) chipset used for HPE ProLiant, Apollo, Synergy, and EdgeLine servers. iLO provides industry-leading security by creating a Silicon Root of Trust for the hardware boot process.  Features in the silicon are used to create an immutable fingerprint that is used to protect from compromised firmware.

Silicon in the race to Exascale

Labs has also completed the “PathForward” program in collaboration with the U.S. Department of Energy.  The world is in a race to build Exascale (10^18 operations per second) computers to solve the toughest problems facing society today, such as global-warming and predicting the spread of a pandemic, but efficiently coordinating the required tens of thousands of compute and storage elements is an incredibly daunting task.  Our PathForward system prototype demonstrates how we can get there by advancing technologies previously created to enable Memory-Driven Computing architectures.  We have proven the benefits of the Gen-Z interconnect protocol and Hyper-X topology for building distributed systems that are scalable and resilient to traffic congestion in the network. These are new technologies not yet broadly available in the industry, so our silicon design engineers blazed the trail by refining the specifications, implementing the protocol blocks, verifying the functionality, performance, and fault-tolerance features, and delivering a fully-verified chipset for the system prototype.  This could not have been done without dedicated circuit-design teams building the custom IP blocks, such the low-latency switch core, high-performance links (SERDES), and configurable clock units.

Silicon for optical solutions

Labs has advanced the packaging technologies needed to connect multiple chips within a single package to achieve high performance at lower cost and power.  We focus on capability, scalability, and flexibility – designing and combining “chiplets” in different ways to satisfy requirements for functionality, bandwidth, and cost. The most complex combination was five chiplets co-packaged with ten Labs-designed optical modules.  This 60-port, high-bandwidth, low-latency switch delivers over 12 terabits per second of aggregate bandwidth, which is roughly equivalent to 12,000 high-performance home internet connections of Gigabit Ethernet.

The Hewlett Packard Labs innovation in this experimental switch module is incredible!  It required the industry’s largest silicon interposer to realize the value of the fully-integrated optical solution, and it was built using high volume production methods that deliver industry-leading capability, cost, performance, and reliability.

What excites me most about silicon design technology?

The world never stops changing.  The more capabilities we deliver with our advanced silicon, the more the public demands from us.  Over the past few years, HPE has merged with SGI and Cray, adding even more engineering expertise and an increased customer base for scalable, value-add computing platforms.  By combining talent between Labs and the business groups, we will be accelerating the adoption of advanced technologies that solve the world’s toughest problems.


Pat Knebel.jpgAbout the author
Patrick Knebel is an HPE Fellow and Vice President at Hewlett Packard Labs, specializing in silicon design, advanced technologies, and system architectures for scalable computing platforms.

 
 

 

 

 

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