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I would like to know about "N Class Processor Architectures".

 
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Katsu39
Frequent Advisor

I would like to know about "N Class Processor Architectures".

Hello All;

I had a LPMC for I-cache parity error on processor#3 of N class.
I understood that was no problem,Coz it was recovered from the OS.

But, I'd like to know about "N Class Processor Architectures".

1. Where are I-cache and D-cache?
2. How to use them.
3. I'd like to get the "Block Diagram".

Please help;
Regards
Katsu
6 REPLIES 6
Joseph Loo
Honored Contributor
Solution

Re: I would like to know about "N Class Processor Architectures".

hi,

u may like to refer to this:

http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,2533,00.html

on PA-RISC 8500:
http://www.hpl.hp.com/techreports/98/HPL-98-126R1.html

regards.
what you do not see does not mean you should not believe
Brian M Rawlings
Honored Contributor

Re: I would like to know about "N Class Processor Architectures".

Hi, you might want to reconsider the "no problem" part. All the instruction and data caches are part of the processor chip on this noble old beast, and the error message you got is a warning bell. It's nice that the OS was able to retry and recover without crashing, but it may not always be able to do that.

Parity errors aren't the same as ECC corrected errors. Parity only signals that an error has occured, not which bit was bad or whatever. ECC (main memory correction bits) allows the bad bit to be re-created, which is much less risk of a panic/crash. Occasional ECC errors are no big deal, and HP won't replace memory just because of one or two errors per month (by policy).

If parity errors show up on a processor cache or data bus, however, with any regularity at all (like, a couple of times in a month or week), that processor should be replaced. The likelihood that a parity error like the one you mention can be recovered from is not a good risk. Any pattern of such failures is a red flag, and should be reported to HP. They should not give you any grief at all about replacing it (if you are on support).

Oh, you use the I-cache and D-cache every time you do anything at all with the N4000. Since the OS and apps are doing all they can possibly do with them... you can't do any more than you're already doing... unless you are a serious Application programmer. In which case, you'd already know all this.

Regards, --bmr
We must indeed all hang together, or, most assuredly, we shall all hang separately. (Benjamin Franklin)
Alex Lavrov.
Honored Contributor

Re: I would like to know about "N Class Processor Architectures".

If you have more than 2-3 LPMC on specific CPU, this CPU *must* be replaced or your server may crash.
I don't give a damn for a man that can only spell a word one way. (M. Twain)
mits
Respected Contributor

Re: I would like to know about "N Class Processor Architectures".

I would suggest you will check the EMS documents to learn how the online diagnostic handles the CPU cache parity error.

Data sheet:
http://docs.fc.hp.com/en/diag/ems/emd_lpmc.htm
Event detail:
http://docs.fc.hp.com/en/diag/ems/lpmc_em.htm
Kent Ostby
Honored Contributor

Re: I would like to know about "N Class Processor Architectures".

I-cache = Instruction Cache
D-cache = Data Cache

These two CHIPS are on the CPU board and are used to store the address of either data or instructions that are needed.

I agree with those above who say that if you get multiple LPMCs on a CPU board you want to replace the board.

"Well, actually, she is a rocket scientist" -- Steve Martin in "Roxanne"
Katsu39
Frequent Advisor

Re: I would like to know about "N Class Processor Architectures".

Hello All;

Thank you for reply, and good infomation.

We are going to replace the Processor, if that will happen again.

Regards;
Katsu