Processor Technology

[Jay Gomez]

Hi,

Good day to all.
One of our client is asking if what processor technology has CPU to CPU communication capability at the chip level.
Can anyone provide me a write ups or white paper on this technology?
If ever, what servers on HP has this kind of processor.

Hope someone could help me on this.
Thanks in advance.

jay

[Robert-Jan Goossens]

Hi Jay,

Check below link for more information.

http://www.arcade-eu.info/overview/2004/itanium.html#itanium

http://www.arcade-eu.info/overview/2004/integ-superd.html#integ-superd

http://www.arcade-eu.info/overview/2004/pa-risc.html#pa-risc

http://www.arcade-eu.info/overview/2004/superdome.html#superdome

Hope this helps,
Robert-Jan

[Jay Gomez]

Hi Sir,

Thanks for your reply..
I am just curious about the question of my client... What does he mean on the processor technology "CPU to CPU communication capability at the chip level" ... We actually positioned RX4640 and RX7620 servers. Are this servers meets the processor technology requirements?
Can you help me provide a whitepaper on this processor technology...
Hoping for your very kind response.

Thanks,
jay

[Jay Gomez]

Hi...
Based from the link that you've posted..
I did try to check the Itanium2 processor since it is the processor of the RX servers,how will I explain to the client the technology that they are saying coz i dont see any explaination about the CPU to CPU communication capability at the chip level on the article about Itanium2.

[Ivajlo Yanakiev]

I thinks that any multi processors server have communication CPU to CPU ot low level

[Ivajlo Yanakiev]

REad that one:

http://search2.intel.com/corporate/default.aspx?culture=en-US&q=itanium+2

[Alzhy]

All system architectures utilize some form of a cross-bar switched architecture to enable "cpu to cpu" communication with very low latencies. AS far as CPU architectures -- the trend is to put more CPU cores (complete cpu modules) on a single chip/die or CPU architectures than enable mutiple threads - thereby increasing its ability to do more processing than previously possible.

HP's newest PARISC and Itanium2 CPUs employ dial cores but am not sure about how multi-threaded it is.

Sun's and IBM's scientists (and maybe HP) are developing alternative chip to chip communications that no longer uses the tradional copper/PCB interconnects. There've been demonstrations and POC's already but actual use on systems may be years away.

See this:

http://research.sun.com/spotlight/2004-09-20.feature-proximity.html

[Ted Buis]

I wonder who has been talking to your client and selling them on this "feature". It sounds like something AMD Opteron or the Alpha EV7 might claim since those chips do directly connect, but communication to me implies much more, and processor chips don't address registers on other processor chips, so to calling it CPU to CPU communication seems like stretching it to my thinking. HP's DL145 and DL585 use the AMD Opteron and HP's Alpha servers use a similar approach. That doesn't make the newest Alpha Servers as fast as an Integrity Superdome, so I don't see this technique as a critical factor in processor chip design. HP has internal documents that compare chip architectues, but unless you are a computer scientist, you are likely to be mislead by some of the "features". I suggest that customers judge the designs based on their abilities to do real workloads, such as SAP or whatever their intended application is. Different architectures perform quite differently on different jobs. Itanium has proven itself to be very good at most applications for systems that need 64-bit addressing or need to scale beyond 4 processors.

[Robert Gezelter]

Jay,

Without a more complete definition, the term "CPU To CPU communication" is essentially undefined.

At the lowest level, inter-CPU doorbell interrups are a form of inter-processor communication available on every multi-processor system for approximately the past two decades. The details of the mechanisms vary, as do the efficiencies. Absent a more detailed situation, and a complete context, the question as asked is not clear.

As to questions concerning systems based on the Alpha EV7-series designs, the interchip communications are primarily about memory references, not the overt interprocessor communications, which are several orders of magnitude less frequent. A significant difference between the EV7-series systems and earlier systems is in the faster and more uniform access speeds to main memory shared between the processors.

It is important to note that I am dramatically simplifying the situation to keep the reply reasonable for this forum. For a client situation, I would have to look at the details of the situation and the details of the systems to determine the actual important and impact of the different architectures.

I hope that the above is helpful.

- Bob Gezelter, http://www.rlgsc.com