ProLiant Servers (ML,DL,SL)

Low efficiency xeon e5 2696 v2 processor in the HP ProLiant DL380p Gen8 server

 
gallanonimus
Occasional Visitor

Low efficiency xeon e5 2696 v2 processor in the HP ProLiant DL380p Gen8 server

My CPU
Test in RAMDRIVE. Memory is QUAD CHANEL. Why only such a low result?

 
 

https://www.cpubenchmark.net/cpu.php?cp ... Hz&id=2039
Should be
Single Thread Rating: 1652
Cross-Platform Rating: 35,585

https://www.cpubenchmark.net/cpu.php?cp ... Hz&id=2039

What's the nature of lower efficiency?

 


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SUCESS i changed in BIOS evry MAX PERORMANCE and now is better. No CPU changes ;/

2 REPLIES 2
Anu_K
HPE Pro

Re: Low efficiency xeon e5 2696 v2 processor in the HP ProLiant DL380p Gen8 server

Hello,

Looks like enabling the power management settings to Maximum on the server had improved the performace. You can refer to RBSU user guide at https://support.hpe.com/hpesc/public/docDisplay?docId=c00191707 Pg. 45 to understand more about this.

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AmRa
HPE Pro

Re: Low efficiency xeon e5 2696 v2 processor in the HP ProLiant DL380p Gen8 server

Below are description for power profile options within RBSU.

 

Setting a power profile

1.       From the System Utilities screen, select System Configuration  BIOS/Platform Configuration (RBSU)  Power Management  Power Profile and press Enter.

2.       Select a setting and Enter.

·         Balanced Power and Performance (default)—Provides optimum settings to maximize power savings with minimal impact to performance for most operating systems and applications.

·         Minimum Power Usage—Enables power reduction mechanisms that can negatively affect performance. This mode guarantees a lower maximum power usage by the system.

·         Maximum PerformanceDisables all power management options that can affect negatively affect performance.

·         Custom—Enables you to configure settings for your environment.

3.       Press F10.

 

To select a Power Regulator mode:

1.       From the System Utilities screen, select System Configuration  BIOS/Platform Configuration (RBSU)  Power Management  Power Regulator and press Enter.

2.       Select a setting and press Enter.

·         Dynamic Power Savings Mode (default)—Automatically varies processor speed and power usage based on processor utilization. This mode uses an ROM-based algorithm to monitor processor activity. It can reduce overall power consumption with little or no impact to performance, and does not require OS support.

·         Static Low Power Mode—Reduces processor speed and power usage. Guarantees a lower maximum power usage for the system. This mode is useful in environments where power availability is constrained and it is critical to lower the maximum power use of the system.

·         Static High Performance ModeProcessors run in the maximum power and performance state, regardless of the OS power management policy. This mode is useful in environments where performance is critical and power consumption is less important.

·         OS Control Mode—Processors run in their maximum power and performance state at all times, unless the OS enables a power management policy.

3.       Press F10.

 

To select a minimum processor idle power core C-State setting:

1.       From the System Utilities screen, select System Configuration  BIOS/Platform Configuration (RBSU)  Power Management  Minimum Processor Idle Power Core C-State and press Enter.

2.       Select a setting and press Enter.

  • C6 State (default—lowest) — Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. In addition to flushing core caches core architecture state is saved to the uncore. Once the core state save is completed, core voltage is reduced to zero. During exit, the core is powered on and its architectural state is restored.
  • C3 State—Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the core’s caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.
  • C1E State—C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state.
  • No C-statesThe normal operating state of a core where code is being executed.

3.       Press F10.

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