EFI Addressing

[mhm]

Dears,

I have question about the SCSI efi H/W addressing, basically I understand how to map between the HP-UX H/W address and the EFI H/W address for the cell-based systems like:

ACPI(vendor,cxx)/PCI(d|f)/SCSI(PUNt,LUNl)/HD(Partp,hex)

As an example:
1/0/4/1/0.8.0
would be in EFI H/W address:
ACPI(vendor,104)/PCI(1|0)/SCSI(PUN8,LUN0)/HD(Part1,hex)

why sometimes we have SCSI hardware paths like:
4/0/1/1/0/4/0.0.0 (more two digits)
which in the form:
Acpi(HWP0002,PNP0A03,501)/Pci(1|0)/Pci(4|0)/Scsi(Pun0,Lun0)/HD(Part1,hex)

Why there is two Pci addresses?

[Torsten.]

Maybe due to a combo card with a PCI to PCI bridge on it? I never noticed this so far ...

[Michael Steele_2]

Alt and pri paths to a lun? Best guess if you're using 11.31. However, from this table this is normal

Table 5-10 Disk and Removable Media I/O Paths
Slot Path
Disk Drives
Slot A ACPI(HWP0002,0)/PCI(2|0)/SCSI(Pun0,Lun0)/HD(Part1,SigD4EE0000)
Slot B ACPI(HWP0002,0)/PCI(2|0)/SSI(Pun2,Lun0)/HD(Part1,SigD4EE0000)
Slot C ACPI(HWP0002,100)/PCI(1|0)/PCI(1|1)/SCSI(Pun0,Lun0)/HD(Part1,SigD4EE0000)
Slot D ACPI(HWP0002,100)/PCI(1|0)/PCI(1|1)/SCSI(Pun2,Lun0)/HD(Part1,SigD4EE0000)
Removable Media
Slot ACPI(HWP0002,0)/PCI(2|1)/SCSI(Pun2,Lun0)/CDROM(Entry0)

[Robert_Jewell]

The multiple PCI(x|x) entries are in fact due to PCI to PCI bridges.. This is compounded further with PCI express backplanes that can be found in newer systems. For example the following is a path for a PCIe I/O slot in an rx3600:

Acpi(HPQ0002,PNP0A08,600)/Pci(0|0)/Pci(0|0)/Pci(1|0)/Pci(0|0)

And that's without a card installed!

-Bob

[Michael Steele_2]

Oh, well that interesting. From google I'm deducting that 2 32bit PCI buses are joined together into one 64 bit PCI bus.

Is this correct?

I.e.

82467GXâ The PCI eXpander Bridge (PXB) provided two 32-bit, 33MHz PCI interfaces or a single 64-bit, 33MHz PCI interface to the SAC.

[Robert_Jewell]

Thats a good way to think of it. Each double-speed bus is consisted of two ropes (or data paths) coming from the main IO controller to the local bus adapter. A double speed PCI slot is the end result.

The zx2 systems dynamically assign bus numbers to the LBA's as they are detected; plug and play topology of sorts (which is why you see the PNP notation in the address).

It makes things a bit more complex, but there is more flexibility allowing more options such as PCIe combo backplanes and faster slots.

-Bob