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Difference between Itanium and RISC based Technology

 
FOIS CRIS
Occasional Contributor

Difference between Itanium and RISC based Technology

Kindly update the technology difference between Itanium & RISC based technology.
4 REPLIES 4
Ivan Ferreira
Honored Contributor

Re: Difference between Itanium and RISC based Technology

Theorically, for HP, Itanium is the evolution of the RISC technology. RISC has reached a level that cannot be improved, so Itanium was created. Both are true 64 bit processors. But, probably, the real thing is that maintining a processor is too expensive and is more rentable to use Intel's technology.

See also:

http://www.intel.com/performance/server/itanium2/risc/cpu.htm
Por que hacerlo dificil si es posible hacerlo facil? - Why do it the hard way, when you can do it the easy way?
Mridul Shrivastava
Honored Contributor

Re: Difference between Itanium and RISC based Technology

Earlier we can't install other flavours of OS like linux, Windows etc on RISC servers. With Itanium servers we can install multiple OS on the single Itanium server. As there is a lot of competition in market and HP realise that they have to build those kind of servers where other Os also can be installed. So HP & Intel is doing it jointly. There is some new features also like EFI which gives us more flexibility in maintaining the multiple OS.
Time has a wonderful way of weeding out the trivial
FOIS CRIS
Occasional Contributor

Re: Difference between Itanium and RISC based Technology

As I come to know that Itanium based machine are not RISC based m/c. They are EPIC based machines. Know kindly tell me the diffrence between RISC and EPIC based technology and the advantages over each other. Which is benificial and how.
Mridul Shrivastava
Honored Contributor

Re: Difference between Itanium and RISC based Technology

Yes u r right that they use EPIC.
The Itanium Processor Family (IPF) is based on the EPIC (Explicitly Parallel instruction Computing) architecture developed by HP Labs. EPIC architecture far surpasses the sequential nature of today's processor architectures by allowing the software to communicate explicitly to the
processor whenever operations can be done in parallel. It delivers the enhanced performance needed for the servers of the future.

For more info i m attaching the docs
Time has a wonderful way of weeding out the trivial