The MCA(Machine Check Architecture) for x86 processors.

[chuckk281]

This is what I have been waiting to see on X86 world. The MCA(Machine Check Architecture) has already been on Itanium since it’s beginning.

Starting from G7 generation, it’s also implemented to X86 generation architecture. It will help to isolate cpu, memory and IO parity, etc. errors.

http://en.wikipedia.org/wiki/Machine_check_architecture

However all things are not equal as our Itanium friends already know.

The Machine Check Exception architecture is nowhere near as rich as in Itanium. This is clearly seen by the fact below you’ve got 4 registers. In Itanium you have up to 100Kb of information (the spec for x64 is a max of 1Kb!!).

A machine check exception like this points to either the CPU cache, the memory controller (thus the CPU) or an HT [AMD]/QPI [INTEL] link (which could then lead to I/O I suppose). In Linux there are some decoders for this that you can add, and are pretty good (amusingly they’re written by  Intel engineers but decode for both vendors). In Windows you should have an eventlog entry which you can view, since the WHEA architecture should retrieve the MCA and propagate it to the Windows’ System Event Log. 

As x64 matures, I’m sure the MCA architecture for it will improve. On the DL980  there has already been significant steps….

Is this type of info important to you? Do you care or use MCA info?