How to write a Complex Makefile

[CA1490051]

Hi All,

First of all, i wish a happy and Properous New Year 2008 to all.


Now, i am trying to write a makefile which runs multiple makefiles present in different directories.

Here is my example make file if i try yo run the same It gives the error message as dont know how to run

Dont Know How to make ./GenerateBVF/Src

I am not understanding where i am going wrong. Can any one help me out of this,
Please find the Makefile attached.

thanks and regards
Vikram

[Hasan Atasoy]

hi ;


sub-GenerateBVF :./GenerateBVF/Src/$(MAKEFILE) FORCE
$(ISDIRPRESENT) GenerateBVF || echo GenerateBVF doesnt exist
$(MAKEFILE) -f GenerateBVF/Src/$(MAKEFILE)



make -f makefile

will help you.


Hasan

[CA1490051]

Hi Hasan,

I have changed the last line as follows
make -f GenerateBVF/Src/$(MAKEFILE)

i.e. my Makefile looks as below now

sub-GenerateBVF : GenerateBVF/Src/$(MAKEFILE)
$(ISDIRPRESENT) GenerateBVF || echo GenerateBVF doesnt exist
cd GenerateBVF/Src make -f GenerateBVF/Src/$(MAKEFILE)

But , for this the error message is as follows

"Dont know how to make bvfWriter.cpp"

Where bvfWriter.cpp is the file which i want to compile throught the Makefile that is present in the directory GenerateBVF/Src

Can some one correct me where ia m going wrong here.

thanks and regards
Vikram

[CA1490051]

Hi All,

I am able to solve this problem .

The solution is we have to give the make command in the same line when we execute the "cd" command as follows

@cd GenerateBVF/Src ; make

The makefile is working fine.

But, i am not understanding what is the meaning of '@' at the beginning of the line.

Befoer closing the thread i would like to know the meaning of '@'


Can any one help me out for this..

thanks and regards
Vikram

[CA1490051]

Hi All,

I am able to solve this problem .

The solution is we have to give the make command in the same line when we execute the "cd" command as follows

@cd GenerateBVF/Src ; make

The makefile is working fine.

But, i am not understanding what is the meaning of '@' at the beginning of the line.

Befoer closing the thread i would like to know the meaning of '@'


Can any one help me out for this please..

thanks and regards
Vikram

[Dennis Handly · Accepted solution]

As you found out, you need to be aware that each line in a makefile rule is executed by a separate shell. That's why you see lines with ";" and with trailing "\".

$(ISDIRPRESENT) GenerateBVF || echo GenerateBVF doesnt exist
cd GenerateBVF/Src; $(MAKEFILE)

The code here will try to cd even if it doesn't exist. You may want to add an exit 1 after the echo:
$(ISDIRPRESENT) GenerateBVF || ( echo GenerateBVF doesnt exist; exit 1 )

>Before closing the thread I would like to know the meaning of '@'.

It means don't print the line when executing the makefile. I would suggest you remove all leading "@" from your makefile because evil "@" makes them hard to debug. Especially when going from one makefile to another.

The only lines that should have "@" are echo or common code that never fails. :-)

http://docs.hp.com/en/B2355-60130/make.1.html
Command lines are executed one at a time, each by its own shell. Each command line can have one or more of the following prefixes: -, @, or +.

[OldSchool]

You also might want to look at "Managing Projects with Make" published by O'Reilly

http://www.oreilly.com/catalog/make2/