The Alpha 21264 series EV6 processor has a so-called Harvard Architecture level one cache design used for its on-chip processor cache, with a 64 KB instruction cache and a 64 KB data cache.
The EV6 level one cache is set-associative, virtually indexed, physically tagged, and writeback.
The 1 GHz Alpha EV6 processor configurations within the AlphaServer ES45 series systems have an off-chip level two cache of 8 MB using 250 MHz DDR.
The 1.25 GHz Alpha EV6 processor configurations within the AlphaServer ES45 series systems have a level two off-chip cache of 16 MB using 313 MHz DDR.
The EV7-based AlphaServer ES47 series system has far smaller caches, but its caching efficiency and its cache performance is equivalent to that of the (far larger) cache found on the EV6-based AlphaServer ES45 EV6 series. And this is due in no small part to the significantly higher off-chip bandwidth of the EV7 series processor. EV7 bandwidth to local main memory is twice as fast as EV6 bandwidth to its level two processor cache.
In isolation, all discussions of processor cache size should be approached cautiously.
XFC and other OpenVMS system caches can be far, far, far larger. The above addresses the hardware caches found AlphaServer ES45 EV6-based systems.
Stephen Hoffman
HoffmanLabs
