How to find the RP5470 CPU Line Width

[Karl_]

Hi All,

How can we find the "line width" of a cpu? The costums is looking for the "line width" of the RP5470 CPU that we shipped to China.

Thanks,

Karl

[Eknath]

Hi Karl,

Look at
http://forums1.itrc.hp.com/service/forums/questionanswer.do?threadId=856994
or
http://docs.hp.com/en/rp54xx_Update/rp54xx_Update.pdf

Cheers!!!
eknath

[Karl_]

Hi eknath,

The pages you referred do not have "line width" on it. Based on your reply, does "line width" refer to CPU speed? Scree size?

Best regards,

Karl

[Robert-Jan Goossens · Accepted solution]

Hi Karl,

# echo "selclass qualifier cpu;infolog" | /usr/sbin/cstm | grep CPU

In you case it will probable br PA-RISC 8700 cpu's

0.18 micron line width

PA-8700 (PCX-W2) (Piranha)
Used in
A400-6X , A400-7X (rp2430), A500-6X, A500-7X (rp2470), C3650, C3700, C3750
J6700
L1000-7X, L1000-8X (rp5400), L2000-7X, L2000-8X (rp5450),
L1500-6X, L1500-7X, L1500-8X (rp5430), L3000-6X, L3000-7X, L3000-8X (rp5470)
N4000-6X, N4000-7X, N4000-8X (rp7400, rp7405, rp7410)
Superdome
rp7410
more ...
Time of introduction
August 2001

Overview
The PA-8700 is also basically just an enhanced and revamped PA-8500 core with some slight modifications. As all PA-8x00 CPUs before, it logically still is very close to the original PA-8000 core from 1997. All subsequent new CPUs from HP were based on this design and added several features and some slight modifications to it while retaining the basic PA-RISC version 2.0 core. The PA-8700 enhanced the on-chip L1 caches and the TLB significantly while jumping to a new CMOS-process helped to boost the clock-frequency. The chip was at its time one of the largest available commercial CPUs and one of the first to be manufactured in a SOI process. The PA-8700 was manufactured by IBM, in contrast to the PA-8500 and PA-8600, which were fabbed by Intel, since HP gave up its fabs a long time ago. (Though HP supposedly still manufactures a lot of custom ASICs)

Details
PA-RISC version 2.0 64-bit
10 functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 FP multiply/accumulate units, 2 FP divide/square root units
4-way superscalar
2 address adders
240-entry fully-associative dual-ported TLB
32-entry BTAC (branch target address cache)
2048-entry BHT (branch history table)
dynamic and static branch prediction modes
on-chip L1 caches 0.75MB I and 1.5MB D, each 4-way set associatve, implemented in independent 0.75MB banks.
32 or 64 Byte cache line size
Data cache prefetching
Quasi LRU replacement policy for both the instruction and data cache.
Supports up to 16 TB of physically addressable memory (44-bit physical addresses)
56-entry instruction queue/reorder buffer (IRB)
bi-endian support
Support for hardware lock-stepping, i.e. operating multiple chips in parallel to detect faults
Runway system/memory bus, 125MHz, 64-bit, DDR (double data rate), ~2GB/s peak bandwidth
Up to 750MHz (875MHz on the PA-8700+) frequency with 1.5V core voltage
16.0 x 19.0 mm2 die, 186'000'000 FETs, 0.18 micron, 7-layer SOI CMOS packaged in a 544-pin LGA package

Regards,
Robert-Jan

[Karl_]

Thank you very much Robert for your straight forward ansewer.

Best regards,

Karl