You're trying to compare apples to alligators. A RISC machine has just a few dozen unique instructions while CISC (like a Pentium) has hundreds of instructions which translates into highly variable instruction completion time. RISC is quite easy to provide pipelined instruction execution which means that 3 or 4 (or more) instructions are being executed at the same time. Now this isn't parallel execution (they don't start at the same time) but overlapped execution. One instruction is being fetched, a previous instruction is obtaining register data, and another is performing aritmetic tasks and another is storing the results, etc. This means that optimization and getting more than one instruction to run per clock cycle is fairly easy.
On the other hand, large instruction and data caches and similar overlapping instruction techniques in Pentium chips can narrow the differences. One thing that is quite difficult to do is to compare clock speeds directly. You will usually find (in compute-bound programs) that RISC accomplishes more per clock cycle, and that the equivalent CISC chip will need a faster clock speed to match a given RISC clock speed.
But all of this is smoke and mirrors until you define what the real load will be. PC-based processors suffer from tremendous legacy designs for I/O and it is much harder to find boxes that can handle massive I/O. On the other hand, most RISC machines require proprietary I/O cards. So until you define the goal: arithmetic (ie, floating point) processing, database processing (disk and memory) or web services, etc, it will be difficult to compare the hardware performance.
Bill Hassell, sysadmin
